ΣAD -RFDAC - High-Speed Continuous-Time Bandpass ΣAD Modulator Architecture Employing Sub-Sampling Technnique with 376-8515 1-5-1 Masafumi Uemori Tomonari Ichikawa Haruo Kobayashi Department of Electronic Engineering, Faculty of Engineering, Gunma University Tel: 277-3-1788 Fax: 277-3-177 e-mail:{a1e6,k haruo}@el.gunma-u.ac.jp AD ΣAD RF DAC. RFDAC DAC AD. MATLAB. Σ I LAN, AD ΣAD [1]-[6]. ΣAD DAC DAC RF AD. RF AD ( 1 II ΣAD AD BPF BPF LNA LNA BP ADC I Q LP ADC LP ADC DSP DSP 1:. 2: ΣAD 3. 3: () (. ADC DAC AD ΣAD DAC.
3 4 2 2 4 4: () (). III ΣAD ( ) (f c ) 4 ( =4f c )[7]. ADC, DAC ( ) 4 1 (f c = 1 4 ADC, DAC. ( ) (f c ) 3 4 (f c = 3 4 4 3 3 (f c = 3 4 f 1 2 1 2 f ( 4 LSI. [4]. IV ΣAD DAC NRZ(Non-Return-to-Zero) DAC. MATLAB ( 5 3 4.. DAC DC 3 4. 5 7 ΣAD 1. DAC RTZ DAC 24 Lucent RTZ(Return-to-Zero) DAC [4]. MATLAB DAC 25% RTZ DAC 6 3 4. RTZ DAC AD. (DAC RTZ 1 2 NRZ DAC ( 8) DAC 24 MIT Radio-Frequency Digital-to-Analog Converter(RF DAC) [8]. DAC 1 1 DAC. DAC DC DC 3 4.. MATLAB 3 4 ( 7 DAC (ddac out /dt =). [8] DAC ΣAD. ΣAD
-4-8 -12-16.5.6.7.8.9 1 Frequency[fs] 5: DAC ΣAD. -4-8 -12-16.5.6.7.8.9 1 Frequency[fs] 6: DAC25%RTZ DAC ΣAD. -4-8 -12-16.5.6.7.8.9 1 Frequency[fs] 7: DAC ΣAD. 25% RTZ DAC 8: DAC (1bit DAC fin 3 4 = fs + - ADC fs RFDAC 9: ΣAD.. ΣAD DAC. (i) ADC, DAC 4 3. 3. (ii) DAC AD. Σ.... V 1, 25%RTZ DAC, 8 DAC. DAC k (k =, ±1 ± 2, ±3,... 1 : D out,nrz (t) 1 (for k : D out,nrz (t) 1 (for k. 1 : D out,rf (t) =A 1 (t) (for k /2 ) D out,rf (t) =A 2 (t) (for k+1/2 : D out,rf (t) =A 2 (t) (for k /2 ) D out,rf (t) =A 1 (t) A 1 (t) = 1 2 cos{2π(2)t} + 1 2 A 2 (t) = 1 2 cos{2π(2)t} 1 2. (for k+1/2
D in=1 time -1 DAC GAIN 25% RTZ DAC 25% RTZ DAC (a) 1 Gain -2-3 -4 D in = time 25% RTZ DAC -5 3 1 2 3 4 4 Frequency(Fs) 12: DAC. (b) 1: DAC (1bit DAC. Data fs Switch Driver fosc Iout Iout 11: 1bit. 1 1 1 2 A 1 (t) A 2 (t) 1 2 A 2 (t) A 1 (t). cos{2π(2 )t} ( 11, [8] 12 3 4 DC. 9 3 4. k =, ±1, ±2, ±3,.... A 1 ( k 2 )=, A 2 ( k 2 )=, (1) da 1 dt t=( k 2fs ) =, da 2 dt t=( k ) =. (2) 2fs [9]. fs 4 3 ADC CLK fs 1bit ADC 1bit DAC CLK fs 13:. VI ΣAD MATLAB 13. ΣAD DAC 1bit 3 4 2 f in 3 4. ω c =2π( 3 4 ), b 1 = 1.5 3 ω c, b 2 = 5 3 ω c (3).( 1.) 14 3 4. 15 15dB/oct 2 ΣAD. DAC ΣAD DAC RFDAC 25% RTZ DAC[4] ( 1)DAC ±1%. 16(a) 16(b)
-2-6 -1-14 -18.5.6.7.8.9 1 14: DAC ΣAD. 1 8 6 4 2 1 2 3 4 5 6 7 8 15: DAC ΣADOSR. 1 8 6 4 2 1 2 3 4 5 6 7 8 1 8 6 4 2 Jitter 1% Jitter (a) Jitter 1% Jitter 1 2 3 4 5 6 7 8 (b)25% RTZ DAC 17: DAC DAC DAC CLK ΣAD. -2-6 -1-14 Output Power spectrum Jitter 1% Jitter -18.73.74.75.76.77-2 -6-1 -14 (a) Output Power spectrum Jitter 1% Jitter -18.73.74.75.76.77 (b)25% RTZ DAC 16: DACDACDAC CLK ΣAD.. RTZ DAC. OSR 17(a) 17(b). 25% RTZ DAC SNR. VII ΣAD ΣAD DAC,ADC DAC,ADC ΣAD ( 18 AD. 3bitRFDAC 19. 3bit DAC 1bit 1 1
fs 4 3 ADC CLK fs 3bit ADC 3bit DAC CLK fs 18: 3bit ΣAD. 19: () 3bit ( -2-4 -6-8 -1-12 -14-16 1bit -18 3bit -2.65.7.75.8.85 12 1 8 6 4 2 1bit 3bit 1 2 3 4 5 6 7 8 2: ADC,DAC3bitADC, ΣAD ()OSRSNR( 3 4 2 f in 3 4. ω c =2π( 3 4 ), b 1 = 3 3 ω c, b 2 = 18 3 ω c (4). ADC,DAC 3bit ADC, 2 1bit 2 SNR OSR 2 5 27dB DAC AD [6]DWA. VIII ΣAD DAC RFDAC.. ADC, RFDAC 2.. ΣAD ADC DAC Excess Loop Delay [5] AD.. () (STARC). [1] F. Munoz, K. Philips, A. Torralba, A 4.7mW 89.5dB DR CT Complex Σ ADC with Built-in LPF, ISSCC Digest of Technical Papers, vol.47, pp.5-51 (Feb. 24 [2] R. Schreier, J. Lloyd, L. Singer, D. Paterson, M. Timko, M. Hensley, G. Patterson, K. Behel, J. Zhou, A 1-3MHz IF-digitizing IC with 9-15dB dynamic range and 15-333kHz bandwidth, IEEE Journal of Solid- State Circuits vol.37, pp.1636-1644 (Dec. 22 [3] T. Salo, T. Hollman, S. Lindfors, K. Halonen, A Dual-Mode 8MHz Bandpass Σ Modulator for a GSM/WCDMA IF-receiver, ISSCC Digest of Technical Papers, vol.45, pp.218-219 (Feb 22 [4] U.V. Kack, J. Lee, Direct RF Sampling Continuous- Time Bandpass ΣAD Converter Design for 3G Wireless Applications, Proc. of IEEE ISCAS, Vancouver, Canada (May 24 [5] P. Fontaine, A. N. Mohieldin, A. Bellaouar, ALow- Noise Low-Voltage CT Σ Modulator with Digital Compensation of Excess Loop Delay, ISSCC Digest of Technical Papers, vol.47, pp.498-499 (Feb. 24 [6] H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa, A noise-shaping algorithm of multi-bit DAC nonlinearities in complex bandpass ΣAD modulators, IEICE Trans. on Fundamentals, vol.e87-a, no.4, pp.792-8 (April 24 [7] S. R. Norsworthy, R. Schreier, G. C. Temes (editors), Deta-Sigma Data Converters, - Theory, Design and Simulation, IEEE Press (1997 [8] S. Luschs, R. Schreier, H.-S. Lee, Radio Frequency Digital-to-Analog Converter, IEEE Journal of Solid- State Circuits, vol.39, no.9, pp.1462-1467 (Sept. 24 [9] H. Kobayashi, K. Kobayashi, M. Morimura, Y. Onaya, Y. Takahashi, K. Enomoto, and H. Kogure, Sampling Jitter and Finite Aperture Time Effects in Wideband Data Acquisition Systems, IEICE Trans. on Fundamentals, vol. E85-A, no. 2, pp.335-346 (Feb. 22