1.5 Gbps 4x4 LVDS Crosspoint Switch Literature Number: JAJS984
1.5Gbps 4 4 LVDS 4 4 (LVDS) ( ) 4 4:1 4 1 MODE 4 42.5Gb/s LVDS 20010301 33020 23900 11800 ds200287 2007 12 Removed preliminary. Removed old CP44 pin names and replaced with updated CP04 pin names. Removed TBD from jitter note in AC table. removed incorrect artwork, included correct order numbers, and changed all references from Vss to GND. No limit changes (LMS) removed duplicate colspec from thead in table 3 updated limits (LMS) changed datasheet title in pid source to match document title converted to nat2000 and removed application division saying TBD Converted to nat2000 DTD correct pkg added, format errors corrected (JFG) new datasheet to be created by RRD) DC 1.5Gbps LVDS LVPECL 2.5V-CML TRI-STATE LVDS 2 2.5V 6 6mm LLP-32 CMOS 1.5Gbps 4 4 LVDS 20021023 National Semiconductor Corporation DS200287-09-JP 1
( ) Order Number TLQ, TLQX (Tape and Reel) See NS Package Number LQA32A 2
IN1 IN1 16 15 I, LVDS IN2 IN2 IN3 IN3 IN4 IN4 14 13 12 11 10 9 OUT1 OUT1 25 26 OUT2 27 OUT2 28 OUT3 29 OUT3 30 OUT4 31 OUT4 32 I, LVDS I, LVDS I, LVDS O, LVDS IN1 IN2 IN3 IN4 OUT1 O, LVDS IN1 IN2 IN3 IN4 OUT2 O, LVDS IN1 IN2 IN3 IN4 OUT3 O, LVDS IN1 IN2 IN3 IN4 OUT4 SCLK 6 I, LVCMOS SI SCLK 0MHz 100MHz SCLK SCLK LOW SI / SEL1 7 I, LVCMOS SCLK SEL0 5 I, LVCMOS CSO RSO CSCLK RSCLK 18 2 19 3 O, LVCMOS MODE LOW CSO (RSO) CSO (RSO) SI ( ) 1 CSO (RSO) SCLK O, LVCMOS MODE LOW SCLK CSCLK(RSCLK) LOAD 22 I, LVCMOS LOAD HIGH SCLK LOW HIGH LOAD 1 SCLK HIGH LOAD HIGH MODE 23 I, LVCMOS MODE LOW SCLK SCLK CSCLK/RSCLK MODE HIGH SCLK MODE LOW POWER V DD 1, 8, 17, 24 I, Power V DD 2.5V 5 4 ESR 0.01 F V DD GND GND 4, 20, 21, I, Power LVDS CMOS LLP-32 DAP DAP DAP AC 4 3
LOAD MODE SCLK 0 0 LH SI 0 1 LH SCLK MODE LOW RSCLK CSCLK LOW LH 0 X OUT1 OUT4 SCLK 1 1 LH SCLK MODE LOW RSCLK CSCLK LOW MODE SEL1 SEL0 0 X X SEL0/1 1 0 0 : IN1 - OUT1 OUT2 OUT3 OUT4 1 0 1 : IN2 - OUT1 OUT2 OUT3 OUT4 1 1 0 : IN1 - OUT1 OUT2 IN3 - OUT3 OUT4 1 1 1 : IN1 - OUT1 IN2 - OUT2 IN3 - OUT3 IN4 - OUT4 LH: LOW HIGH ( ) X: 4
( ) FIGURE 1. Configuration Select Decode 5
(Note 1) (V DD ) 0.3V 3V CMOS/TTL 0.3V (V DD 0.3V) LVDS 0.3V 3.3V LVDS 0.3V 3V LVDS 40mA 150 65 150 ( 4 ) 260 25 LLP-32 3200 mw 25 38mW/ JA 26.4 /W ESD 1.5k 100pF LVDS 1.0kV LVDS 1.5 V 4.0 V EIAJ 0 200pF 100V (V DD GND) 2.375 2.5 2.625 V 0.05 3.3 V 40 25 85 110 6
( ) 7
( ) Note 1: Note 2: Note 3: Note 4: Note 5: V DD 2.5V T A 25 V OD OUT OUT V ID IN IN V OS LVDS HIGH LOW 1 LVDS 3 1.25Gb/s K28.5 1,000 K28.5 0011111010 1100000101 (DJ ) 350 (TJ) 3,500 FIGURE 2. Differential Driver DC Test Circuit 8
( ) FIGURE 3. Differential Driver AC Test Circuit FIGURE 4. LVCMOS Driver AC Test Circuit (Note 6) 9
( ) Note 6: LVCMOS AC Figure 4 FIGURE 5. LVDS Signals FIGURE 6. LVDS Output Transition Time FIGURE 7. LVDS Output Propagation Delay 10
( ) FIGURE 8. Serial Interface Propagation Delay and Input Timing Waveforms FIGURE 9. Serial Interface MODE Timing and Functionality 11
( ) FIGURE 10. Configuration and Output Enable/Disable Timing SCLK SI (RSCLK RSO) (CSCLK CSO) RSCLK RSO CSCLK CSO (SCLK SI) 30 6 SI 1FH 1EH 2 4 Table 1 Table 2 D29 SI TABLE 1. 30-Bit Control Word D29 D24 6 (01 1111'b LOAD) D23 D18 6 64 D17 D12 6 64 D11 D9 3 1 Table 2 D8 D6 3 2 Table 2 D5 D3 3 3 Table 2 D2 D0 3 4 Table 2 TABLE 2. Switch Configuration Data MSB LSB OUT1 OUT2 OUT3 OUT4 0 0 0 1 TRI-STATE 2 TRI-STATE 3 TRI-STATE 4 TRI-STATE 0 0 1 IN1 IN1 IN1 IN1 0 1 0 IN2 IN2 IN2 IN2 0 1 1 IN3 IN3 IN3 IN3 1 0 0 IN4 IN4 IN4 IN4 1 0 1 12
( ) TABLE 2. Switch Configuration Data ( ) MSB LSB OUT1 OUT2 OUT3 OUT4 1 1 0 1 1 1 N N 1 N 1 N (SCLK SI) 1 1 (CSO CSCLK) 1 (RSO RSCLK) (D29 24 01 1111'b 01 1110'b) 30 LOAD HIGH LOAD 2 SCLK RSO CSO 7 (SCLK) 4 Table 3 (OUT1 IN1 OUT2 IN2 OUT16 D29:D24 D23:D18 D17:D12 IN16) 4 30 120 TABLE 3. Example to Program a 4 Device Array OUT1 D11:D9 OUT2 D8:D6 (01 1110'b) OUT1 OUT4 RSO CSO (11 1111'b) RSO CSO SI Table 4 4 4 4 SCLK 4 30 4 30 SCLK 1 7 SCLK SCLK 148 RSO RSCLK 4 SI LOW OUT3 D5:D3 OUT4 D2:D0 SCLK 01 1111 00 0000 00 0011 001 010 011 100 30 0, 3 01 1111 00 0000 00 0010 001 010 011 100 30 0, 2 01 1111 00 0000 00 0001 001 010 011 100 30 0, 1 01 1111 00 0000 00 0000 001 010 011 100 30 0, 0 SI 2 2 13
( ) D29:D24 D23:D18 TABLE 4. A Read-Back Example from a 4 Device Array D17:D12 OUT1 D11:D9 OUT2 D8:D6 OUT3 D5:D3 OUT4 D2:D0 SCLK 01 1110 00 0000 11 1111 000 000 000 000 30 01 1110 00 0000 11 1110 000 000 000 000 30 01 1110 00 0000 11 1101 000 000 000 000 30 01 1110 00 0000 11 1100 001 010 011 100 30 Read-Back (R,C) 0, 3 Read-Back (R,C) 0, 2 Read-Back (R,C) 0, 1 Read-Back (R,C) 0, 0 Note 7: Figure 11 16 16 RSO RSCLK CSO CSCLK LOAD LOAD LOAD FIGURE 11. 14
30 : [ ][ ][ ][OUT1][OUT2][OUT3][OUT4] [01 1111] [0][1] [1][1][1][1] //* 1 IN1 *// [01 1111] [0][0] [2][2][4][4] //* 0 IN2 OUT1 OUT2 IN4 OUT3 OUT4 *// LOAD H SCLK LH 0 SCLK 6 0 (R 0 C 0) 1 18 0 (R 0 C 0) 1 1 0 1 1 ( 0) RSO 36 0 (R 0 C 0) 2 48 0 (R 0 C 0) 2 0 0 0 60 0 (R 0 C 0) LOAD 1 SCLK 13 1 (R 1 C 0) 1 25 1 (R 1 C 0) 2 0 0 1 37 1 (R 1 C 0) LOAD 43 1 (R 1 C 0) 2 55 1 (R 1 C 0) 2 3F 0 2 1 ( 3E) RSO 30 : [ ][ ][ ][OUT1][OUT2][OUT3][OUT4] [01 1110] [1][0] [0][0][0][0] //* 1 *// [01 1110] [0][0] [0][0][0][0] //* 0 *// 15
( ) 0 SCLK 6 0 (R 0 C 0) 1 18 0 (R 0 C 0) 1 1 0 1 1 ( 0) RSO 36 0 (R 0 C 0) 2 48 0 (R 0 C 0) 2 0 0 0 1 ( 3F) RSO 60 0 (R 0 C 0) 74 ( 1 RSO) 1 SCLK 13 1 (R 1 C 0) 1 25 1 (R 1 C 0) 1 0 0 1 1 1 ( 3F) RSO 37 1 (R 1 C 0) ( 1 RSO) 16
millimeters LLP, Plastic, QUAD, Order Number TLQ, TLQX (Tape and Reel) NS Package Number LQA032A 1.5Gbps 4 4 LVDS (CEO) (GENERAL COUNSEL) a (b) National Semiconductor Copyright 2008 National Semiconductor Corporation www.national.com 135-0042 2-17-16 / TEL.(03)5639-7300 www.national.com/jpn/
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