1. 3 1.1.....3 1.2... 3 1.3... 5 2. 6 3. 8 4. Beryll 9 4.1... 9 4.2... 9 4.3... 10 4.4... 10 5. Beryll 14 5.1 Cyclone V GX FPGA... 14 5.2 FPGA ROM...

Mpression Beryll Board Revision 1.0 2014/2 2014/2 Mpression by Macnica Group http://www.m-pression.com

1. 3 1.1.....3 1.2... 3 1.3... 5 2. 6 3. 8 4. Beryll 9 4.1... 9 4.2... 9 4.3... 10 4.4... 10 5. Beryll 14 5.1 Cyclone V GX FPGA... 14 5.2 FPGA ROM... 14 5.3 ROM... 16 5.4... 19 5.5... 22 5.6 DDR3 SDRAM... 22 5.7 FLASH / SRAM... 24 5.8 USB 2.0... 25 5.9 10 / 100... 26 5.10 24... 27 5.11... 28 5.12... 29 5.13... 31 6. 32 7. 33 2 - Mpression Beryll Board Mpression by Macnica Group

1. 1.1 1.2 AC ( ) AC AC AC 5 35 0% 85% AC - Mpression Beryll Board 3 Mpression by Macnica Group

() 4 - Mpression Beryll Board Mpression by Macnica Group

1.3 1 222-8563 1-5-5 Web 1.4 Web http://www.m-pression.com/ja/contact - Mpression Beryll Board 5 Mpression by Macnica Group

2. Cyclone V GX FPGA Getting Started FPGA USB SD LAN RMA 30 6 - Mpression Beryll Board Mpression by Macnica Group

- Mpression Beryll Board 7 Mpression by Macnica Group

3. 30 Customer letter Beryll USB A to Mini-B AC ( 12V) Beryll FPGA URL 8 - Mpression Beryll Board Mpression by Macnica Group

4. Beryll 4.1 FPGA Cyclone V GX FPGA FPGA A. Cyclone V GX FPGA B. ( HSMC ) C. On-Board USB-Blaster USB FPGA D. Cyclone V FPGA HMC () DDR3 4.2 1 FPGA Power Supply Dimensions HSMC Printed Circuit Board Configuration ROM SRAM DDR-SDRAM Flash ROM USB 2.0 (Mini-B) Audio Ethernet Clock (for FPGA) JTAG Connector Status LED FPGA Reconfiguration Push SW General-purpose LED General-purpose Push SW General-purpose Dip SW General-purpose 7 Segment LED Character LCD Connector Power SW RS-232C 1 Beryll 5CGXFC4C6F27C DC 12 V 3.8 A 140.00 mm x 155.00 mm ASP-122953-01 FR4 10-layer EPCS128SI16N IDT71V416S10PHG8 (512 KByte) DDR3-800 256 MBytes (128 MByte x 2) MT41J64MJT JS28F256M29EWLA (32 MByte) CY7C68013A-56LTXC UDA1345TS DP83865DVH 27 MHz x 1, 33 MHz x 1, 50 MHz x 1, 125 MHz x 1 DIP 10-pin Header, 2.54-mm pitch 1 12 pcs (12V_POWER, HSMC PSNTn, nstatus, nconfig, CONF_DONE, INIT_DONE, Blaster, ACT,LK10,LK100,LK1000,DUPLEX) 1 (SYS_RESET) 8 4 1 (SW0-SW3) 2 1 (3.3-V) * A character LCD is optional. 1 DB9 Female Connector LCD LCD LCD - Mpression Beryll Board 9 Mpression by Macnica Group

4.3 1 Cyclone V GX FPGA Cyclone V GX FPGA 1 Beryll 4.4 4.4.1 Beryll / 2 Beryll, 10 - Mpression Beryll Board Mpression by Macnica Group

4.4.2 Beryll 3 3 Beryll - Mpression Beryll Board 11 Mpression by Macnica Group

4.4.3 Beryll / LED 4 / LED 4 LED 2 LED 2 LED 12 - Mpression Beryll Board Mpression by Macnica Group

3 3 - Mpression Beryll Board 13 Mpression by Macnica Group

5. Beryll FPGA 5.1 Cyclone V GX FPGA 28nm FPGA Cyclone V GX Cyclone V GX FPGA 4 4. Cyclone V GX FPGA Specification IP LE (Kb) MLAB (Kb) DSP PLL GPIO LVDS PCIe 5CGXC4 50K 250 2,500 295 70 6 6 336 90 2 2 5.2 FPGA FPGA EPCS USB (U27) On-Board USB-Blaster USB-Blaster 5.2.1 Quartus II Programmer Configuration file 5.2.2 FPGA A. Programmer Quartus II Tools Programmer 14 - Mpression Beryll Board Mpression by Macnica Group

B. Mode JTAG C. a. Hardware Setup b. Hardware Setup Hardware Settings c. Current selected hardware Add Hardware d. Add Hardware Hardware type USB-Blaster OK e. Hardware Setup Currently selected hardware USB-Blaster Close D. a. (*.SOF) b. Program / Configure c. POF *.pof MAX CPLD SOF *.sof Stratix FPGA Arria FPGA Cyclone FPGA FPGA JIC *.jic Program / Configure Verify Programmer - Mpression Beryll Board 15 Mpression by Macnica Group

Blank-Check Examine MAX CPLD Security Bit () Examine Security Bit Examine MAX 7000 MAX 3000 Erase MAX CPLD ISP CLAMP IPS *.ips I/O MAX 7000B MAX II 5.3 EPCS configuration ROM 5.3.1 FPGA JTAG Indirect Configuration ( JIC) JTAG EPCS JTAG 5.3.2 JIC Cyclone V FPGA EPCS (AS ) AS EPCS AS 10 FPGA JTAG SignalTap II JTAG 10 JIC FPGA EPCS JTAG AS 10 16 - Mpression Beryll Board Mpression by Macnica Group

5.3.3 EPCS SOF POF JIC FPGA SOF JIC 1 2 JIC 3 1. JIC (.sof) Processing Start Compilation 2. JIC SOF JIC *.jic 1) File Convert Programming Files 2) Output Programming File Programming file type JTAG Indirect Configuration File (.jic) Configuration device EPCS128 File name Input files to convert FPGA Flash Loader Add Device Select Device Device family Cyclone V GX Device name OK JIC (.sof) SOF Data Add File sof SOF - Mpression Beryll Board 17 Mpression by Macnica Group

Properties SOF File Properties Compression OK Generate Generated <jic > successfully JIC 3. JIC EPCS JTAG 1) Programmer Tools Programmer 2) Mode JTAG 3) JIC 4) JIC Program/Configure 5) FPGA EPCS Progress Programmer 100% Message JTAG Indirect Configuration EPCS 18 - Mpression Beryll Board Mpression by Macnica Group

5.4 4 4. Beryll 01. U35 (DC ) 02. U20 (USB 2.0_CONN) 03. U17 (ENET_CONN) 04. J3 (Audio ) - Mpression Beryll Board 19 Mpression by Macnica Group

05. J4 (Audio ) 06. J2 (SMA CLKIN) 07. J1 (SMA CLKOUT) 08. U27 (USB-Blaster) 9. J6 (RS232C DSub9 ) 10.J5 ( LCD) 20 - Mpression Beryll Board Mpression by Macnica Group

11. J8 (HSMC ) - Mpression Beryll Board 21 Mpression by Macnica Group

5.5 1 RS232C LTC2803 FPGA 9 D SUB FPGA LTC2803 D SUB 5 LTC2803 URL * 5. FPGA LTC2803 DB9 5. RS232C FPGA LTC2803 FPGA LTC2803 (D-SUB D-SUB UART_XD Bank 8A_K6 14 3 2 UART_RXD Bank 8A_L7 16 1 3 5.6 DDR3 SDRAM MT41J64M16JT (16bit, 128MByte, 800MHz) 2 FPGA HMC () Cyclone V GX FPGA Cyclone V GX FPGA DDR3 6 MT41J64M16JT, URL * * DDR3 DDR3 800MHz 22 - Mpression Beryll Board Mpression by Macnica Group

6 FPGA DDR3 6. FPGA DDR3 - Mpression Beryll Board 23 Mpression by Macnica Group

5.7 FLASH / SRAM JS28F256M29EWL (16bit, 256Mbits)FLASH ROM IDT IDT71V416S10PHG8 16bit 4Mbit SRAM FLASH / SRAM Cyclone V GX FPGA Nios II Nios II FLASH Nios II ROM SRAM FLASH SRAM FLASH SRAM FPGA 7 Flash ROM URL * SRAM URL * 7 FPGA FLASH/SRAM 24 - Mpression Beryll Board Mpression by Macnica Group

7. FPGA FLASH/SRAM 5.8 USB 2.0 USB2.0 EZ-USB CY7C68013A-56LTXC USB2.0 8051 USB 16KB RAM USB2.0 Cyclone V GX FPGA EZ-USB GPIF FPGA CY7C68013 8 EZ-USB URL * 8. FPGA EZ-USB - Mpression Beryll Board 25 Mpression by Macnica Group

8. FPGA EZ-USB 5.9 10/100 DP83865DVH DP83865DVH 1.8V, 0.18μ FPGA DP83865DVH 9 LSI URL * 9. FPGA DP83865DVH 26 - Mpression Beryll Board Mpression by Macnica Group

9. FPGA DP83865DVH 5.10 24 Audio 24bit CODEC NXP UDA1345TS FPGA DP83865DVH 10 URL * 10. FPGA UDA1345 - Mpression Beryll Board 27 Mpression by Macnica Group

10. FPGA UDA1345 5.11 8 LED 2 7 4 1 DIP LCD, UART ~ 11. 28 - Mpression Beryll Board Mpression by Macnica Group

5.12 5.12.1 FPGA 25-MHz, 50-MHz, 125-MHz 11. 11. - Mpression Beryll Board 29 Mpression by Macnica Group

12 I/O 12. I/O Cyclone V U7 CLK27M 27 MHz 3.3V T21 U8 CLK33M 33 MHz 1.8V T13 U10 CLK50M 50 MHz 1.8 U12 U11 CLK125M 125 MHz 1.8V P11 U3 DIFF0_P 100 MHz LVDS V6 DIFF0_N 100 MHz LVDS W6 U18 TSE_MAC_CLK 25 MHz 3.3V N20 PHY TSE_RX_CLK 25 MHz 3.3V R20 PHY U22 EZ_CLK 48 MHz 3.3V K25 USB 2.0 5.12.2 HSMC SMA 13 13. I/O Cyclone V HSMC HSMC_1_CLKIN 2.5V L8 HSMC. HSMC_2_CLKIN_P LVDS/ 2.5V H12 HSMC HSMC LVDS. 2 x 2.5V HSMC_2_CLKIN_N LVDS/ 2.5V G11. HSMC_3_CLKIN_P LVDS/ 2.5V G15 HSMC HSMC LVDS. 2 x 2.5V HSMC_3_CLKIN_N LVDS/ 2.5V G14. SMA SMA_CLKIN 2.5V N9 SMA 30 - Mpression Beryll Board Mpression by Macnica Group

14. 14. I/O Cyclone V HSMC HSMC_1_CLKOUT 2.5V A7 FPGA 2.5V ( GPIO) HSMC_2_CLKOUT_P LVDS/ 2.5V B15 HSMC HSMC HSMC_2_CLKOUT_N LVDS. 2 x 2.5V LVDS/ 2.5V C15. HSMC_3_CLKOUT_P LVDS/ 2.5V A23 HSMC HSMC HSMC_3_CLKOUT_N LVDS. 2 x 2.5V LVDS/ 2.5V A22. SMA SMA_CLKOUT 2.5V M9 SMA 5.13 12 LTC3605 - Mpression Beryll Board 31 Mpression by Macnica Group

6. 6.1 ( ) Quartus II 32 - Mpression Beryll Board Mpression by Macnica Group

7. 2014 2 1 0.1 1. 2. 3. Mpression 222-8561 1-6-3 HP: http://www.m-pression.com 4. 5. - Mpression Beryll Board 33 Mpression by Macnica Group