HardCopy IIデバイスのタイミング制約

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1 7. HardCopy II H Stratix II FPGA FPGA ASIC HardCopy II ASIC NRE Quartus II HardCopy Design Center HCDC Quartus II TimeQuest HardCopy II 2 DR2 TimeQuest TimeQuest FPGA ASIC FPGA ASIC Quartus II TimeQuest TimeQuest Synopsys Design Constraints SDC TimeQuest Quartus II Volume 3 TimeQuest Altera Corporation 7 1

2 HardCopy Volume 1 HardCopy II ASIC Stratix II FPGA TimeQuest HardCopy II Advisor Quartus II HardCopy II HardCopy II HardCopy II Stratix II HardCopy II ASIC Stratix II FPGA HardCopy II Quartus II Stratix II FPGA HardCopy II Stratix II HardCopy II I/O Stratix II HardCopy II HardCopy II Stratix II Stratix II ALM HardCopy II HCell HardCopy II HardCopy II SRAM HardCopy II HardCopy II 7 2 Altera Corporation

3 HardCopy II Stratix II FPGA Stratix II ALM HardCopy II HCell ALM HardCopy II HCell HCell Stratix II ALM MUX Stratix II ALM Stratix II FPGA ALM HardCopy II HardCopy II SRAM Stratix II 1 HardCopy II 5 6 SRAM SRAM HardCopy II Stratix II FPGA HardCopy II Stratix II HardCopy II Stratix II FPGA HardCopy II DSP Stratix II FPGA DSP DSP DSP DSP HardCopy II Altera Corporation 7 3

4 HardCopy Volume 1 DSP Stratix II DSP HCell DSP DSP HardCopy II Stratix II FPGA RAM Stratix II FPGA HardCopy II DSP RAM HardCopy II Stratix II FPGA I/O HardCopy II I/O Stratix II I/O I/O I/O 1 I/O I/O HardCopy II Stratix II I/O HardCopy II Stratix II HardCopy II PLL Stratix II FPGA HardCopy II ASIC Stratix II FPGA SRAM 7 4 Altera Corporation

5 HardCopy II PLL HardCopy II SRAM I/O I/O I/O Quartus II Stratix II FPGA HardCopy II ASIC I/O PLL Stratix II HardCopy II PLL Quartus II HardCopy II PLL PLL Stratix II FPGA HardCopy II ASIC HardCopy II HardCopy II ASIC Stratix II FPGA Quartus II Altera Corporation 7 5

6 HardCopy Volume 1 HardCopy II HardCopy Design Center HCDC HCDC ASIC Quartus II Quartus II Stratix II FPGA HardCopy II ASIC Stratix II HardCopy II ASIC HardCopy II HardCopy II Quartus II TimeQuest FPGA TimeQuest Quartus II TimeQuest TimeQuest TimeQuest TimeQuest SDC SDC Tcl GUI 7 6 Altera Corporation

7 HardCopy II HardCopy II TimeQuest HCDC Quartus SDC 7 1 Quartus II HardCopy II TimeQuest FPGA HardCopy II HardCopy II Stratix II Altera Corporation 7 7

8 HardCopy Volume Stratix II (1) Stratix II Revision Timing Constraints HardCopy II Revision Timing Constraints Stratix II Design Setup Compilation Constraint Coverage Checks Static Timing Analysis FPGA Prototyping HardCopy II Design Setup Compilation Constraint Coverage Checks Static Timing Analysis HardCopy II Structured ASIC Design FPGA Prototype Design Industry Standard SDC Timing Constraints Revision Comparison HardCopy Design Center Handoff 7 1 : (1) Stratix II HardCopy II TimeQuest SDC.sdc Quartus.qsf 7 1 Quartus II Stratix II FPGA TimeQuest TimeQuest Altera Corporation

9 HardCopy II TimeQuest Quartus II Synopsys PrimeTime Stratix II FPGA HardCopy II Stratix II FPGA HardCopy II Stratix II FPGA HardCopy II HardCopy II HardCopy II HardCopy II Stratix II TimeQuest Quartus II HardCopy II 1 Stratix II HardCopy II Stratix II FPGA Quartus II HCDC HardCopy II SDC Quartus II sdc HardCopy II Quartus II sdc Quartus II Quartus II sdc Quartus II Scripting Reference Manual Tcl Packages and Commands sdc Altera Corporation 7 9

10 HardCopy Volume 1 TimeQuest TimeQuest Quartus II HardCopy II TimeQuest HardCopy II HardCopy II Advisor TimeQuest HardCopy II Advisor TimeQuest TimeQuest report_ucp TimeQuest GUI Tasks Report Unconstrained Paths 7 10 Altera Corporation

11 HardCopy II TimeQuest HardCopy SDC TimeQuest Quartus II 2 Tcl sdc sdc_ext HardCopy II sdc SDC 1.5 Quartus II SDC sdc_ext SDC 1.5 TimeQuest HardCopy II SDC HCDC HardCopy Design Center sdc_ext Quartus II sdc sdc_ext Quartus II Scripting Reference Manual Tcl Packages and Commands sdc SDC and TimeQuest API Reference Manual Quartus II 7 3 Altera Corporation 7 11

12 HardCopy Volume TimeQuest TimeQuest Quartus II Volume 3 TimeQuest QuartusII 7 12 Altera Corporation

13 HardCopy II Quartus II HardCopyII HardCopy II Advisor HardCopy II HardCopy II Advisor Design Assistant HardCopy Hardware Design Considerations Design Guidelines for HardCopy Series Devices HardCopy II Advisor Quartus II 7 4 Enable Recovery/Removal Analysis / Enable Timing Constraints Check Report Combined Fast/Slow Timing / Report I/O Paths Separately I/O I/O Enable Clock Latency Enable Misc. Timing Assignments CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS OFF UCP PLL ON Altera Corporation 7 13

14 HardCopy Volume HardCopy II Advisor TimeQuest HardCopy II HardCopy II Advisor Check for Incompatible Assignments Remove Unsupported Global Timing Assignments Remove Unsupported Instance Timing Assignments 7 5 HardCopy II 7 23 HardCopy II Quartus II HardCopy II HCDC 7 14 Altera Corporation

15 HardCopy II 7 5. HardCopy II Advisor Altera Corporation 7 15

16 HardCopy Volume 1 Stratix II HardCopy II Timing Constraints Check 7 6 I/O 7 6. TimeQuest Quartus II 7 16 Altera Corporation

17 HardCopy HardCopy HardCopy HardCopy Design Center FPGA HardCopy FPGA HardCopy HardCopy SDC Quartus II SDC File Editor Constraints SDC SDC Quartus II Volume 3 TimeQuest TimeQuest Quartus II Volume 3 TimeQuest Quartus II Volume Altera Corporation 7 17

18 HardCopy Volume Clock Uncertainty Clock Period = 10.0 ns clk Rising Edge of Clock Falling Edge of Clock PLL PLL PLL PLL PLL set_clock_uncertainty PLL PLL FAE MySupport SDC PLL SDC # create_clock -period [get_ports clkin] #PLL derive_pll_clocks 7 18 Altera Corporation

19 HardCopy derive_pll_clocks sdc_ext HardCopy II sdc HCDC sdc generated_pll_clock API SDC and TimeQuest API Reference Manual 2 HardCopy FPGA External Device D Q dff Data Path Delay Primary Input to PLD/HardCopy Series Device Data Path Delay D dff Q External Input Delay HardCopy Device or FPGA 7 9 Altera Corporation 7 19

20 HardCopy Volume tsu for a Primary Input Port data Data Path Delay tsu clk Clock Delay th for a Primary Input data Data Path Delay th clk Clock Delay Altera Corporation

21 HardCopy 1 HardCopy External Device D Q dff Data Path Delay Primary Output from FPGA/HardCopy Series Device Data Path Delay D Q dff HardCopy Device or FPGA External Output Delay Tco Clock-to-Output T CO 7 12 T CO T CO Clock-to-Output (T co ) tco Data Path Delay output clk Clock Delay tco for a Primary Output Port Altera Corporation 7 21

22 HardCopy Volume input Data Path Delay output Combinational Delay Arc 2 HCDC HardCopy HardCopy 7 22 Altera Corporation

23 HardCopy II HardCopy II Quartus II HardCopy II HCDC SDC HardCopyII TSU Th TCO Min T CO T PD Quartus II HardCopy II Quartus II SDC HCDC HardCopy II Advisor Incompatible Assignments 7 5 SDC TimeQuest HardCopy II Quartus II HardCopy II HardCopy II Quartus II Altera Corporation 7 23

24 HardCopy Volume TCO Th TSU Min T CO HardCopy II 7 1. TSU TH TCO Minimum T CO (1) (2) (3) (4) (5) setup_relationship set_input_delay hold_relationship set_output_delay TSU Req TSU -max <TCK-TSU> Th Req -min Th -Th TCO Req TCO -max <TCK-TCO> Min T CO Req Min T CO -min <- Min T CO > 7 1 : (1) TSU = TSU (2) TCO = TCO (3) Th = Th (4) Min T CO = Min T CO (5) TCK = TSU TCO HardCopy II Quartus II Quartus II ASIC HardCopy Design Center HardCopy II 7 24 Altera Corporation

25 & v v2.0 Quartus II Quartus II HardCopy II TimeQuest TimeQuest 22 HardCopy HardCopy II v1.0 HardCopy Quartus II 6.1 TimeQuest HardCopy II TimeQuest HardCopy Altera Corporation 7 25

26 HardCopy Volume Altera Corporation

ネットリストおよびフィジカル・シンセシスの最適化

ネットリストおよびフィジカル・シンセシスの最適化 11. QII52007-7.1.0 Quartus II Quartus II atom atom Electronic Design Interchange Format (.edf) Verilog Quartus (.vqm) Quartus II Quartus II Quartus II Quartus II 1 Quartus II Quartus II 11 3 11 12 Altera