FPGA SATA AE/
AVNET, INC. : 1921 : 1955 / : 1960 NYSE - AVT ( Sector : Technology ) CEO: Roy Vallee ( : : : 11,000 : KPMG LLP : 6 30 Fortune 500 ( 2006 212 ) InformationWeek 500 ( 2004 3 ) Fortune Top50 Fastest Growing Companies ( 2002 )
AVNET JAPAN 1983 4 1 160 ( ) IP
SATA HDD SATA HDD SATA PC SATA 4 PC 3Gbps 1 PC esata 2m PC PC HDD/PC PC SATA
SATA SATA SATA SATA FPGA FPGA SATA /
SATA
ATA SATA ATA ATA SATA FIS Frame Information Structure FIS FIS ATA
FIS Register Host to Device (Reg HD) FIS 27h
FIS Register Device to Host (Reg DH) FIS 34h
FIS Data FIS 46h
SATA IDENTIFY DEVICE ATA Device/Head ECh 1 SATA RegHD FIS Device Command Ech PIOSU FIS RegDH DataDH FIS 1
RegHD FIS PIOSU FIS DataDH FIS
SATA
8b/10b 10b/8b 8b/10b 8bit 10bit 3Gbps 300MB/s H L DC 8bit 10b K 8bit 1bit 10bit 5bit 3bit Dxx.x Kxx.x 10000 010 D16.2 K K16.2
SATA 4 K
ALIGN - 256DWORD SOF, EOF FIS SOF EOF R_OK, R_ERR R_OK CRC R_ERR HOLD, HOLDA FIFO / HOLD HOLD 20DWORD HOLDA 2m 1Dword
CRC/ CRC CRC FIS EMI Liner Feedback Shift Register (LFSR) XOR
SATA
Out-of-Band (OOB) P N / / 3 106.7ns 106.7ns ALIGN ALIGN ALIGN ALIGN ALIGN ALIGN ALIGN ALIGN ALIGN ALIGN 320ns COMRESET/COMINIT 106.7ns COMWAKE
OOB
FPGA SATA
FPGA SATA GTP/GTX SATA FPGA SATA GTP/GTX FPGA IP SATA Gen2 SATA Gen 1/2 XAPP870 GTP
DesignGateway SATA IP Virtex-5 LXT SATA IP ML505 Xilinx Virtex5 Microblaze SATA-II Host IP BRAM Interface Host I/F Transport Layer Link Layer Peripherals MPMC2 Memory Controller PIM I/F DMA Table FIS I/F FIFO FIFO CRC Descrambler Scrambler FIFO SATA-II PHY I/F RocketIO GTP SATA-II HDD Memory Mapped I/O Host Clock 75MHz SATA FIS I/F 150MHz 150MHz
8b/10b,,CRC CPU esata HOLDp HOLDAp 18DWords 2m 1Dword 20Dwors 50cm SATA
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/ FPGA FIS FIS CPU CPU DMA SATA IP DMA DMA Data FIS FIS DMA CPU 2008 11
FPGA ATA Avnet JAPAN-XILINX@Avnet.com Web HDD RAID FPGA SATA Viretx-5 ML505/ML506