LMH0340,LMH0341 Literature Number: JAJA432
SIGNAL PATH designer Tips, tricks, and techniques from the analog signal-path experts No. 113... 1-5...4... 7 1080p60 3Gbps SDI Mark Sauerwald, SDI Applications Engineer, National Semiconductor / Bob Feng, Spartan Applications Engineer, Xilinx SDI
SIGNAL PATH designer 1080p60 3Gbps SDI SDI : 20GHz Tektronix CSA8000 : PRBS 2 15-1 : 2.97Gbps Figure 1. LMH0340 3Gbps : 30ps Table 1. Smart SerDes LMH0340 LMH0341 LMH0040 LMH0041 / / 3G 2.97G 1.485G 3G 2.97G 1.485G HD 1.485G HD 1.485G LMH0050 HD 1.485G LMH0051 HD 1.485G LMH0070 / LMH0071 SMPTE 424M 424M SD SD (UI)... 1000.0 100.0 10.0 1.0 0.1 1.0E+3 10.0E+3 : 2.97 G bps : Agilent J-BERT 100.0E+3 LMH0341, 2.97G SMPTE 1.0E+6 Figure 2. LMH0341 10.0E+6 100.0E+6 2
SIGNAL PATH designer : EMI VC : 1.485 G bps FPGA 20 TTL HD-SDI SDI : ~ 115 ps : EMI LMH0340 LMH 0340 SDI : 2.97 G bps FPFA 5LVDS + 3G-SDI / : 50 ps Figure 3. SDI Spartan signalpath.national.com/jpndesigner 3
SD/HD national.com/jpn/amplifiers LMH198150% ADC12L080 LMH1981 LMH1982 350ps LMH1981 50 NTSC PAL SECAM 480i 480p 576i 576p 720p 1080i1080p 0.5V P-P 2V P-P C 60ns LMH1981 Odd/Even 5V A/V /SDI national.com/jpn/amplifiers 4
SIGNAL PATH designer 1080p60 3Gbps SDI SERDES IP Table 2. FPGA SERDES SD-SDI 27 MHz 27 MHz HD-SDI 148.5 MHz 74.25 MHz 3G-SDI 297 MHz 148.5 MHz 20:5/5:20 LVDS SerDes CLK DCM CLKx2 CLKx2not D0 D1 CLK_P D+ D - CLK - CLK CLK_N CLK+ 20 - bit D+ D - Alignment = C0/C1 D0 D1 CLK - CLK+ DCM CLKx2 CLKx2not 20 - bit Figure 4. Spartan-3E FPGA SERDES signalpath.national.com/jpndesigner 5
SIGNAL PATH designer R x Clk R x LVD Data (5) Reset LVDS Interface (5 to 20 DeMux) LVDS Interface 27 MHz 150 MHz 300 MHz PL L 20-bits SDI EVK IP Descramble SDI Blocks 27 MHz (SD) 75 MHz 150 MHz (3G) Word Align LN, CRC, Extract Control Interface 10-bit C, 10-bit Y Lock T x CIk TLVDS Data (5) Reset LVDS Interface (20 to 5 DeMux) 27 MHz 150 MHz 300 MHz PL L 20-bits SMB Data, SMB Clk Scramble D M at UX a 27 MHz (SD) 75 MHz 150 MHz (3G) FVH Extract 10-bit C, 10-bit Y CR Insert LN Insert Auto- Rate Support SM Bus Master System Application Xilinx Xilinx Xilinx Figure 5. XAPP514 6
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V S R S CLK CLK WEBENCH Signal-Path Designer national.com/jpn/webench WaveVision 4.1 signalpath.national.com/jpn jpn.feedback@nsc.com POWER designer Expert tips, tricks, and techniques for powerful designs No. 121...1-7... 2...4 FPGA Dennis Hudgins, Low Voltage Applications Manager, Tucson Design Center Table 1. FPGA I/O FPGA Cyclone II 1.5V - 3.3V 5% 1.2V 50mV Cyclone III 1.5V - 3.3V 5% 1.2V 50mV 2.5V 5% Stratix III 1.5V - 3.3V 5% 1.1V or 0.9V 50mV 2.5V 5% Virtex V 1.2V - 3.3V 5% 1.0V 5% 2.5V 5% Spartan III 1.2V - 3.3V Varies 1.2V 5% 2.5V 5% signalpath.national.com/jpndesigner power.national.com/jpndesigner SIGNAL PATH designer Tips, tricks, and techniques from the analog signal-path experts No. 111...1-9 GHz...10 A/D...11 ADC Mike Ewer, Principal Applications Engineer LNA ADC Figure 1. AFE ADC National Semiconductor Corporation 2008. National Semiconductor,, PowerWise, and Signal Path Designer are registered trademarks of National Semiconductor. All other brand or product names are trademarks or registered trademarks of their respective holders. All rights reserved. 550263-019-JP
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