+
From Tradeoffs of Receive and Transmit Equalization Architectures, ICC006,Bryan Casper, Intel Labs
Transmitter Receiver 0 magnitude (db) 0 0 30 40 50 60 0 4 frequency (GHz).
Receiver Transmitter FFE + DFE Analog Digital IC
Equalizer Emulation Receiver Transmitter FFE + DFE Analog Digital
( ) = Q.5 GHz 30 in MHz mi Q.5 GHz 30 MHz
0 0 Gain = 00 Gain = (-a) y( n) = ax( n ) + ( a) x( n)
: ( ) :
db = 4.35 [R(f)/Z 0 + G(f) Z 0 ], R(f) = R 0 + R s (f), G(f) = G 0 + Π f δ C FR4 dielectric, 8 mil wide and m long 50 Ohm strip line Transfer function 0.8 0.6 0.4 0. 0 Frequency.0E+06.0E+07.0E+08.0E+09.0E+0 Frequency, Hz Total loss Conductor loss Dielectric loss
(Tanδ = 0.007) 50 0 6 RM :.3 µm 0 0.0E+00 5.0E+09.0E+0.5E+0.0E+0-5 -0 Loss, db -5-0 -5 Cond. loss w/o R Cond. loss with R Dielectric loss Total loss w/o R Total loss with R urface roughness a significant potential issue! -30 Frequency, Hz
: L d C d V r = L d V i Z0 Tr V r = -C d Z0 V i Tr Impedance, Ohms 5 0 05 00 95 90 85 80 75 70 Z - Z Z + Z Package Z Z TDR impedance profile LC 0 0.5.5 Time, ns LC via Connector BP via BP
= 7.5 mm (300 mil) 0.95 0.45 = 50 ps -0.05 0 50 00 50 00 50 300 350 400-0.55 -.05.0 Normalized output 0.8 0.6 ingle stub (50 ps, 50 ohms) 0.4 Two stubs (50 ps, 50 Ohms) 0. ingle stub (50 ps, 30 ohms) ingle stub (7 ps, 50 ohms) 0.0.0E+08.0E+09.0E+0 Frequency, Hz :.5mm : 5mm
TX DATA RX DATA A T A R B C T C R D 0 gh-gh conn. (baseline) : Normalized Raw and eq pulse response: PR length after main 60 8 6 A T, T,R R C T, T,R R D 4 A T, T,R R B 0 - -4-6 T -8
( ) αl*di/dt ( )
+ + +
60. Fb 40 0 magnitude (db) 0 0 40 60 0 4 6 8 0 4 frequency (GHz) 00. Fb 00 phase (degrees) 0 00 00 0 4 6 8 0 4 frequency (GHz)
.5.5. Linear Equalizer. DFE 0.5 0.5 0 0 0.5 0 4 6 8 0 4 6 8 0 0.5 0 4 6 8 0 4 6 8 0
Rms amplitude 0 5 0 5 0 5 30 35 40 time (UI) 0 Error : absolute error 0. 0.0 5 0 5 0 5 30 35 40 time (UI)
DFE, FFE PLL PLL DFE +
DFE 0
DFE
DFE
0
FFE
Pre-Cursor Taps D D Pre-cursor tap C -0.3 C C.4-0.5
DFE (Decision Feedback Equalizer) D D C -0.4 C C -0. -0.
Virtual Probing Receiver Transmitter FFE + DFE CHANNEL CHANNEL /N Analog Digital
TDR TDR
Z =Z O 00% 0% Z O ( )
V MAX V MIN :, Γ Z Z O Γ= V R /V I =(Z L -Z O )/(Z L +Z O ) = ρ /Φ Z L ρ = Γ V I V R, in db RL= -0 Log(ρ) (VWR) 0 < ρ < < VWR < < RL < 0 db VWR= V MAX /V MIN =(+ρ)/(-ρ)
VWR,,
Z Z O Z L
Z a, Incident Voltage b = a + a b = a + a a, Incident Voltage Z L b, Reflected Voltage b, Reflected Voltage : = b /a a =0, = b /a a =0, = b /a a =0, = b /a a =0 Z, Y, H :
Z a, b = a + a b = a + a a, Z L b, b, = b /a a =0 = b /a a =0 = b /a a =0 = b /a a =0
T Z a, Incident Voltage a, Incident Voltage Z L b, Reflected Voltage b b s = s b a T = T s s T T a a a b b, Reflected Voltage a b a b T T T T T T = = T T T T T T T T T T
a b T b a b a T = T but a b Therefore b a T T a b b' = a' T = T T T a ' b ' T' b ' a ' b a' T ' T ' T ' T ' ' T ' T ' = T ' a' b' T' a' b' T. T T T
, 4 (&3, &4) p 4 4 = 4 3 44 43 4 4 34 33 3 3 4 3 4 3 4 3 a a a a b b b b = c c d d c c d c d c c c c c d c d c c d c d d d d d c d c d d d d d c c d d a a a a b b b b c c 4 port network 4 3
Virtual Probing parameter files ystem definition file ( 8 )
Virtual Probing 0.05 bsp bsm V sp 3 T V 4 sm spa bsp b a spb a b sma bsm b a smb a b 0.05 T V lp V lm lpa b3 a lpb a3 b lma b4 a lmb a4 b L L FIR 0 0 5 0 5 0. 5 0 5 0 5 0. 5 0
Virtual Probing /N
Transmitter Receiver PCB_Trace Coupling_Cap PCB_Trace Output VT Ideal ignal Flow Probing Point PCB_Trace Coupling_Cap PCB_Trace Output Probe Measure ignal Flow during ignal Measurement cope
Eye Doctor = Virtual Probing + Equalizer Emulation Virtual Probing Equalizer Emulation Receiver Transmitter FFE + DFE
4 (Lattice ) 4 DD DD
Odd Mode (Port ) Odd Mode (Port ) Even Mode (Port ) Even Mode (Port )
DD (Port ) DD (Port ) CC (Port ) CC (Port )
Odd Mode (Port ) Odd Mode (Port ) Even Mode (Port ) Even Mode (Port )
PCI Express Gen
PCI Express Gen
. Equalizer Emulation. Virtual Probing 3. 4. A-0