SONY HAD Sensor に関する SONY と NEC の特許戦争 (1994~2002) SONY の 1975 年の HAD Sensor 特許に対する NEC からの攻撃内容の詳細 NECの1980 年の埋め込みPhotodiode 特許では BASE 領域を完全空乏化することを特許請
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1 SONY HAD Sensor に関する SONY と NEC の特許戦争 (1994~2002) SONY の 1975 年の HAD Sensor 特許に対する NEC からの攻撃内容の詳細 NECの1980 年の埋め込みPhotodiode 特許では BASE 領域を完全空乏化することを特許請求しているが すでに上記の2 件の萩原 1975 年特許の実施図で完全空乏化が明示されている また その埋め込み層の電位は CCDの埋め込みチャネル層の濃度と同程度であることも明示している 1978 年にSONYはこの PNP 接合型 ( SONY HAD = Pinned Photo Diode ) の受光構造を採用した Imager で 20 volt 以下の 埋め込み層の電圧を既に実現している 従って 周知情報であり NECの1980 年特許は無効である
2 NECの1980 年の埋め込みPhotodiode 特許では BASE 領域を完全空乏化することを特許請求しているが すでに上記の2 件の萩原 1975 年特許の実施図で完全空乏化が明示されている また その埋め込み層の電位は CCDの埋め込みチャネル層の濃度と同程度であることも明示している 1978 年にSONYはこの PNP 接合型 ( SONY HAD = Pinned Photo Diode ) の受光構造を採用した Imager で 20 volt 以下の 埋め込み層の電圧を既に実現している 従って 周知情報であり NECの1980 年特許は無効である
3 Transistor の動作は Diode の動作を含む HAD センサーは Dynamic Phototransistor 動作である Transistor operation modes include the operation modes of two diodes ( Je and Jc ). Two Operation Modes of PN junction ( diode ) (1) Forward Bias Mode (2) Reverse Bias Mode Four Operation Modes of PNP junction ( transistor ) Jc Je Forward Bias Reverse Bias Forward Bias Reverse Bias Large Current Burn-out Mode Normal Current Amplification Mode Reverse Current Amplification Mode Dynamic Floating Capacitor Mode Pinned `Photodiode Mode Sony HAD Sesnor Jc = Collector Junction Je = Emitter Junction
4 Transistor の動作は Diode の動作を含む HAD センサーは Dynamic Phototransistor 動作である Transistor operation modes include the operation modes of two diodes ( Je and Jc ).
5 The first publication of a PNP junction type Pinned Photodiode in 1978 at Tokyo Conference Proceeding of the 10th Conference on Solid State Devices, Tokyo, 1978; Japanese Journal of Applied Physics, Volume 18(1979) Suuplement 18-1,pp "A 388H x 488V CCD Imager with Narrow Channel Transfer Gate" reported by Yoshiaki Daimon-Hagiwara, Motoaki Abe and Chikao Okada P N P The voltage of the empty potential well of this PNP junction type Pinned Photodiode can be set less than 20 volts by a proper light doping level The Patent by Hagiwara at Sony explains that an ILT CCD image sensor is one of the possible applications. A low image-lag and high picture quality was reported in the Sony 1978 one chip color video camera FT CCD image sensor. This was actually achieved by the PNP junction type Pinned Photodiode with the complete charge transfer operation, by pinching-off the N type storage region of the PNP junction type photo sensing structure. The photo electron signal charge is to be completely transferred to the adjacent vertical buried channel CCD analog shift register. As can be seen from the channel potential curves shown above, the potential of the buried channel storage region was successfully adjusted, for a practical application, to a value less than 20 volt. So, the shallower N-type region of the PNP junction type Pinned Photodiode was less than 20 volt. The same result can be expected also in an ILT CCD case.
6 The first publication of a PNP junction type Pinned Photodiode in 1978 at Tokyo Conference Proceeding of the 10th Conference on Solid State Devices, Tokyo, 1978; Japanese Journal of Applied Physics, Volume 18(1979) Suuplement 18-1,pp "A 388H x 488V CCD Imager with Narrow Channel Transfer Gate" reported by Yoshiaki Daimon-Hagiwara, Motoaki Abe and Chikao Okada P N P The Patent by Hagiwara at Sony explains that an ILT CCD image sensor is one of the possible applications. The voltage of the empty potential well of this PNP junction type Pinned Photodiode can be set less than 20 volts by a proper light doping level インターライン CCD センサとその駆動方法 File ( 1980/9/5 ) by 白木廣光 and 寺西信一 Public ( 1982/3/19) 特許請求範囲 2. 一導電形を有する半導体基板上に該半導体板と反対の導電型を有する第 1の微小領域とこれに接して形成された前期 1. 一導電形を有する半導体基板上 (P) に半導体基板と反基板の同一の導電型の第 2の微小領域とこれらの微細領域対の導電型 (N) を有する第 1の微小領域とこれに接して形を含む前期半導体基板上に形成された絶縁膜上に少なくと成された前記基板と同一の導電型の第 2の微小領域とこも1/2 段以上の電荷転送段を設けた撮像素子の単位セルにれらの微小領域を含む前記半導体基板上に形成された絶おいて前記第 1の微小領域がピンチオフするのに必要な前縁膜上に少なくとも1/2 段以上の電荷転送段とを設けた撮期基板と前記第 1の微小領域の間の逆バイアス電圧をVB 像獅子の単位セルにおいて 前期第 1の微小領域がピン前期第 2の微小領域のフェルミレベルとイントリンシック フェチオフするのに必要な前期基板と前期第 1の微小領域のルミレベルの値をφpp+ としたとき VB + 2φpp < 30 ボルトを間の逆バイアス電圧をVB 前期第 2の微小領域のフェルミみたすように構成されるインターライン CCD センサの前記第レベルとイントリンシック フェルミレベルの値を φpp とした時 2の領域の表面電位 φp+ を VB + 2φpp < φp+ にすること VB + 2φpp < 30ボルトを満たすように構成されていることをよって前期微小領域から前記転送段へ電荷を移動ることを特徴とするインターライン CCDセンサ 特徴とするインターライン CCDセンサーの駆動法 30 volt 以下と規定しているが 既に SONY は 1978 年には 20 volt 以下を実現している かつ同じ PNP 接合構造であるので この特許は重複特許で 無効
7 Transistor の動作は Diode の動作を含む HAD センサーは Dynamic Phototransistor 動作である
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18 Story of Pinned Photodiode and Sony HAD Sensor SONY 1975 年の発明 Completely Depleted Potentail Well Completely Depleted Potentail Well Japanese Patent Japanese Patent NECの1980 年の埋め込みPhotodiode 特許では BASE 領域を完全空乏化することを特許請求しているが すでに上記の2 件の萩原 1975 年特許の実施図で完全空乏化が明示されている また その埋め込み層の電位は CCDの埋め込みチャネル層の濃度と同程度であることも明示している 1978 年にSONYはこの PNP 接合型 ( SONY HAD = Pinned Photo Diode ) の受光構造を採用した Imager で 20 volt 以下の 埋め込み層の電圧を既に実現している 従って 周知情報であり NECの1980 年特許は無効である
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