2005 1

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きみのしんながおか
5 years ago
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1 25

2 SPARCstation 2 CPU central processor unit 25 2

3 25 3

4 25 4

5 DRAM 25 5

6 25 6

7 : DRAM 25 7

8 2 25 8

9 2 25 9

10 2 bit: binary digit V 2V 25

12 A B C A B C A B C A B C A C A B

13 25 3 Co Cin A B S A B Cin S Co

14 32 Cin a b Cin Co Result A B S a b Cin Co Result Co a2 b2 Cin Co Result2 a3 b3 Cin Co Result3 25 4

15 ALU (arithematic logic unit) ALUop ALUop? a[3-] 32 Zero b[3-] 32 ALU 32 Resul t[3-] Overflow CarryOut 25 5

16 ALU Binvert CarryIn Operation a Result b 2 CarryOut 25 6

17 ALU Binvert CarryIn Operation a b CarryIn ALU CarryOut Result a b CarryIn ALU CarryOut Result a2 b2 CarryIn ALU2 CarryOut Result2 CarryIn a3 b3 CarryIn ALU3 Result3 25 7

18 ALUop ALUop ALUop a b ALU Zero Result Overflow Binvert a b CarryIn CarryIn ALU Less CarryOut Result Operation CarryOut a b CarryIn ALU Result ALUop Binvert CarryIn Operation 25 8

19 2V V 25 9

20 A B C A B C C C A B A B 25 2

21 25 2

22 25 22

23 (2) ENIAC

24 ENIAC 7,468 5kW 24m.9m 2.5m 3 ABC 25 24

25 N P + P N N P 25 25

26 (2) Metal SiO2 N-Si P-Si N-Si MOS metal oxide silicon IC: integrated circuit (<K LSI: large scale integrated circuit K K 25 26

27 Intel 44: IC Intel.3.4cm 2,

29 () = R R2 R3 R4 R load -> R load -> R2 load 2 -> R3 R+R2 -> R4 R4-R3 -> R5 R5 -> store 3 ALU 25 29

30 (2) = R R2 R3 R4 R5 2 load -> R 22 load -> R2 23 load 2 -> R3 ALU 24 R+R2 -> R4 25 R4-R3 -> R5 26 R5 -> store

31 (3) = R R2 R3 R4 R5 2 2 load -> R 22 load -> R2 23 load 2 -> R3 ALU 24 R+R2 -> R4 25 R4-R3 -> R5 26 R5 -> store

32 (4) = R R2 R3 R4 R load -> R 22 load -> R2 23 load 2 -> R3 ALU 24 R+R2 -> R4 25 R4-R3 -> R5 26 R5 -> store

33 (5) = R R2 R3 R4 R load -> R 2 22 load -> R2 23 load 2 -> R3 ALU 24 R+R2 -> R R4-R3 -> R5 26 R5 -> store

34 (6) = R R2 R3 R4 R load -> R load -> R load 2 -> R3 R+R2 -> R4 ALU 25 R4-R3 -> R5 26 R5 -> store

35 (7) = R R2 R3 R4 R load -> R 22 load -> R2 23 load 2 -> R3 ALU 24 R+R2 -> R4 25 R4-R3 -> R5 26 R5 -> store

36 IM RF DM RF i i2 i i2 i i2 i i2 i i

37 IM RF DM RF i 2 i2 i 3 i3 i2 i 4 i4 i3 i2 i 5 i5 i4 i3 i2 i 6 i6 i5 i4 i3 i2 7 i7 i6 i5 i4 i3 8 i8 i7 i6 i5 i4 9 i9 i8 i7 i6 i

38 i IF ID EX MEM WR i2 IF ID EX MEM WR i3 IF ID EX MEM WR i4 IF ID EX MEM WR i5 IF ID EX MEM WR 25 38

39 a b P Q IF ID EX MEM WB IF ID EX MEM WB 25 39

40 25 4 WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF

41 i IF ID EX MEM WB i2 IF ID EX MEM WB i3 IF ID EX MEM WB i4 IF ID EX MEM WB i5 IF ID EX MEM WB i6 IF ID EX MEM WB 25 4

42 i BHT 2 i

43 2 2bc 2 4 TTT N TTN T TNT T NTT T

44 i: r = r2 + r3 i2: r4 = r

45 (cont d)

46 VLIW Intel Pentium 4, AMD Athlon VLIW Very Long Instruction Word Intel Itanium, Transmeta Crusoe 25 46

47 main( ) { main( ) { } } add r... add r... add r... sub r

48 VLIW i: r3 = r4 + i2: r = load (r2) i3: r = r < r3 i4: r5 = r2 + r6 i5: beq r5, L i: r3 = r4 + i4: r5 = r2 + r6 nop i2: r=load(r2) i3: r = r < r3 nop i5: beq r5, L nop VLIW nop 25 48

49 vs. VLIW VLIW Pentium 4 vs. TM54 Intel Pentium 4 Transmeta TM54.5GHz 7MHz.8µm.8µm 42M 2.8M 27mm 2 73mm

50 2 MOS 25 5

.,. 0. (MSB). =2, =1/2.,. MSB LSB, LSB MSB. MSB 0 LSB 0 0 P

.,. 0. (MSB). =2, =1/2.,. MSB LSB, LSB MSB. MSB 0 LSB 0 0 P , 0 (MSB) =2, =1/2, MSB LSB, LSB MSB MSB 0 LSB 0 0 P61 231 1 (100, 100 3 ) 2 10 0 1 1 0 0 1 0 0 100 (64+32+4) 2 10 100 2 5, ( ), & 3 (hardware), (software) (firmware), hardware, software 4 wired logic