システムオンチップ技術

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ゆりかやぶき
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1 (SoC) 2004/6/11 Yukihiro Nakamura u.ac.jp

2 (VLSI) () VLSI

3 DIPS IBM370 CPU MH MB GB DIPS VAIO LSI Sony VAIO CPU MH MB GB Pentium

7 () ()

14 V,S.,B Sun Micro Apple Microsoft

15 NTT NASDAQ() Cisco Systems, Inc. Intel Corporation Dell Computer Corporation WorldCom, Inc. Sun Microsystems, Inc. Oracle Corporation Microsoft Corporation JDS Uniphase Corporation Applied Materials, Inc. Network Appliance, Inc. IT

16 $1= NTT () 10 General Electric Cisco Systems Intel Microsoft Exxon Mobil Wal-Mart Stores Citigroup Oracle IBM EMC IT

17 NTT IT NEC () :

18 (SEMATECH) Logic Tr. / Chip 10M 1M 100K 10K 1K Logic Tr./Chip Tr. /Staff-Mo 58% /Yr. Compound Complexity Growth rate Year 21% /Yr. Compound Productivity Growth rate 100M 10M 1M 100K 10K 1K Tr. / Staff-Month

19 DB DB / LSI LSI LSI LSI LSI LSI LSI LSI / / ( ) / / / LSI/MSI/SSI LSI/MSI/SSI / ( )

20 VLSI 10 7

21 Deep Submicron Technology SoC 10 7 SoCIT ScCIT()

22 SFLCPU 18 Data Address 8bit 8bit RR op IF1 EX RX op IF1 M RXE op IF1 M EX INX, SEC, CLC, ROLA, COMA, INP LDAX, STAX ADCX, ANDX, SUBX RI op imm IF1 IF2 EX 3 LDAI, LDXI XM op adrs IF1 IF2 M 3 LDXM, STXM B op adrs IF1 IF2 B 3 BC, BZ, B

30 () ()DA(1981

31 Programming-like Design Method SFL( ) PARTHENON

32 stage fetch { } stage exec { state exec par{ SFL state fetch1 par { /* word */ op1 := memory.read( pc ).out_data ; pc := inc.inc( pc ).out ; alt{ idec.idec( memory.out_data ).out: goto fetch2 ; else :relay exec. task( ) ; } } state fetch2 par{ /* () */ op2 := memory.read( pc ).out_data ; pc := inc.inc( pc ).out ; goto fetch1 ; relay exec.task( ) ;

33 Global System Designer CAD IT Information Technology SoC System on-a-chip

34 SFL/PARTHENON SFL 8bit CPU)( ) (1) SFL (Structured Function description Language) (2) (8bit CPU) (3) SFL ( ) ASIC Mask Pattern netlist () () FPGA FPGA Mapper

35 SFL Verilog-HDL VHDL UDL/I

36 SFL Verilog-HDL VHDL UDL/I NTT Cadence IFIP Gateway Synopsys IEEE PARTHENON

37 SFL SFL Verilog-HDL, VHDL UDL/I

38 SFL

39 ITSoC

40 SoC SpecC, SystemC, Superlog C/C++ IT Information Technology SoC System on-a-chip

PARTHENON s success PARTHENON 32 bit Risc Processor, FDDP Perfect

Number of Instructions Pipelining Number of Gates Performance Pins

pipeline 13,933 gates More than 10 MIPS 172/223 8.76mm8.79mm 1.

41 PARTHENON s success PARTHENON 32 bit Risc Processor, FDDP Perfect Harmony between Behavioral Language and Logic Synthesis! Number of Instructions Pipelining Number of Gates Performance Pins Chip Size Process Design Effort Foundry 47(subset of DLX) 5-stage pipeline 13,933 gates More than 10 MIPS 172/ mm8.79mm 1.0m CMOS 44 person-days VLSI Technology Inc. 44 NTT Communication Science Laboratories

42 PARTHENON s success 155Mbps TCP/IP

43 PARTHENON s success MPEG Decoder LSI

44 PARTHENON s success MPEG2/PCI Card

45 MPEG2 Card

46 PARTHENON s success Apple CPU6502 () 19947

PARTHENON s success PARTHENON Vector Processor for DSP Systems

Microcode Pipelining Number of Gates Performance Pins Chip Size

pipeline3 150Kgates 120 MFLOPS (40MHz) 223 14mm15mm 1.

47 PARTHENON s success PARTHENON Vector Processor for DSP Systems Perfect Harmony between Behavioral Language and Logic Synthesis! Microcode Pipelining Number of Gates Performance Pins Chip Size Process Design Effort Foundry VLIW type 128bit(2types) 3-stage pipeline3 150Kgates 120 MFLOPS (40MHz) mm15mm 1.0m CMOS 30 person-months TOSHIBA Corp. NTT Transmission Systems Laboratories

48 SHD

49 ()) SoC/VLSI /VLSI,

55 () 4

56 EMS (Electronics Manufacturing Services) EMCS20014 Engineering, Manufacturing and Customer Services

57 ATT) (20023) NEC/WS/ (200110)

59 Fedex

60 ()(2003) ()

61 EMS

64 (1) 49.7 (2)79.3 (3)25.1 (51.4)(20.6) (4)55.1 (22) (19.9) (5) 55.6 (6)

69 REJECT

Verilog HDL による回路設計記述

Verilog HDL による回路設計記述 Verilog HDL 3 2019 4 1 / 24 ( ) (RTL) (HDL) RTL HDL アルゴリズム動作合成論理合成論理回路配置配線ハードウェア記述言語シミュレーションレイアウト 2 / 24 HDL VHDL: IEEE Std 1076-1987 Ada IEEE Std 1164-1991 Verilog HDL: 1984 IEEE Std 1364-1995