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とらふみさわい
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1 PC

2 muscle server blade server PC PC +

3 EHPC/Eric (Embedded HPC with Eric) 1216 Compact PCI Compact PCIPC Compact PCISH-4 Compact PCISH-4 Eric Eric

4 EHPC/Eric

5 EHPC/Eric Gigabit Ethernet CompactPCI CompactPCI LSI Eric LSI Eric LSI Eric CompactPCI PC CPU SH-4 PCI

6 Compact PCI Compact PCI Eric LSI SDRAM Eric1GB MPU SH4 PCII/F Ethrenet

7 vs. HPC MPP SMP PC Ethernet, etc. Compact PCI, Ethernet, etc.

8 PC Compute Intensive +

9 p 0 p 1 o 0 o 1 N H S PC S = (1 p) + p N 1 (1 o) + o H

10 etc.

11 PCXeon (2.8GHz) GB/processor2 STO-3G 1 HIV-1 protease

12 RNA

13 (1) (2) (3) (4) (6) (5)C = = = N I a ai IJ N I ai IJ C S C F 1 1 ε + + = K L KL IJ IJ IJ JL IK KL IJ P V T F ), ( 2 1 ), (

14 (1) (2) (3) (4) (6) (5)C Total (98.6%) (98.8%) (98.6%) (98.7%) 22.9 (96.6%) GAQMY GAQM GAQ GA G 98 LSI

15 for(i = 0; I < Nshell; I++) for( J = 0; J < I; J++) for (K = 0; K < I; K ++) for( L = 0; L < I; L++) for(i = 0; i < N i ; i++) for(j = 0; j < N j ; j++) for (k = 0; k < N k ; k++) for(l = 0; l < N l ; l++) <s i s j s k s l > forend forend forend forend <a I a J a K a L >() forend forend forend forend

16 Eric LSI LSI: IIC RC

17 Eric:LSI 32b SH-4 I/F 64b 64b 64b 64b IIC Program Memory (64KB) ERF Table (128KB) RC Microprogram Memory (64KB) 16b 64b 64b 64b 64b 64b IIC Engine RC Engine 0 RC Engine 1 RC Engine 2 RC Engine 3 IALU FMUL &ADD FDIV &SQRT EXP &ERF IALU FMUL &ADD IALU FMUL &ADD IALU FMUL &ADD IALU FMUL &ADD Register File Register File Register File Register File Register File 64b 64b 64b 64b 64b Data Memory (32KB/bank 8banks) 64b IIC (RISC ) 64b SDRAM I/F 64b RC ( CMP )

18 LSI Eric vs. Intel P4 LSI Eric CMP 200MHz Intel P4 3.2GHz

19 GAQMY Pentium 1100 ( 19 ) Pentium 640 ( 11 )

20 (704KB) Eric LSI (3.6M) 5mm 10mm TSMC 0.13µm 3.6M 704KB 5mm 10mm :200MHz 10W 2GFlop/s()

21 Compact PCI Compact PCI Eric LSI SDRAM Eric1GB MPU SH4 PCII/F Ethrenet

22 EHPC/Eric =Eric 28 PC Ethernet Eric112

EHPC/Eric GFlop/s MO ( ) W D H:mm KW M$ EHPC/Eric 112 224 ()) 2

23 EHPC/Eric GFlop/s MO ( ) W D H:mm KW M$ EHPC/Eric ()) () 2 () 0.1 SR8000/

24 HPC PCI I/O SDRAM GPIO UART Interrupt Controller PCI I/O

300 MHz, 32-bit Xtensa-based processor 16- and 24-bit instructions FPU

store 8, 16, 32, 64, and 128 bit Unaligned load and store Up to 16 bytes

User-defined extensions to the core ISA Defined in C/C++ Fully pipelined

25 300 MHz, 32-bit Xtensa-based processor 16- and 24-bit instructions FPU MMU with TLB Stretch Instruction Set Extension Fabric Aligned load and store 8, 16, 32, 64, and 128 bit Unaligned load and store Up to 16 bytes variable byte streaming I/O Up to 32 bits variable bit streaming I/O User-defined extensions to the core ISA Defined in C/C++ Fully pipelined and interlocked Low power consumption Support for standard operating systems Stretch

Memory Bandwidth Maximum Memory Maximum Disk Storage 53 GFlop/s 96

26 CRAY XD1 Compute Processors Chassis 12 Each Rack 144 Performance Aggregate Switching Capacity Interprocessor Latency Aggregate Memory Bandwidth Maximum Memory Maximum Disk Storage 53 GFlop/s 96 GB/s 1.6 us 77 GB/s 96 GB 296 GB 633 GFlop/s 1152 GB/s 1.8 us 922 GB/s 1152 GB

27 PC

九州大学学術情報リポジトリ Kyushu University Institutional Repository マッスルサーバー ( 汎用 PC クラスタ + 特定計算向けハードウェア ) の開発 : 分子軌道法を例にして村上, 和彰九州大学大学院システム情報科学研究院九州大学情報基盤センタ

九州大学学術情報リポジトリ Kyushu University Institutional Repository マッスルサーバー ( 汎用 PC クラスタ + 特定計算向けハードウェア ) の開発 : 分子軌道法を例にして村上, 和彰九州大学大学院システム情報科学研究院九州大学情報基盤センター http://hdl.handle.net/2324/9106 出版情報 :SLRC プレゼンテーション,