Itanium2ベンチマーク
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- さゆり なみこし
- 5 years ago
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1 HPC CPU Special thanks Timur Esirkepov HPC
2 1. CPU Itanium 2 HPC 2
3 1 Itanium2 CPU CPU 3
4 ( ) Intel Itanium2 NEC SX-6 HP Alpha Server ES40 PRIMEPOWER SR8000 Intel Pentium4 4
5 Intel Itanium2 CPU:Intel Itanium2 1.5GHz/L3 6MB/4way Memory:16GB 1CPU 6.4GB/s 6.4GB/s OS:Red Hat Enterprise Linux AS2.1(Kernel e.31smp) Compiler:Intel Fortran Compiler ver8.0 6GFLOPS 5
6 NEC SX-6 CPU:8GFLOPS/4way Memory:24GB 1CPU 32GB/s 128GB/s OS:SUPER-UX R13.1 Compiler:NEC Fortran Compiler for SX Rev.285 8GFLOPS 6
7 HP Alpha Server ES40-4 CPU:Alpha21264B 833MHz/4way Memory 16GB 1CPU 2.6GB/s ( 5.2GB/s) OS:Compaq Tru64 UNIX V5.1 Compiler:Compaq Fortran Compiler V GFLOPS 7
8 PRIMEPOWER CPU: SPARC 64V 1.3GHz/128way Memory:256GB 1CPU 8.4GB/s ( 133GB/s OS:SUN Sloaris9 Compiler:Fujitsu Fortran Compiler V GFLOPS 8
9 SR8000 F1 CPU: Power3-375MHz/8way Memory:8GB 1CPU 4GB/s ( 32GB/s) OS:HI-UX/MPP Compiler:Hitachi Fortran Compiler V01-05-/A 1.5GFLOPS 9
10 Intel Pentium4 CPU: Intel Pentium4 3.0GHz /L2 512KB/FSB800 /HT off Memory:2GB 1CPU 6.4GB/s /DDR400/ 875P OS:Redhat Linux 9(Kernel ) Compiler:Intel Fortran Compiler ver8.0 SSE 12GFLOPS SSE2; 6GFLOPS 10
11 FLOPS FLOPS Floating point number Operations Per Second 1FLOPS1 1 Itanium FLOPS 4 / 2 / 2 / Itanium2 1.5GHz 1.5*4=6GFlops 11
12 Pentium4 SSE SSE2 SIMD Single Instruction Multiple Data Pentium4 SSE Streaming SIMD Extensions Pentium4 SSE2 Streaming SIMD Extensions Pentium4 FLOPS Pentium4 3GHz 3*4=12Gflops 3*2=6Gflops Intel Technology Journal Q1,
13 1. M CIP 2-2 Roe +MUSCL +TVD APR 2-3 PPM 3. PIC Timur 4.(FP) 13
14 1. 3 M MB 14
15 1. NEC SX-6 -C hopt MLFOPS HP Alpha Sever ES40-4 Alpha 21264B 833MHz -O5 -fast -tune ev7-inline all -speculate all -unroll MFLOPS PRIMEPOWER SPARC64V 1.3GHz -Kfast_GP2=2 -Klargepage=2 -Kprefetch_cache_level=3 -Kstriping= MFLOPS SR8000 F1 -Os -noparallel MFLOPS Intel Pentium4 3GHz Pentium IPO -O3 -fast -Vaxlib -xkwn -tpp6 -prof_use MFLOPS 15
16 1. Itanium2 log 1:12: MFLOPS: time(s): Vaxlib log 2:12: MFLOPS: time(s): Vaxlib -tpp1 log3 :12: MFLOPS: time(s): O3 -Vaxlib log 4:12: MFLOPS: time(s): O3 -Vaxlib -tpp1 log 5:12: MFLOPS: time(s): O3 -Vaxlib -fast log 6:12: MFLOPS: time(s): O3 -Vaxlib -fast -tpp1 log 7:12: MFLOPS: time(s): O3 -Vaxlib -ipo log 8:12: MFLOPS: time(s): O3 -Vaxlib -tpp1 -ipo log 9:12: MFLOPS: time(s): O3 -Vaxlib -static log10:12: MFLOPS: time(s): O3 -Vaxlib -tpp1 -static log11:12: MFLOPS: time(s): O3 -Vaxlib -fno-fnalias log12:12: MFLOPS: time(s): O3 -Vaxlib -tpp1 -fno-fnalias log13:12: MFLOPS: time(s): O3 -Vaxlib -fast -fno-fnalias log14:12: MFLOPS: time(s): O3 -Vaxlib -fast -tpp1 -fno-fnalias log15:12: MFLOPS: time(s): O3 -Vaxlib -fno-fnalias -static log16:12: MFLOPS: time(s): log17:12: MFLOPS: time(s): log18:12: MFLOPS: time(s): log19:12: MFLOPS: time(s): log20:12: MFLOPS: time(s): O3 -Vaxlib -tpp1 -fno-fnalias -static -O3 -Vaxlib -fno-fnalias -ipo log21:12: MFLOPS: time(s): O3 -Vaxlib -fast -fno-alias log22:12: MFLOPS: time(s): O3 -Vaxlib -fast -tpp1 -fno-alias log23:12: MFLOPS: time(s): O3 -Vaxlib -fno-alias -static log24:12: MFLOPS: time(s): O3 -Vaxlib -tpp1 -fno-alias -static log25:12: MFLOPS: time(s): O3 -Vaxlib -fno-alias -ipo log26:12: MFLOPS: time(s): O3 -Vaxlib -tpp1 -fno-alias ipo -O2 -O3 2 3 (-fast -ipo) -tpp1 Itanimu2 Itanium -O3 -Vaxlib -tpp1 -fno-fnalias -ipo MFLOPS-O3 -Vaxlib -fno-alias -O3 -Vaxlib -tpp1 -fno-alias -O3 -fast -Vaxlib -tpp1 -fno-fnalias ivdep_parallel -ftz MFLOPS
17 1. Itanium2!DIR$PREFETCH!DEC$PREFETCH log 6 :12: MFLOPS: log_preftc 6:12: MFLOPS: log14 :12: MFLOPS: log_preftc14:12: MFLOPS: log22 :12: MFLOPS: log_preftc22:12: MFLOPS: Do Intel log_idep6: MFLOPS: prefetch og_idep_pref6:12: MFLOPS: log_idep22: MFLOPS: log_idep_pref14:12: MFLOPS: log_idep14: MFLOPS: log_idep_pref22:12: MFLOPS:
18 1. Itanium2!DIR$UNROLL (n)!dec$ PREFETCH a, p, b, c, wrk1, bnd!dec$ UNROLL (126) DO K=2,kmax-1 DO J=2,jmax-1!DEC$ UNROLL (12) DO I=2,imax-1 S0=a(I,J,K,1)*p(I+1,J,K)+a(I,J,K,2)*p(I,J+1,K) 1 +a(i,j,k,3)*p(i,j,k+1) 2 +b(i,j,k,1)*(p(i+1,j+1,k)-p(i+1,j-1,k) 3 -p(i-1,j+1,k)+p(i-1,j-1,k)) 4 +b(i,j,k,2)*(p(i,j+1,k+1)-p(i,j-1,k+1) 5 -p(i,j+1,k-1)+p(i,j-1,k-1)) 6 +b(i,j,k,3)*(p(i+1,j,k+1)-p(i-1,j,k+1) 7 -p(i+1,j,k-1)+p(i-1,j,k-1)) 8 +c(i,j,k,1)*p(i-1,j,k)+c(i,j,k,2)*p(i,j-1,k) 9 +c(i,j,k,3)*p(i,j,k-1)+wrk1(i,j,k) SS=(S0*a(I,J,K,4)-p(I,J,K))*bnd(I,J,K) GOSA=GOSA+SS*SS wrk2(i,j,k)=p(i,j,k)+omega *SS!DEC$UNROLL (n)!dec$ PREFETCH wrk2!dec$ UNROLL (12) DO K=2,kmax-1 DO J=2,jmax-1!DEC$ UNROLL (12) DO I=2,imax-1 p(i,j,k)=wrk2(i,j,k) enddo enddo enddo MFLOPS MFLOPS
19 1. Itanium2 1 prof_gen 2 prof_use -O3 -fast -Vaxlib -tpp1 -fno-fnalias -ivdep_parallel -ftz MFLOPS -O3 -fast -Vaxlib -tpp1 -fno-fnalias -ivdep_parallel -ftz -prof_use MFLOPS -O3 -fast -Vaxlib -tpp1 -fno-fnalias -ivdep_parallel -ftz MFLOPS -O3 -fast -Vaxlib -tpp1 -fno-fnalias -ivdep_parallel -ftz -prof_use MFLOPS 19.
20 Itanium2 SX Fast 20
21 PRIMEPOWER,Alpha,Itanium2 High efficiency 21
22 2. 3 CIP ( 3 1 ) APR( 2 2 ) PPM ( 3 2 ) 99% GB 22
23 2-1 CIP NEC SX-6 -C hopt % MFLOPS HP Alpha Sever ES MHz -O5 -fast -tune ev7 -inline all -speculate all PRIMEPOWER SPARC64V 1.3GHz -Kfast_GP2=2 -Klargepage=2 -Kprefetch_cache_level=3 -Kstriping= SR8000 F1 -Oss -noparallel Intel Pentium4 -O3 -Vaxlib -xkwn -tpp6 -ipo -prof_use Pentium IPO 23
24 2-1 CIP Itanium2 ifort -Vaxlib ( -O2 -tpp2) ifort -O3 -Vaxlib ifort -O3 -Vaxlib -ipo ifort -O3 -Vaxlib -ipo -fno-alias ifort -O3 -Vaxlib -ipo -fno-alias!dir$ PREFETCH ifort -O3 -tpp1 -Vaxlib -ipo -fno-alias -prof_use!dir$ PREFETCH Itanium IPO 24
25 CIP Itanium2 Pentium4 SX % Fast 25
26 Itanium2 CPU SX High efficiency 26
27 2-2 APR NEC SX-6 -C hopt pi auto % 3402MFLOPS HP Alpha Sever ES MHz -O5 -fast -tune ev7 -inline all -speculate all PRIMEPOWER SPARC64V 1.3GHz -Kfast_GP2=3 -Klargepage=2 -Kprefetch_cache_level=3 -Kstriping= SR8000 F1 -Oss -noparallel Intel Pentium4 -O3 -Vaxlib -xkwn -tpp6 -fno-fnalias -ipo Pentium IPO 27
28 2-2 APR Itanium2 ifort -Vaxlib ( -O2 -tpp2) ifort -O3 -Vaxlib ifort -O3 -Vaxlib -fno-fnalias -ipo Itanium2 IPO Loop unrolling 28
29 APR SR Itanium2 20 Fast 29
30 PRIMEPOWER SR APR Alpha CIP High efficiency 30
31 2- PPM NEC SX-6 -C hopt pi auto % 1991MFLOPS HP Alpha Sever ES MHz -O5 -fast -tune ev7 arch ev PRIMEPOWER SPARC64V 1.3GHz -Kfast_GP2=3 -Klargepage=1 -Kprefetch_cache_level=3 -Kstriping= SR8000 F1 -Oss -noparallel -pvfunc=3 -predicate noscope Intel Pentium4 -O3 -Vaxlib -xkwn -tpp6 -ipo Pentium IPO 31
32 2- PPM Itanium2 ifort -Vaxlib ( -O2 -tpp2) ifort -O3 -Vaxlib ifort -O3 -Vaxlib -ipo ifort -O3 -Vaxlib -fno-alias Itanium2 Loop unrolling 32
33 PPM13-45 SX 30 Itanium2 Fast 33
34 PPM SR, PRIMEPOWER High efficiency 34
35 Pentium4 CPU Itanium2 VLIW EPIC max,min,abs / SX 3.2~3.6 FLOPS Alpha Itanium2 ON PRIMEPOWER ON Alpha SR8000 Alpha PRIMEPOWER ON SX 1CPU 35
36 2 PIC 95% GB 2,000,
37 3 PIC NEC SX-6 -C hopt -Wf"-pvctl listvec loopcnt= " % MFLOPS HP Alpha Sever ES40-4 Alpha 21264B 833MHz -fast -tune ev PRIMEPOWER SPARC64V 1.3GHz -Kfast_GP2=2 -Klargepage=2 -Kprefetch_cache_level=3 -Kstriping= SR8000 F1 -Oss -noparallel Intel Pentium4 3GHz -O3 -fast -Vaxlib -xkwn Pentium4 IPO 37
38 3 PIC Itanium2 ifort -Vaxlib ifort -O3 -Vaxlib ( -O2 -tpp2) ifort -O3 -Vaxlib -ipo -fno-alias ifort -O3 -Vaxlib -fast -fno-alias -prof_use ifort -O3 -Vaxlib -fast -fno-fnalias -prof_use Itanium2 IPO 38
39 PIC Itanium2 SX Fast 39
40 SR, Alpha Itanium2 High efficiency 40
41 Pentium4 CPU Itanium2 FLOPS 4 SR8000) Pentium4 SX 1.4 Alpha FLOPS PRIMEPOWER SR FLOPS SX FLOPS Itanium2 41
42 1 (FP) FP 98% MB 12 42
43 FP NEC SX-6 -C hopt -Wf"-pvctl listvec loopcnt= " % 2911MFLOPS HP Alpha Sever ES40-4 Alpha 21264B 833MHz -O5 -fast -tune ev7 -inline all -speculate all PRIMEPOWER SPARC64V 1.3GHz -Kfast_GP2=2 -Klargepage=2 -Kprefetch_cache_level=3 -Kstriping= SR8000 F1 -Os -noparallel Intel Pentium4 3GHz -O3 -fast -Vaxlib -xkwn -fno-alias Pentium4 IPO 43
44 4 FP Itanium2 ifort -Vaxlib -noautomatic ( -O2 -tpp2) ifort -Vaxlib -O3 -noautomatic ifort -O3 -fast -Vaxlib -noautomatic ifort -O3 -fast -Vaxlib -noautomatic -prof_use Itanium2 IPO 44
45 FP CIP PRIMEPOWER Fast 45
46 FP PRIMEPOWER CPU High efficiency 46
47 Pentium4 CPU FP Itanium2 VLIW EPIC SX 2.3 FLOPS Alpha ON PRIMEPOWER SR8000 FLOPS Itanium2 ON SX 47
48 Pentium4~Itanium2~Alpha FLOPS Pentium4:Itanium2:Alpha 0.63:1.00:0.51 Pentium4:Itanium2:Alpha 0.32:1.00:0.26 Itanium2 SR8000 PIC CPU PRIMEPOWER CIP Itanium2 APR,PPM 128waySMP 48
49 2 CPU 49
50 CPU XL Alpha Sever CPU 50
51 XL 180node*4CPU: 162 GFLOPS 13.5% 245 GFLOPS 20.4% 180node*3CPU 180 GFLOPS 20.0% 205 GFLOPS 22.7% 180node*2CPU 150 GFLOPS 25.0% 166 GFLOPS 27.6% 180node*1CPU 101 GFLOPS 33.7% 149 GFLOPS 50.0% 51
52 CPU Alpha bandwidth340mb/s Latency5 s 1. 2.Alpha
53 CPU 1CPU CPU CPU CPU CPUCPU 2 CPU /32 *2=12 12 *4CPU=48CPU 53
54 3 Itanium 2 HPC CPU Itanium2 Pentium4 Xeon 54
55 Bandwidth MPI Latency Quadrics QsNet ~900MB/s 4.5 s cost~?? Infiniband ~800MB/s 7 s cost ~$2000/port Quadrics QsNet ~350MB/s 5.5 s cost ~$3500/port Myrinet 2000 ~ 240MB/s 7 s cost ~$1700/port Myrinet ~150MB/s 15 s cost ~$1500/port Gigabit Ethernet ~100MB/s 85 s cost ~$1000/port 1 s CPU 55 CPU
56 / Gigabit Ethernet Pentium 16CPU Myrinet Myrinet 2000 Pentium Xeon 64?CPU Myrinet 2000 Infiniband Pentium Xeon 256?CPU Infiniband QsNet Xeon Alpha?CPU 56
57 TOP 3 58% 4.7GFLOPS/CPU Linpak Itanium2 Itanium2 CPU G5 Itanium2 CPU 57 64% 3.9GFLOPS/CPU 74% 4.5GFLOPS/CPU 71% 2.9GFLOPS/CPU
58 TOP 3 ASCI 58% 4.7GFLOPS/CPU 64% 3.9GFLOPS/CPU 74% 4.5GFLOPS/CPU 71% 2.9GFLOPS/CPU Itanium2 CPU CPU 58
59 Itanium2 59
60 CPU Itanium2 SR PRIMEPOWER Alpha GFLOPS 60
61 CPU Pentium4 GFLOPS Itanium2 way/gflops GFLOPS Pentium4 GFLOPS Itanium2 GFLOPS Intel Compiler(Linux) 61
62 Itanium2 Pentium4 Itanium2 SW SW SW 62
63 Itanium2 Pentium4 Itanium2 Dual Xeon Itanium2 Itanium2 MPI 63
64 Itanium2 4way V.S. SX-6 6 1CPU 64
65 ,000 ( 3,000 ) 1,000 ldm-rg@nifty.com 65
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