THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS TECHNICAL REPORT OF IEICE. dou
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1 九州大学学術情報リポジトリ Kyushu University Institutional Repository キャッシュ ミス頻発ロード命令を対象としたミス原因解析 三輪, 英樹九州大学大学院システム情報科学府 堂後, 靖博福岡大学大学院工学研究科 井上, 弘士九州大学大学院システム情報科学府 村上, 和彰九州大学大学院システム情報科学府 出版情報 : 電子情報通信学会技術研究報告, CPSY005-(005-08). 105 (6), pp.43-48, 電子情報通信学会 CPSY 研究会バージョン :accepted 権利関係 :
2 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS TECHNICAL REPORT OF IEICE. DRAM 100 () 90 % Abstract Behavior Analysis for Delinquent Loads Hideki MIWA, Yasuhiro DOUGO, Koji INOUE, and Kazuaki MURAKAMI Dept. of Informatics, Kyushu University Dept. of Electronics Engineering, Fukuoka University {h-miwa,inoue,murakami}@i.kyushu-u.ac.jp, dougo@v.tl.fukuoka-u.ac.jp In recent years, the performance of microprocessors has been improved extremely. On the other hand, DRAMs, commonly used as the main memory, is about 100 times as slow as microprocessors. In this situation, DRAMs suppress the performance of microprocessors. This problem is commonly called Memory Wall Problem. For the performance improvement of computer systems, it is very important to solve this problem. Currently, the authors are developing cache miss penalty reduction techniques focused on the delinquent loads which cause the cache misses frequently. Such load instructions are responsible for 90% of all the cache misses, and deteriorate the performance. In this paper, to reveal the cause of cache misses, the authors investigate the memory access patterns for several benchmark programs. The results show that almost all of the data which cause cache misses had been written to memory system by store instructions. Key words cache memory, memory wall problem, cache miss penalty reduction, delinquent load instructions 1. DRAM DRAM DRAM 1 1
3 ( ) (Delinquent Load DL ) [1] DL [1] [7] DL DL [8] DL DL DL DL (Corresponding Store CS ) DL CS 1 DL CS DL DL CS CS. DL CS DL CS DL CS c=a+b; z=x+c; 1 Load a Load b Add c, a, b Store c Load c Load x Add z, x, c Store z CS DL DL CS 3bit RISC 1 L. 1 DL CS DL DL CS pc i pc j (1) () Load(pc i ) (i = 1,,, i load ) (1) Store(pc j ) (j = 1,,, j store ) () pc i, pc j : i load, j store : n, m ( n, m ) (3) (4) Load(pc i, n) (n = 1,,, n i) (3) Store(pc j, m) (m = 1,,, m j) (4) n, m: n i, m j : pc i, pc j (1) () (3) () d inst addr (5) L stat (6) addr = DataAddr(d inst) (5) stat = LDataMissStatus(Load(pc i, n)) (6)
4 ( stat=1 : stat=0) LDataMissCount ( Load(pc i ) ) LDataMissCount ( Load(pc i ) ) n i = LDataMissStatus ( Load(pc i, n) ) (7) n=1 L LDataMissCount ( Load(pc i) ) 1 (8) LDataMissRank ( Load(pc i ) ) (8) DL CS DL L 16 1 CS DL (9) dlpc x DL (10) cspc y CS LDataMissRank ( Load(dlpc x) ) < = 16 (9) DataAddr ( Load(dlpc x, n) ) = DataAddr ( Store(cspc y, m) ) (10) ( n, m n < = n pci, m < = m pcj ). DL CS DL CS DL CS DL DL CS 3 DL DL DL CS CS DL 1 16 CS DL CS DL CS CS DL CS CS DL CS 3 DL CS CS DL SimpleScalar Toolset [9] Version 3.0d sim-outorder SimpleScalar 3bit MIPS [10] PISA Alpha AXP [11]. PISA 1 SPEC CPU 000 [1] 10 SimpleScakar gcc O [13] SimpleScalar sim-safe SPEC CPU 000 SPEC CPU 000 Reference 0 3
5 1 Type (gshare, K ) BTB 51, 4 RAS 3 8 /cc 8 /cc IFQ 8 RUU 64 LSQ 3 L1 3KB (64B/,, 56 ) L1 3KB (64B/, 1, 51 ) L MB (64B/, 4, 819 ) L1 1 cc L 16 cc 50 cc 8B ITLB, DTLB 1M (4KB/, 56 /, 4 ) 30 cc ( ) ALU 4, 1 cc, 1 cc Mult. 1, 3 cc, 1 cc Div. 1, 0 cc, 19 cc ( ) ALU 4, cc, 1 cc Mult. 1, 4 cc, 1 cc Div. 1, 1 cc, 1 cc SQRT 1, 4 cc, 4 cc (cc: clock cycle(s)) 177.mesa art 183.equake 188.ammp 164.gzip 176.gcc C 181.mcf 197.parser 55.vortex 56.bzip 3. DL DL DL L DL 179.art, 188.ammp, 181.mcf : DL 80-90% DL DL 183.equake, 164.gzip, 197.parser, 55.bzip: % DL (%) DL mesa 179.art 183.equake 188.ammp 164.gzip 176.gcc 181.mcf 197.parser 55.vortex 56.bzip 177mesa 179art 183equake 188ammp 164gzip 176gcc 181mcf 197parser 55vortex 56bzip 3 CS 177.mesa, 176.gcc, 55.vortex: 10% 3. 3 CS DL CS DL PC DL L DL CS 3 3 DL CS DL CS 3. 4 CS DL 3. 3 DL CS CS DL CS 3. 3 (179.art, 188.ammp, 181.mcf ) 4, 5, 6, DL 4
6 CS DL PC CS PC DL PC DL L DL DL CS ammp 16 L DL (PC) (PC) 400f (179.art, 188.ammp, 181.mcf ) 4, 5, art: (PC) 400bb8, 401d ammp: (PC) 40ad mcf : 179.art, 188.ammp CS CS CS 4. DL CS [1] J. D. Collins, H. Wang, D. M. Tullsen, C. Hughes, G. Hoflener, D. Lavery and J. P. Shen: Speculative precomputation: Long-range prefetching of delinquent loads, Proc of the 8th Intl. Symposium on Computer Architecture (001). [] A. Roth and G. Sohi: Speculative data-driven multithreading, Proc of the 7th Intl. Symposium on High-Performance Computer Architecture (001). [3] D. Kim and D. Yeung: Design and evaluation of compiler algorithms for pre-execution, Proc of the 10th Intl. Conference on Architectural Support for Programming Languages and Operating Systems (00). [4] S. S. Liao, P. H. Wang, H. Wang, G. Hoflener, D. Lavery and J. P. Shen: Post-pass binary adaptation for softwarebased speculative precomputation, Proc of the ACM SIG- PLAN 00 Conference on Programming Language Design and Implementation (00). [5] C. K. Luk: Tolerating memory latency through softwarecontrolled pre-execution in simultaneous multithreading processor, Proc of the 8th Intl. Symposium on Computer Architecture (001). [6] M. Annavaram, J. M. Patel and E. S. Davidson: Data prefetching by dependence graph precomputation, Proc of the 8th Intl. Symposium on Computer Architecture (001). [7] A. Moshovos, D. N. Pnevmatikatos and A. Baniasadi: Slice-processors, Proc of the Intl. Conference on Supercomputiong (001). [8],, V. M. G. Ferreira,,,, 004-ARC-160 (004). [9] D. Burger and T. M. Austin: The simplescalar tool set, version.0, University of Wisconsin-Madison Computer Sciences Department Technical Report (1997). [10] J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, T. Gross, F. Baskett and J. Gill: Mips: A microprocessor architecture, Proceedings of the 15th annual workshop on Microprogramming (198). [11] R. L. Sites: Alpha axp architecture, Communications of the ACM, 36, pp (1993). [1] J. L. Henning: Spec cpu000: Measuring cpu performance in the new millennium, 33, 7 (000). [13] M. Oskin: Pisa gcc.7..3 cross compiler. DL CS DL DL DL CS CS DL 5
7 DL1_401d18 DL15_4009f CS_4038 DL16_40108 CS_400f48 DL14_403c CS_403df0 CS_403cd0 DL8_401a CS_400ed0 DL15_4038e8 CS_400a8 797 DL6_401a CS_ DL14_4038f0 1 CS_400a30 DL11_4007c CS_40e DL5_401ef0 DL16_400b0 DL3_401d CS_4031d8 DL13_40390 DL8_48b CS_400a00 CS_48d10 CS_48e80 DL16_40d CS_40930 CS_40e10 DL4_400a CS_400a88 DL7_ CS_48cb8 77 DL8_4037f CS_40d30 8 DL9_401cc DL_401ef DL14_400a CS_40148 DL6_439c0 DL_40afe8 DL9_40af CS_43890 CS_40ace0 DL7_4037e8 DL13_40d CS_4007b8 CS_40960 DL10_401e CS_401d90 DL1_40aeb CS_40ad90 DL6_ CS_40ea8 DL11_400b DL3_40aff CS_ DL13_ DL5_40ad78 1 CS_40ad98 DL4_403d CS_ DL1_401f CS_400bb8 DL7_400b30 4 DL CS : 179.art 56 DL10_40aea0 DL1_ CS_408b8 5 DL CS : 188.ammp 6 DL CS : 181.mcf 6
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