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1 B

2 CPU pthread

5 4 3.1 perf

6 5 3.1 pthread create perf event open

7 CPU CPU CPU1 CPU CPU 1.2 CPU CPU CPU [1] [2] [12] CPU 2016 CPU L1 L3 3 CPU L1 CPU 1 (LastLevelCache) L3

8 1.3 7 L1,L2 L3 1.3 CPU CPU CPU (Cold Start Miss ) 2 CPU (Capacity Miss) CPU

9 1.4 8 (Conflict Miss) MMU(Memory Management Unit) OS way CPU 1.4 CPU OS ( ) Linux FreeBSD OS 1.3

11 Linux ( ) OS pthread pthread

12 pthread fork-exec 3. pthread 4. perf ( ) PID 7. PID 8. 9.

15 perf PID(Process Identifier) Linux PID pthread pthread create pthread create pthread t PID perf perf Linux CPU MSR(Model Specific Register CPU ) CPU

16 perf perf Linux-4.3 perf perf cpu-cycles bus-cycles instructions branch-instructions or branch-misses alignment-faults page-faults cache-refeerence cache-misses CPU CPU pthread t Linux LD PRELOAD pthread create pthread t 2.1 LD PRELOAD LD PRELOAD pthread create pthread create pthread create

17 pthread create pthread create pthread create dlsym dlsym RTLD NEXT LD PRELOAD gcc constructor main pthread create LD PRELOAD pthread create void a t t r i b u t e ( ( c o n s t r u c t o r ) ) s a v e o r i g i n a l p t h r e a d c r e a t e ( void ){ 2 p t h r e a d c r e a t e o r i g i n a l = ( int ( ) ( p t h r e a d t thread, 3 const p t h r e a d a t t r t a t t r, 4 void ( s t a r t r o u t i n e ) ( void ), void arg ) 5 ) dlsym (RTLD NEXT, p t h r e a d c r e a t e ) ; 6 } 3.1 pthread create pthread create pthread create pthread create pthread t PID PID fork-exec 3.2

18 fork-exec fork LD PRELOAD pipe PID PID PID perf event open PID perf PID perf PID perf event open 64bit read PID perf event open read // p e r f e v e n t o p e n 2 // 3 //

19 struct p e r f e v e n t a t t r g e t P e r f E v e n t A t t r c a c h e M i s s ( ) { 5 struct p e r f e v e n t a t t r e v e n t c a c h e m i s s ; 6 e v e n t c a c h e m i s s = c a l l o c ( 1, s i z e o f ( struct p e r f e v e n t a t t r ) ) ; 7 8 event cachemiss >i n h e r i t = 1 ; // 9 event cachemiss >type = PERF TYPE HW CACHE; 10 event cachemiss >c o n f i g = PERF COUNT HW CACHE LL << 0 11 PERF COUNT HW CACHE OP READ << 8 12 PERF COUNT HW CACHE RESULT MISS << 1 6 ; 13 // 14 // return e v e n t c a c h e m i s s ; 17 } // p e r f e v e n t o p e n C 20 // C s y s c a l l 21 int s y s p e r f e v e n t o p e n w r a p p e r ( struct p e r f e v e n t a t t r a t t r, 22 p i d t pid, 23 int cpu, 24 int group fd, 25 unsigned long f l a g s ){ 26 return s y s c a l l ( 2 9 8, a t t r, pid, cpu, group fd, f l a g s ) ; 27 } int fd = s y s p e r f e v e n t o p e n w r a p p e r ( g e t P e r f E v e n t A t t r cachemiss ( ), 30 pid, 1, 1, 0 ) ; unsigned long int c a c h m i s s v a l u e ; 33 // p e r f e v e n t o p e n 34 // 64 b i t r e a d 35 // 36 read ( fd, &c a c h e m i s s v l a u e, s i z e o f ( unsigned long int ) ) ; 3.2 perf event open 10 CPU ioctl PID

20 /dev ioctl PID task PID task

21 OS Linux CPU Intel Xeon E GHz 8 16 LastLevelCache 20 MB 16 GB 4.2 CPU ( ) ( )

25 Qin [8] Memory Shadowing 5 Valgrind[9] Valgrind Cachegrind[10] 5.2

26 [4] SMT(Simultaneous MultiThreading) SMT CPU SMT [5] VMM(Virtual Machine Monitor) CPU CPU CPU Memorybound CPU CPU Memorybound CPU CPU VMM Linux [6] Zhuravlev [12]

27 [1] 6.2 perf L1

28 bit(unsigned long int) pthread pthread Linux clone LD PRELOAD clone C 6.5 pthread

29 OS

30 29 [1] Zhuravlev, Sergey, Saez, Juan Carlos, Blagodurov, Sergey, Fedorova, Alexandra, and Prieto, Manue: Survey of Scheduling Techniques for Addressing Shared Resources in Multicore Processors. ACM Comput. Surv. Vol.45, No.1, pp.4:1 4:28 [2] Nestbit, K. J., Aggarwal, N., Laudon, J., and Smith, J. E.: Fair queuing memory systems. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 39). pp [3],,:,. (SIG 12(ACS 11)), Vol.46, No.12, pp , [4],,: SMT,. (SIG 12(ACS 11)), Vol.46, No.12, pp , [5],,,,: CPU L2 VM, OS-112(1), pp.1 9 [6],,,,,:, ARC-184(11), pp.1 10 [7] Chen, Shimin, Gibbons, Phillip B., Kozuch, Michael, Liaskovitis, Vasileios, Ailamaki, Anastassia, Blelloch, Guy E, Falsafi, Babak, Fix, Limor, Hardavellas, Nikos, Mowry, Todd C., and Wilkerson, Chris,: Scheduling threads for constructive cache sharing on CMPs, Proceeding SPAA 07 Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures, pp [8] Zhao, Qin, Koh, David, Raza, Syed, Bruening, Derek, Wong, Weng-Fai, and Amarasinghe, Saman,: Dynamic Cache Contention Detection in Multi-threaded Applications, Proceedings of the 7th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments, Vol.46, No.7, pp (Mar. 2011). [9] Valgrind [10] Cachegrind

31 30 [11] Sujay Parekh, Susan Eggers, Henry Levy, and Jack Lo,: Thread-Sensitive Scheduling for SMT Processors, Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 10). pp [12] Zhuravlev, Sergey, Blagodurov, Sergey, and Fedorova, Alexandra,: Addressing Shared Resource Contention in Multicore Processors via Scheduling, Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 10). pp

,4) 1 P% P%P=2.5 5%!%! (1) = (2) l l Figure 1 A compilation flow of the proposing sampling based architecture simulation

,4) 1 P% P%P=2.5 5%!%! (1) = (2) l l Figure 1 A compilation flow of the proposing sampling based architecture simulation 1 1 1 1 SPEC CPU 2000 EQUAKE 1.6 50 500 A Parallelizing Compiler Cooperative Multicore Architecture Simulator with Changeover Mechanism of Simulation Modes GAKUHO TAGUCHI 1 YOUICHI ABE 1 KEIJI KIMURA 1