1 Hybrid Memory Cube HMC CPU HMC 2. Hybrid Memory Cube HMC 2.1 Hybrid Memory Cube (HMC) Micron HMC DDR DRAM TSV I/O HMC 1 1 (Vault ) 4 4 HMC DDR
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1 Micron 3 Hybrid Memory Cube (HMC) HPC SPARC64 XIfx HMC CPU SPARC 64XIfx HMC CPU HMC 1. CPU DRAM 3 LSI 3 Wide I/O[1] Hybrid Memory Cube (HMC)[2], [3] 3 3 CPU DIMM HMC CPU DRAM 4 8 CPU 1 Graduate School of Information Systems, The University of Electro-Communications 2 Graduate School of Information Science and Technology, The University of Tokyo 3 Graduate School of Fundamental Science and Engineering, Waseda University CPU CPU CPU HMC SPARC64 XIfx [4], [5] DDR DRAM 480GB/sec HMC 1 4GB CPU DIMM DDR HPC HMC HMC [3] HMC c 2014 Information Processing Society of Japan 1
2 1 Hybrid Memory Cube HMC CPU HMC 2. Hybrid Memory Cube HMC 2.1 Hybrid Memory Cube (HMC) Micron HMC DDR DRAM TSV I/O HMC 1 1 (Vault ) 4 4 HMC DDR 3 1 HMC DDR HMC 10Gbps 15Gbps HMC GB/sec 2 HMC HMC HMC pass-thru Link Host Link 2 HMC HMC ID ID HMC 16-Byte 2.2 HMC Micron HMC Xilinx Altela HMC [6] HPC SPARC64 XIfx HMC [4], [5] SPARC64 XIfx HMC 1 Vault 4 DRAM 4 4GB GB/sec 240GB/sec 2.3 HMC 3 c 2014 Information Processing Society of Japan 2
3 3 SPARC64 XIfx 4 2 HMC SPARC64 XIfx 1.1TFLOPS SPARC64 VIIIfx 8.6 FX10 SPARC64 IXfx 4.7 SPARC64 VIIIfx 2 SPARC64 IXfx HPC HMC HMC HMC HMC HMC Hop HMC HMC 3. HMC SPARC64 XIfx HMC 3.1 1CPU HMC (1) 2-link HMC Module 2-link HMC 3 SPARC64 XIfx 2 1 Host Link 1 Pass-thru Link HMC * x4x2chain 1 Host Link CPU CPU ( )+ 1x4x2chain HMC CPU Host Link 1 4 CPU CPU 2 single: HMC CPU chain: HMC daisy-chain ring: chain mesh: HMC 2 HMC 1 Pass-thru Link chain ring ID chain ring CPU HMC *1 c 2014 Information Processing Society of Japan 3
4 2 CPU Clock 3GHz L1 Cache size 64KB L2 Cache size 256KB Cache coherence Directory-based MOESI HMC CPU HMC Hop 5 4 HMC HMC HMC Hop chain ring HMC 2 HMC mesh (2) 4-link HMC Module 5 4 HMC 4 HMC CPU 1 HMC CPU HMC 4 HMC 1x4x4mesh 1 Hop 3.2 HMC CPU HMC CPU HMC 3.3 CPU CPU () HPC CPU HMC CPU CPU [19] HMC CPU CPU CPU CPU CPU HMC 3.2 gem5+ruby NoC HMC HMC 3 2 NAS Parallel Benchmarks NPB CLASS=W ( 4) c 2014 Information Processing Society of Japan 4
5 1 2linkHMC 4linkHMC Hop Hop (w/alt.pass) 2x2x1single 1 1 no no low 1x4x1chain 1 1 high no low 1x4x2chain 2 2 high no middle 1x4x4chain 4 4 high no middle 1x4x4ring 4 8 high high high 4x1x1single 1 1 no low low 2x2x1chain 1 1 high low low 2x2x2chain 2 2 high low middle 2x2x4chain 4 4 high low middle 2x4x2ring 4 8 high high high 1x4x4mesh 4 11 very high very high very high 3 HMC HMC 128MB DRAM Timing tras=22, trp=11 Hop Latency 5ns 4 NPB CG EP FT IS LU MG HMC HMC 4 6 Hop IPC 4.2 Hop IPC HMC Hop IPC HMC Hop IPC CPU 2 Hop Hop HMC CPU HMC Hop 1 5 IPC 7 Hop IPC CG Hop 5 IPC 29% FT 7% IPC Hop 4.3 IPC IPC c 2014 Information Processing Society of Japan 5
6 9 4 HMC 2 4 Hop HMC IPC 2 IPC CG IPC 2 4 Hop Hop 2 4 IPC 10 4 HMC 4 2 HMC 2 4 HMC 8KB 7 8 HMC CPU 2x2x1single 1x4x1chain IPC Hop HMC IPC 2 2x2x1single IPC 4 1x4x1chain IPC CG 4 1x4x2chain IPC 1x4x4chain 1x4x4ring Hop IPC IS LU Hop IPC IS 2x2x1single 1x4x % 4 9.1% IPC CPU HMC IPC 4 HMC CPU HMC 2 HMC 1 HMC 4 1 IPC 11 IPC 7 EP FT Hop CG LU MG Hop 4 1x4x4chain 2x2x4chain 1% 2% IPC L2 HPC 5. 3 LSI MCM Multi-Chip Module [7], [8] ThroughSilicon Via (TSV) [9], [10], [11] [12], [13] 3 SRAM DRAM Black SRAM DRAM IPC c 2014 Information Processing Society of Japan 6
7 11 IPC IPC 15% [14]DRAM [15], [16] MRAM PRAM [17] HMC DRAM 3 Wide I/O[1] SoC DRAM DRAM JEDEC HBM (High Bandwidth Memory)[18] Wide I/O 3 TSV CPU LSI 1Tbps HMC Kim [19] HMC HMC Hop IPC Hop 1 4 IPC 9.1% HMC Hop IPC Hop IPC 2% IPC CPU JSPS (CREST) [1] S. Dumas, Mobile Memory Forum: LPDDR3 and WideIO, JEDEC Mobile Forum, [2] J.T. Pawlowski, Hybrid memory cube (HMC) HotChips 23, [3] Hybrid Memory Cube Consortium, Hybrid Memory Cube Specification 1.0, [4] FUJITSU LIMITED, Next-Generation PRIMEHPC, [5] T. Shimizu, Fujitsu HPC Roadmap Beyond Petascale Computing, [6] ALTERA, FPGA HMC, WP , [7] F. Carson, B3D SiP developments and trends in 3D Packag, International Conference and Exhibition on Device Packaging, [8] M. Dreiza, A. Yoshida, K. Ishibashi, and T. Maeda, c 2014 Information Processing Society of Japan 7
8 High Density PoP (Package-on-Package) and Package Stacking Development, Proc. 57th Electronic Components and Technology Conference (ECTC 2007), pp , [9] R. Islam, C. Brubaker, P. Lindner and C. Schaefer, Wafer Level Packaging and 3D Interconnect for IC Technology, Proc. 13th Advanced Semiconductor Manufacturing Conference, pp , [10] N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, and K. Takahashi, Mechanical effects of copper through-vias in a 3D die-stacked module, Proc. Electronic Components and Technology Conference, pp , [11] W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, and P.D. Franzon, Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design and Test of Computers, vol.22, no.6, pp , [12] K. Kanda, D.D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, 1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme, Proc. Int l Solid-State Circuits Conf. (ISSCC 03), pp , [13] N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, A 0.14pJ/b Inductive-Coupling interchip Data Transceiver with Digitally- Controlled Precise Pulse Shaping, Proc. Int l Solid-State Circuits Conf.(ISSCC 07), pp , [14] B. Black M. Annavaram, N. Brekelbaum, and J. DeVale, Die Stacking (3D) Microarchitecture, Proc. 39th International Symposium on Microarchitecture (MICRO 06), pp [15] G. H. Loh, 3D-Stacked Memory Architectures for Multi-Core Processors, Porc. 35th International Symposium on Computer Architecture (ISCA 08), pp , [16] D.H. Woo, N.H. Seong, D.L. Lewis, and H-H.S. Lee, An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth, Proc. 16th International Symposium on High Performance Computer Architecture, (HPCA 2010). pp.1 12, [17] G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs, Proc. 15th International Symposium on High Performance Computer Architecture, (HPCA 2009). pp , [18] JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, JEDEC STANDARD High Bandwidth Memory (HBM) DRAM, JESD235, [19] G. Kim, J. Kim, J.H. Ahn, and J. Kim, Memorycentric System Interconnect Design with Hybrid Memo ry Cubes, Proc. PACT2014, pp , c 2014 Information Processing Society of Japan 8
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