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1 BGA/CSPSIP Series No.179

2 C o n t e n t s Feature... 2 Special Issue BGA/CSPSIP , *,, * Series Challenge of Intelligence for Future BREAK THROUGH

3 2, 30,,,,, 3 ITRS, 1, 10402, ,, 0603, 2001JEITA, , LSI,,,, 1, LSI,,,,,, ALSI, B, A B 2,,,,, SELETESELETE LSI300, SELETE SELETE,,, ASET,,,, LSI,,,,,,, A, B,,,, A,,, 1 LSIITRS1999 Year Hand-Held High-Performance Challenge of Intelligence for Future BREAK THROUGH

4 , 0.1µm2005, , 4,,,,, CSPBGA,,,,,, 75,, 8 40,,, LSI,, 2 1MOS, 1, CR LSI,,,,,,,,, 1,, Low-k, FEOL 1 MOS 1 5, 1,,, Paranoia, 109,,, 101,,,,,, BEOL, Challenge of Intelligence for Future BREAK THROUGH

5 BGA/CSPSIP , 1,000,,,, 21, 1,,, 1.2,, EMSElectronics Manufacturing Service,,,,, KEY WORDS Foundry Subcontractor EMSElectronicd Manufacturing Service CSPChip Size Package SiPSystem In a Package Module CSPChip Size Package, QFPQuad Flat Pack, BGA Ball Grid Array,,, BGA QFP, CSP CSP,, FCFlip Chip 4 Challenge of Intelligence for Future BREAK THROUGH

6 2.2, KGDKnown Good Die,,, 5,,, KGD 1, CSP2, WSCSP 3, c44,, 10, 2.3, SiP 1,,,,, DCADirect Chip Attach,, PKG Ecologically Protected Chip Bare Chip Interposer Interposer BGA FBGA CSP FC KGD CSP 3 4,,,,,,,,, PC,,,,,,,,,,,,, SiP,,,,,, DCA,,, 2,,, SoCSystem On a Chip, SoC,, IP, IP SiPSystem In a Package SoCSiP,, Challenge of Intelligence for Future BREAK THROUGH

7 3SoC 3.1,, MCMMulti Chip Module,,, SSI1, LSI, SoC,,,,,,,,, 1,,,,, SoC, 1,,,,, TAT,,,, BGA/CSP WSCSP CSP,,,, 3.2,,,,,, LSI,,,, CSCustomer Satisfaction, CSP,,, 1,LSI, FC60,,,, 1, 10,, 3,,, System Device Package Product outline Floor plan PKG outline CSP Board layout One Chip/Module System Design Device Design Package Design Challenge of Intelligence for Future BREAK THROUGH

8 ,,,, 3, LSI,,,, 4,,,,,,,,, MP3,,,, CSP,,, jpo.go.jp/index.htm INDEX jpo.go.jp/techno/tt _techno.htm, Tessera,,,,,,, SiP,,,, 1CSP, CSPII, Challenge of Intelligence for Future BREAK THROUGH

9 ,, LSI,, 02 21, 110µm 1, 2,,,, 100 Package Package Package Design Ruleµm Technology Vacuum Interconnect Tr.Gate Upper Layer Lower Layer Tr.Gate Superconnect Upper Layer Middle Layer Lower Layer Tr.Gate M. Kimura, "Superconnect: 21st century LSI Production and Design Method", Nikkei Microdevices, No.180, pp.62-79, June Past Present Future 1 Superconnect Technology Heat Sink DRAM ANALOG RF/ANALOG KEY WORDS Superconnect LSISystem LSI Assembly Vertical Cooperation PURE LOGIC K.Ohsawa, H.Odaira, M.Ohsawa, S.Hirade, T.Iijima, S.G.Pierce, "3-D Assembly Interposer Technology for Next-Generation Integrated Systems," ISSCC Digest of Tech. Papers, pp , Feb Superconnect Example Based on Three-Diensional Assembly 8 Challenge of Intelligence for Future BREAK THROUGH

10 , 10µm,,, 10µm,,,, 1,, 3, 4,, LSILSI 1, LSI, 2, LSI1/4 LSI,,, LSI, LSI, IP,, LSIIP,, LSIAB, LSI,, IP, LSI,, LSI, LSI, 3, DRAM,,,, DRAM, LSI FPGA, 40, FPGA,,, 1 LSI, AB LSI [mm] 100 [mw] 1,000 Off-Chip [GB/ sec] 1,000 [mm 2 /bit] 1,000 On-Chip [AU] 1,000 [day] 1,000 IP, AB, Superconnect LSI , A Design Rule Band Width Area Cost /Line Turn/Around Time AB LSI, AB, 3 Superconnect Challenge of Intelligence for Future BREAK THROUGH

11 Logic SRAM Flash Memory Embeded DRAM CMOS RF FPGA MEMS FeRAM Chemical Sensors Electro-Optical Electro-Biological '98 '00 '02 '04 '06 '08 '10 '12 RF: Radio Frequency FPGA: Field Programmable Gate Array MEMS: Micro Electro Mechanical Systems FeRAM: Ferroelectric RAM Year ITRS'99 4 Technologies Intergrated on a Chip, 4 2, 3,,,,, 1,,,, LSI, 10µm2 2LSI ISSCC,, 2, Giga-Scale IntegrationGSI GSI, GSI,,, IR 10µm GSI LSI,, LSI ITRS 1,,,,, 1Known Good DieKGD, KGD,, KGD,, KGD,, 10µm,,, 10µm,,,,,,,, 5, 10 Challenge of Intelligence for Future BREAK THROUGH

12 U.S. LSI LSI U.S. LSI LSI ASIC,, SoC CPU SoC SiP 5,,,,,,, OFF! Guidebook for in situ Bioremediation Theory and Practice A ,000 7 Challenge of Intelligence for Future BREAK THROUGH

13 1 LSI,, Cu,,,,,,, LSI KEY WORDS, *,, * 03 Wafer Stacking Three-Dimensional LSI Buried Interconnection Microbump Wafer Thinning Three-Dimensional Wafer Aligner Three-Dimensional Computer Chip Three-Dimensional Shared Memory Three-Dimensionally Stacked Image Processing Chip Three-Dimensionally Stacked Artificial Retina Chip , 2 2,,,,,, Au/In In, N MOSFET Si Si MOSFET Si P N N P P SiO2 AL MOSFET Si Substrate MOSFET P P N AL N Buried Interconnection AL N AL SiO2 P 1 Micro-Bump Adhesive Layer 12 Challenge of Intelligence for Future BREAK THROUGH

Process Flow for 3D Integration Buried Interconnection 2D LSI Si MOSFET Quartz

Micro-Bump 3 SEM 3D LSI Upper wafer 2 Lower wafer before Alignment after

1 nmµm, µm, µm, 23µmµm 3 Inductive Coupling Plasma - ICP55µm,, 0.

14 Process Flow for 3D Integration Buried Interconnection 2D LSI Si MOSFET Quartz Glass Grinding and Bump Formation apoly-si bpoly-si Alignment and Gluing Micro-Bump 3 SEM 3D LSI Upper wafer 2 Lower wafer before Alignment after Alignment, 1, , 2.1 nmµm, µm, µm, 23µmµm 3 Inductive Coupling Plasma - ICP55µm,, 0.4mΩ cm SEM3,, 1µm, 50µm 4,, Chemical Mechanical Polishing - CMP, 30µm 60.5µm 2.2,,, x, y, z50nm,,,,,, 4 Challenge of Intelligence for Future BREAK THROUGH

15 , 4,,, SEM52µm 0.1Ω Upper Si Substrate In/Au bump 10 µm10 µm 2 µm 5 µm5 µm Insulating epoxy adhesive Polymide Lower Si Substrate 5 SEM 3, 6, 7, 8,, 5-7 6, SRAM DRAM, 3D-PE, 7, DRAMSRAM,, DRAM DRAM 3D MLM 3D ASIC DRAM SRAM Micro Processor 3D ASIC 3D MLM 6 Layer 1 Layer 2 Layer 3 Memory Cell Array 1 Memory Cell Array 3 Memory Cell Array 5 PE1 Sense Amp 1 PE3 Sense Amp 3 PE5 Sense Amp 5 Broadcast Bus Sense Amp 2 Broadcast Bus Sense Amp 4 Broadcast Bus Sense Amp 6 PE2 Memory Cell Array 2 PE4 Memory Cell Array 4 PE6 Memory Cell Array 6 ADC ADC ADC Image Sensor Array Amplifier & ADC Data Latch & Masking Processor Array & Output Circuit Challenge of Intelligence for Future BREAK THROUGH

V 0 "H" Write "L" Write "H" Write "H" Broadcast "L" Broadcast time5 us/div "H" Broadcast 10 Quartz Glass Buried Interconnections Photodiode

16 , 8,,,,,, 1,,,,,,, 1,,, 8,,, Memory Layer 1 Buried Interconnection Memory Layer 2 In-Au Bump Memory Layer 3 9 SEM Precharge Data WE Broadcast 5 1st Layer Sense Amp.V 0 5 2nd Layer Sense Amp.V 0 5 3rd Layer Sense Amp.V 0 "H" Write "L" Write "H" Write "H" Broadcast "L" Broadcast time5 us/div "H" Broadcast 10 Quartz Glass Buried Interconnections Photodiode Photorecepter layer Epoxy adhesive In-An Bump NMOSFET CMOS circuit layer Photodiode N Buried P-Sub interconnection NMOSFET Gate Source Drain NMOSFET 11 SEM Challenge of Intelligence for Future BREAK THROUGH

17 Light CurrentA Light Intensitylx 12 9 SEM ,, 12, 3 11 SEM 10 3, MOS 1212, 4 LSI,,, 1T. Matsumoto, M. Koyanagi et al.: Ext. Abstr. Intern. Conf. on Solid State Devices and Materials, pp M. Koyanagi: Proc. IEEE Intern. Workshop on Chip Package Co-Design, pp K. W. Lee, M. Koyanagi et al.: Ext. Abstr. Intern. Conf. On Solid State Devices and Materials, pp T. Matsumoto, M. Koyanagi et al.: Ext. Abstr. Intern. Conf. On Solid State Devices and Materials, pp M. Koyanagi et al.: IEEE MICRO, pp K. Hirano, M. Koyanagi et al.: Ext. Abstr. Intern. Conf. on Solid State Devices and Materials, pp M. Koyanagi: Ext. Abstr. Intern. Conf. on Solid State Devices and Materials, pp M. Koyanagi et al.: Dig. Tech. Papers, ISSCC, pp K. W. Lee, M. Koyanagi et al.: Tech. Dig. IEDM, pp H. Kurino, M. Koyanagi et al.: Tech. Dig. IEDM, pp Challenge of Intelligence for Future BREAK THROUGH

18 1 1, 1.1,,, 1,,,,, 1 21,,, 26 2, 607, , 1 2, , ,, , 2, Challenge of Intelligence for Future BREAK THROUGH

19 2,, PCB,,,,,,,,,,,,,,,,,,,,,,,,, 3,3--4,4-,,,,,,,,,,,,,,,,,,,,,, 3,, 1,2-, 1,2-,, 1,1,2,2,-,,,,,,,,,,,,,,,,,,,,,,, 1,4-,, N,N-,,,,, 1,1,1-,, 1-, 2-,,,,,,,,,,,, A 1 2, 330,,, ACGIH,, B ,, 2,,,,,, , AB,, 12,, ,,,,,,,,,, 1.3, 18 Challenge of Intelligence for Future BREAK THROUGH

20 Challenge of Intelligence for Future BREAK THROUGH

21 3-7,,,,,,,,, 3-5, MSDS,,,, ISO14001, Challenge of Intelligence for Future BREAK THROUGH

22 , 71 SIPEC,,,,, SIPEC,,,,,,,,, BreakThrough,,, FOMA,,, FOMA,,,,,,,,,,,,,,,,, BreakThrough, SIPEC, Challenge of Intelligence for Future BREAK THROUGH

スライド 1

スライド 1 SoC -SWG ATE -SWG 2004 2005 1 SEAJ 2 VLSI 3 How can we improve manageability of the divergence between validation and manufacturing equipment? What is the cost and capability optimal SOC test approach?