ＶＬＳＩ工学

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なつきうみのなか
6 years ago
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1 2008//5/ ()

2 2008//5/ () 2 ()

3 2008//5/ () 3!! A (WCDMA/GSM) DD DoCoMo 905iP905i

4 2008//5/ () 4 minisd P900i SemiConsult SDRAM, MPEG4 UIMIrDA LCD/ AF ADC/DAC IC CCD C-CPUA-CPU DSPSRAM Flash FPC FPC

5 2008//5/ () 5 LSI 00W P d f clk C 2 I I I leak sub g = I sub + I g q exp nk exp ( ) gd ox Gordon E. Moore, ISSCC 2003.

6 2008//5/ () 6 CMOS LSI

7 2008//5/ () 7 CMOS LSI LSI

8 2008//5/ () 8 I I I ds dsat U = µ Cox 2 = µ C 2 W L ox W L leak = I k q so G MOS ( ) gs α ( ), W exp nu D S α Ids, α.3 ID(M52) (A) {LOG0(ID(M52))} I leak =0-9 A 2.0m.6m.2m 0.8m 0.4m =0.3 ID(M52) {LOG0(I () I dsat =.7mA

9 2008//5/ () 9 pd CMOS I dsat ) C 2I dsat 2) P d = f 5 0 PULSE 0.5 p 0.n 0.n 0n 20n C pd 2 o.5 M48 PB30 M=20 2 M42 NB30 M=0 C + 2p 2 α C I leak o.5 M5 PB30 M=20 22 M50 NB30 M=0 α RANSIEN RESPONSES () pd =.3ns (22) n 0n 5n 20n 25n 30n IME (s) pd =.0ns (20) (2)

10 2008//5/ () 0 pd C α α / P = f C 2 d I leak = I so W exp nu

11 2008//5/ ()

12 2008//5/ () 2 2 2, d d C f P E C f P = = = α α pd C ( ) α α α α α η = η = η = pd C C C E

13 E pd = η C ( ) α um CMOSED d( E d pd ) 3 = 0 = α 3 α 3 =.3 =.7 =. 8 J. Rabaey, et al., Digital Integrated Circuits Prentice Hall 2008//5/ () 3

14 2008//5/ () 4 [=]

15 0 3 P0 P = = OU = A + B 4 4 NAND A 0 0 B 0 0 OU P P P P0 = = = 9 6 ( P )( P ) = P A B P P P0 = = 4 4 P = = A B OU P A, P B A,B J. Rabaey, et al., Digital Integrated Circuits Prentice Hall 2008//5/ () 5

16 2008//5/ () 6 CMOS 2 t d C f P P

17 2008//5/ () I = I W exp leak so nu a.u.

18 2008//5/ () 8 Ioff (na/u) 0,000, nm 65nm 90nm 0.3µ 0.8µ 0.25µ emp (C) Assume: 0.25µm, I off = na/µ 5X increase each generation at 30ºC

19 2008//5/ () 9 Operating oltage () Delay time (Arbitral) Low leak (3pA/um) pd L α Design rule (um)

20 2008//5/ () 20 R R

21 2008//5/ () 2 H ds gs W H = FB + 2φ F + 2ε s ε 0 qn C ox A ( 2φ F ) n + x ) ox ( I( x ) b L X po X n + γ = 2φ H H F = 2φ FB F + 2φ F b + 2ε s ε 0 qn A C ( 2φ ox F ( ) b + 2φ φ = 2 2qN C A ox ε s ε o H 0 + γ F b ) F

22 2008//5/ () 22 n Log I ds (A) 0.4umNMOS (0/0.4) gs ()

23 2008//5/ () 23 I 0.um gd L eff ( ) exp 5.6 gd ox (A/cm 2 ) (nm)

24 2008//5/ () 24 LSI Memory I/O I/O MPU Clock Memory MPU2 Clock Logic Logic I/O Clock Clock Memory ASSP Logic I/O ASSP2 Logic Memory

25 2008//5/ () 25 /0 LSI75% Power consumption (A.U) Clock /2 F/F F/F 3.0->.5 (0.6) (0.6) /5 0.35um 0.35um 0. 8um

26 2008//5/ () 26 r2 r3 r4

27 F/F F/F Power consumption (uw) (A) (B) (C) (A) (B) (C) (A) Conventional (B) Differential (C) Memory Data Clock 0.8um, =.8, fclk=00mhz 2008//5/ () 27

28 2008//5/ () 28

29 2008//5/ () 29 he Effect of Clock Gating Clock Gating Non Clock Gating 40% [mw] he Effect of Core Engines WIH the Core Engines WIHOU the Core Engines 37% [mw] 300 DSP CE CE PU MIF DRAM PAD (Core) (not Core)

2008//5/ () 30 DRAM DRAMI/O00 DRAM MPEG4 codec Separate chips Logic & memory DRAM - logic interface DRAM 89mW Speech codec DRAM on a chip 240mW 6Mbit DRAM

30 2008//5/ () 30 DRAM DRAMI/O00 DRAM MPEG4 codec Separate chips Logic & memory DRAM - logic interface DRAM 89mW Speech codec DRAM on a chip 240mW 6Mbit DRAM Host I/F Multiplexer Power 70% power reduction by DRAM embeing alone Courtesy oshiba, ISSCC 2000 DRAM I/F CamDisplayPre- filter PLL I/F I/F MPEG-4 ideo Codec

MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated

1 -- 7 6 2011 11 1 6-1 MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated Injection Logic 6-3 CMOS CMOS NAND NOR CMOS 6-4 6-5 6-1 6-2 CMOS 6-3 6-4 6-5 c 2011 1/(33)