VLSI工学

Size: px
Start display at page:

Download "VLSI工学"

Transcription

1 2008//5/ ()

2 2008//5/ () 2 ()

3 2008//5/ () 3!! A (WCDMA/GSM) DD DoCoMo 905iP905i

4 2008//5/ () 4 minisd P900i SemiConsult SDRAM, MPEG4 UIMIrDA LCD/ AF ADC/DAC IC CCD C-CPUA-CPU DSPSRAM Flash FPC FPC

5 2008//5/ () 5 LSI 00W P d f clk C 2 I I I leak sub g = I sub + I g q exp nk exp ( ) gd ox Gordon E. Moore, ISSCC 2003.

6 2008//5/ () 6 CMOS LSI

7 2008//5/ () 7 CMOS LSI LSI

8 2008//5/ () 8 I I I ds dsat U = µ Cox 2 = µ C 2 W L ox W L leak = I k q so G MOS ( ) gs α ( ), W exp nu D S α Ids, α.3 ID(M52) (A) {LOG0(ID(M52))} I leak =0-9 A 2.0m.6m.2m 0.8m 0.4m =0.3 ID(M52) {LOG0(I () I dsat =.7mA

9 2008//5/ () 9 pd CMOS I dsat ) C 2I dsat 2) P d = f 5 0 PULSE 0.5 p 0.n 0.n 0n 20n C pd 2 o.5 M48 PB30 M=20 2 M42 NB30 M=0 C + 2p 2 α C I leak o.5 M5 PB30 M=20 22 M50 NB30 M=0 α RANSIEN RESPONSES () pd =.3ns (22) n 0n 5n 20n 25n 30n IME (s) pd =.0ns (20) (2)

10 2008//5/ () 0 pd C α α / P = f C 2 d I leak = I so W exp nu

11 2008//5/ ()

12 2008//5/ () 2 2 2, d d C f P E C f P = = = α α pd C ( ) α α α α α η = η = η = pd C C C E

13 E pd = η C ( ) α um CMOSED d( E d pd ) 3 = 0 = α 3 α 3 =.3 =.7 =. 8 J. Rabaey, et al., Digital Integrated Circuits Prentice Hall 2008//5/ () 3

14 2008//5/ () 4 [=]

15 0 3 P0 P = = OU = A + B 4 4 NAND A 0 0 B 0 0 OU P P P P0 = = = 9 6 ( P )( P ) = P A B P P P0 = = 4 4 P = = A B OU P A, P B A,B J. Rabaey, et al., Digital Integrated Circuits Prentice Hall 2008//5/ () 5

16 2008//5/ () 6 CMOS 2 t d C f P P

17 2008//5/ () I = I W exp leak so nu a.u.

18 2008//5/ () 8 Ioff (na/u) 0,000, nm 65nm 90nm 0.3µ 0.8µ 0.25µ emp (C) Assume: 0.25µm, I off = na/µ 5X increase each generation at 30ºC

19 2008//5/ () 9 Operating oltage () Delay time (Arbitral) Low leak (3pA/um) pd L α Design rule (um)

20 2008//5/ () 20 R R

21 2008//5/ () 2 H ds gs W H = FB + 2φ F + 2ε s ε 0 qn C ox A ( 2φ F ) n + x ) ox ( I( x ) b L X po X n + γ = 2φ H H F = 2φ FB F + 2φ F b + 2ε s ε 0 qn A C ( 2φ ox F ( ) b + 2φ φ = 2 2qN C A ox ε s ε o H 0 + γ F b ) F

22 2008//5/ () 22 n Log I ds (A) 0.4umNMOS (0/0.4) gs ()

23 2008//5/ () 23 I 0.um gd L eff ( ) exp 5.6 gd ox (A/cm 2 ) (nm)

24 2008//5/ () 24 LSI Memory I/O I/O MPU Clock Memory MPU2 Clock Logic Logic I/O Clock Clock Memory ASSP Logic I/O ASSP2 Logic Memory

25 2008//5/ () 25 /0 LSI75% Power consumption (A.U) Clock /2 F/F F/F 3.0->.5 (0.6) (0.6) /5 0.35um 0.35um 0. 8um

26 2008//5/ () 26 r2 r3 r4

27 F/F F/F Power consumption (uw) (A) (B) (C) (A) (B) (C) (A) Conventional (B) Differential (C) Memory Data Clock 0.8um, =.8, fclk=00mhz 2008//5/ () 27

28 2008//5/ () 28

29 2008//5/ () 29 he Effect of Clock Gating Clock Gating Non Clock Gating 40% [mw] he Effect of Core Engines WIH the Core Engines WIHOU the Core Engines 37% [mw] 300 DSP CE CE PU MIF DRAM PAD (Core) (not Core)

30 2008//5/ () 30 DRAM DRAMI/O00 DRAM MPEG4 codec Separate chips Logic & memory DRAM - logic interface DRAM 89mW Speech codec DRAM on a chip 240mW 6Mbit DRAM Host I/F Multiplexer Power 70% power reduction by DRAM embeing alone Courtesy oshiba, ISSCC 2000 DRAM I/F CamDisplayPre- filter PLL I/F I/F MPEG-4 ideo Codec

Microsoft PowerPoint - 集積回路工学(11)_LP改_100112

Microsoft PowerPoint - 集積回路工学(11)_LP改_100112 集積回路工学 東京工業大学大学院理工学研究科電子物理工学専攻 松澤昭 2//3 集積回路工学 () () 低消費電力設計 デバイスと回路設計 資料は松澤研のホームページ http://ssc.pe.titech.ac.jp にあります 2//3 集積回路工学 () 2 携帯電話 低消費電力技術無しでは携帯機器は実現しない!! 現在の携帯電話は万能の通信 A 機器である 携帯電話 (WCDMA/GSM)

More information

VLSI工学

VLSI工学 2008/1/15 (12) 1 2008/1/15 (12) 2 (12) http://ssc.pe.titech.ac.jp 2008/1/15 (12) 3 VLSI 100W P d f clk C V 2 dd I I I leak sub g = I sub + I g qv exp nkt exp ( 5. 6V 10T 2. 5) gd T V T ox Gordon E. Moore,

More information

MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated

MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated 1 -- 7 6 2011 11 1 6-1 MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated Injection Logic 6-3 CMOS CMOS NAND NOR CMOS 6-4 6-5 6-1 6-2 CMOS 6-3 6-4 6-5 c 2011 1/(33)

More information

( ) : 1997

( ) : 1997 ( ) 2008 2 17 : 1997 CMOS FET AD-DA All Rights Reserved (c) Yoichi OKABE 2000-present. [ HTML ] [ PDF ] [ ] [ Web ] [ ] [ HTML ] [ PDF ] 1 1 4 1.1..................................... 4 1.2..................................

More information

テストコスト抑制のための技術課題-DFTとATEの観点から

テストコスト抑制のための技術課題-DFTとATEの観点から 2 -at -talk -talk -drop 3 4 5 6 7 Year of Production 2003 2004 2005 2006 2007 2008 Embedded Cores Standardization of core Standard format Standard format Standard format Extension to Extension to test

More information

devicemondai

devicemondai c 2019 i 3 (1) q V I T ε 0 k h c n p (2) T 300 K (3) A ii c 2019 i 1 1 2 13 3 30 4 53 5 78 6 89 7 101 8 112 9 116 A 131 B 132 c 2019 1 1 300 K 1.1 1.5 V 1.1 qv = 1.60 10 19 C 1.5 V = 2.4 10 19 J (1.1)

More information

I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator

I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator - - 18 I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator - - 19 - - 20 N P P - - 21 - - 22 DRAM - - 23 a b MC-Tr avcc=2.5vvbb=-1.5vvpp=4.0v bvcc=1.7vvbb=-1.0vvpp=3.0v

More information

MOS FET c /(17)

MOS FET c /(17) 1 -- 7 1 2008 9 MOS FT 1-1 1-2 1-3 1-4 c 2011 1/(17) 1 -- 7 -- 1 1--1 2008 9 1 1 1 1(a) VVS: Voltage ontrolled Voltage Source v in µ µ µ 1 µ 1 vin 1 + - v in 2 2 1 1 (a) VVS( ) (b) S( ) i in i in 2 2 1

More information

untitled

untitled ITRS2005 DFM STRJ : () 1 ITRS STRJ ITRS2005DFM STRJ DFM ITRS: International Technology Roadmap for Semiconductors STRJ: Semiconductor Technology Roadmap committee of Japan 2 ITRS STRJ 1990 1998 2000 2005

More information

untitled

untitled NJU7704/05 C-MOS ( ) ±1.00.9µA DSP SOT-23-5 SC88A 2 DSP NJU7704/05F NJU7704/05F3 ±1.0 0.9µA typ ( ) 1.5 6.0(0.1 step) ( C ) ( ) Active "L" : NJU770****A Active "H" : NJU770****B Nch : NJU7704 C-MOS : C-MOS

More information

ST 1 MOS MOS 1 1 2 8 1 CMOS CMOS 7mm3mm LSI 10 SSIS

ST 1 MOS MOS 1 1 2 8 1 CMOS CMOS 7mm3mm LSI 10 SSIS No.28 1 SSIS 5 244 38 1600 SSIS 53 2 SSIS Human Net Work Knowledge Chain 3 11 1 SSIS OB SSIS 1 NoSide 2 5 2003 7 RCA 9 11 12 13 ST 1 MOS MOS 1 1 2 8 1 CMOS CMOS 7mm3mm LSI 10 SSIS 21 GM RCA IBM GE WE 20

More information

PowerPoint Presentation

PowerPoint Presentation / 2008/04/04 Ferran Salleras 1 2 40Gb/s 40Gb/s PC QD PC: QD: e.g. PCQD PC/QD 3 CP-ON SP T CP-OFF PC/QD-SMZ T ~ps, 40Gb/s ~100fJ T CP-ON CP-OFF 500µm500µm Photonic Crystal SMZ K. Tajima, JJAP, 1993. Control

More information

エミフィルによるノイズ対策 アプリケーション編

エミフィルによるノイズ対策 アプリケーション編 .pdf Noise Suppression by EMIFIL Application Guide Application Manual Cat.No.C35-2 .pdf .pdf .pdf 2 .pdf CD-ROM Power Supply CPU Gate Array RAM ROM Driver Driver Driver USB Chip Set Mouse Keyboard Display

More information

1 1 H Li Be Na M g B A l C S i N P O S F He N Cl A e K Ca S c T i V C Mn Fe Co Ni Cu Zn Ga Ge As Se B K Rb S Y Z Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb T e

1 1 H Li Be Na M g B A l C S i N P O S F He N Cl A e K Ca S c T i V C Mn Fe Co Ni Cu Zn Ga Ge As Se B K Rb S Y Z Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb T e No. 1 1 1 H Li Be Na M g B A l C S i N P O S F He N Cl A e K Ca S c T i V C Mn Fe Co Ni Cu Zn Ga Ge As Se B K Rb S Y Z Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb T e I X e Cs Ba F Ra Hf Ta W Re Os I Rf Db Sg Bh

More information

untitled

untitled MOSFET 17 1 MOSFET.1 MOS.1.1 MOS.1. MOS.1.3 MOS 4.1.4 8.1.5 9. MOSFET..1 1.. 13..3 18..4 18..5 0..6 1.3 MOSFET.3.1.3. Poon & Yau 3.3.3 LDD MOSFET 5 3.1 3.1.1 6 3.1. 6 3. p MOSFET 3..1 8 3.. 31 3..3 36

More information

Mixed Signal SOC Circuit Design

Mixed Signal SOC Circuit Design 1 STRJ WS: March 4, 2004 STRJ WS: March 4, 2004 2 STRJ WS: March 4, 2004 3 STRJ WS: March 4, 2004 4 DVD TV 12 LSI () STRJ WS: March 4, 2004 5 PC, Flash, CCD 2003.10.27pp.129-130 STRJ WS: March 4, 2004

More information

6 2 T γ T B (6.4) (6.1) [( d nm + 3 ] 2 nt B )a 3 + nt B da 3 = 0 (6.9) na 3 = T B V 3/2 = T B V γ 1 = const. or T B a 2 = const. (6.10) H 2 = 8π kc2

6 2 T γ T B (6.4) (6.1) [( d nm + 3 ] 2 nt B )a 3 + nt B da 3 = 0 (6.9) na 3 = T B V 3/2 = T B V γ 1 = const. or T B a 2 = const. (6.10) H 2 = 8π kc2 1 6 6.1 (??) (P = ρ rad /3) ρ rad T 4 d(ρv ) + PdV = 0 (6.1) dρ rad ρ rad + 4 da a = 0 (6.2) dt T + da a = 0 T 1 a (6.3) ( ) n ρ m = n (m + 12 ) m v2 = n (m + 32 ) T, P = nt (6.4) (6.1) d [(nm + 32 ] )a

More information

(a) 4 1. A v = / 2. A i = / 3. A p = A v A i = ( )/( ) 4. Z i = / 5. Z o = /( ) = 0 2 1

(a) 4 1. A v = / 2. A i = / 3. A p = A v A i = ( )/( ) 4. Z i = / 5. Z o = /( ) = 0 2 1 http://www.ieicehbkb.org/ 1 7 2 1 7 2 2009 2 21 1 1 3 22 23 24 25 2 26 21 22 23 24 25 26 c 2011 1/(22) http://www.ieicehbkb.org/ 1 7 2 1 7 2 21 2009 2 1 1 3 1 211 2 1(a) 4 1. A v = / 2. A i = / 3. A p

More information

MOSFET HiSIM HiSIM2 1

MOSFET HiSIM HiSIM2 1 MOSFET 2007 11 19 HiSIM HiSIM2 1 p/n Junction Shockley - - on-quasi-static - - - Y- HiSIM2 2 Wilson E f E c E g E v Bandgap: E g Fermi Level: E f HiSIM2 3 a Si 1s 2s 2p 3s 3p HiSIM2 4 Fermi-Dirac Distribution

More information

LSI LSI Logic Detection by using Laser Probing Pad

LSI LSI Logic Detection by using Laser Probing Pad LSI LSI Logic Detection by using Laser Probing Pad LPP : Laser Probing Pad() 1 3p 3p 3p 2 4p 2.1 4p 2.2 5p 2.2.1 G6p 2.2.2 7p 2.3 8p 2.4 9p 3 10p 3.1 10p 3.2 11p 4 LPP 13p 4.1 13p 4.2 14p 4.3 15p 4.4 15p

More information

V s d d 2 d n d n 2 n R 2 n V s q n 2 n Output q 2 q Decoder 2 R 2 2R 2R 2R 2R A R R R 2R A A n A n 2R R f R (a) 0 (b) 7.4 D-A (a) (b) FET n H ON p H

V s d d 2 d n d n 2 n R 2 n V s q n 2 n Output q 2 q Decoder 2 R 2 2R 2R 2R 2R A R R R 2R A A n A n 2R R f R (a) 0 (b) 7.4 D-A (a) (b) FET n H ON p H 3 ( ) 208 2 3 7.5 A-D/D-A D-A/A-D A-D/D-A CCD D () ( ) A-D (ADC) D-A (DAC) LSI 7.5. - 7.4(a) n 2 n V S 2 n R ( ),, 2 n i i i V S /2 n MOS i V S /2 n 8 256 MOS 7.4(b) DA n R n 2 2R n MOS 2R R 2R 2R OP OP

More information

Microsoft Word - AK2300-MS0997-J-00_ doc

Microsoft Word - AK2300-MS0997-J-00_ doc AK2300 A-Law -law14bitpcm(16bit ) A/D D/A A-law/μ-law GST VFTN VR AMPT AAF SMF A/D CODEC Core D/A PCM I/F DIF0 DIF1 MUTEN DX DR FS BCLK VREF BGREF Internal Main Clock PLLC VDD VSS LVDD Power Down AK2300

More information

untitled

untitled CMOS 376-851511 0277 (30) 1788 0277 (30)1707 e-mail: k_haruo@el.gunma-u.ac.jp AD AD AD [] AD AD AD [] ISSCC 2007 TSMC ISSCC2007 ISSCC2007 /DAC (regulation) (AGC) ADC/DAC AD AD AD [] AD CMOS SAR ADC Gr),,

More information

Microsoft Word - 章末問題

Microsoft Word - 章末問題 1906 R n m 1 = =1 1 R R= 8h ICP s p s HeNeArXe 1 ns 1 1 1 1 1 17 NaCl 1.3 nm 10nm 3s CuAuAg NaCl CaF - - HeNeAr 1.7(b) 2 2 2d = a + a = 2a d = 2a 2 1 1 N = 8 + 6 = 4 8 2 4 4 2a 3 4 π N πr 3 3 4 ρ = = =

More information

untitled

untitled 1 CMOS 0.35um CMOS, 3V CMOS 2 RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3 RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4 5 f T [GHz] 450 400 350 300 250 200 150 Technology loadmap L[nm] f T [GHz]

More information

1 2 2/17

1 2 2/17 1/17 1 2 2/17 ROM ROM 2 CD-ROM CD CD ROM LSI ROM CD-ROM 3/17 3 http://www.pc-view.net/special/000411/ 4/17 4 http://www.pc-view.net/special/000411/page2.html 5 5/17 6/17 7/17 2PS2 6 8/17 7 9/17 8 10/17

More information

5 1 2 3 4 5 6 7 8 9 10 11 12 1 132 CMOS Setup Utility - Copyright (C) 1984-2000 Award Software Power Management Setup ACPI Suspend Type S3 (STR) Power Management User Define Video Off Method DPMS Video

More information

STRJ WS: March 4, 2003, 設計 TF/PIDS/FEP クロスカット 設計 TF/PIDS/FEP クロスカット報告 低電力 SoC のロードマップ - モバイルマルチメディアへのアプローチ - 設計 TF 主査日立製作所内山邦男

STRJ WS: March 4, 2003, 設計 TF/PIDS/FEP クロスカット 設計 TF/PIDS/FEP クロスカット報告 低電力 SoC のロードマップ - モバイルマルチメディアへのアプローチ - 設計 TF 主査日立製作所内山邦男 設計 TF/PIDS/FEP クロスカット報告 低電力 SoC のロードマップ - モバイルマルチメディアへのアプローチ - 設計 TF 主査日立製作所内山邦男 本クロスカットの目的と活動内容 低電力 SoCのロードマップ作成と問題点 技術課題の明確化 (1) モバイルマルチメディアの動向調査 (2) 現状 (0.18um) の低電力 SoCの分析 (3) 低電力 SoC 設計モデルの作成 ( 初期モデル

More information

untitled

untitled PC murakami@cc.kyushu-u.ac.jp muscle server blade server PC PC + EHPC/Eric (Embedded HPC with Eric) 1216 Compact PCI Compact PCIPC Compact PCISH-4 Compact PCISH-4 Eric Eric EHPC/Eric EHPC/Eric Gigabit

More information

nsg02-13/ky045059301600033210

nsg02-13/ky045059301600033210 φ φ φ φ κ κ α α μ μ α α μ χ et al Neurosci. Res. Trpv J Physiol μ μ α α α β in vivo β β β β β β β β in vitro β γ μ δ μδ δ δ α θ α θ α In Biomechanics at Micro- and Nanoscale Levels, Volume I W W v W

More information

ごあいさつ

ごあいさつ 2004 11 7 10 00 2004 13:0014:00 16 00 2004 3 5N S24 29 34 39 44 49 54 59H1 6 11. URL 1 7 2005 2 1 1210 121 149 187 149 606 137 134 177 156 604 162 11 1 2004 2 1241 135 126 120 233 614 145 131 131 220 627

More information

RW1097-0A-001_V0.1_170106

RW1097-0A-001_V0.1_170106 INTRODUCTION RW1097 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1line/2line/3line/4line/5line/6lines x 12 (16 x 16 dot format) with the

More information

? FPGA FPGA FPGA : : : ? ( ) (FFT) ( ) (Localization) ? : 0. 1 2 3 0. 4 5 6 7 3 8 6 1 5 4 9 2 0. 0 5 6 0 8 8 ( ) ? : LU Ax = b LU : Ax = 211 410 221 x 1 x 2 x 3 = 1 0 0 21 1 2 1 0 0 1 2 x = LUx = b 1 31

More information

analog-control-mod : 2007/2/4(8:44) 2 E8 P M () r e K P ( ) T I u K M T M K D E8.: DC PID K D E8. (E8.) P M () E8.2 K P D () ( T ) (E8.2) K M T M K, T

analog-control-mod : 2007/2/4(8:44) 2 E8 P M () r e K P ( ) T I u K M T M K D E8.: DC PID K D E8. (E8.) P M () E8.2 K P D () ( T ) (E8.2) K M T M K, T analog-control-mod : 2007/2/4(8:44) E8 E8. PID DC. PID 2. DC PID 3. E8.2 DC PID C8 E8. DC PID E6 DC P M () K M ( T M ) (E8.) DC PID C8 E8. r e u E8.2 PID E8. PID analog-control-mod : 2007/2/4(8:44) 2 E8

More information

.5 z = a + b + c n.6 = a sin t y = b cos t dy d a e e b e + e c e e e + e 3 s36 3 a + y = a, b > b 3 s363.7 y = + 3 y = + 3 s364.8 cos a 3 s365.9 y =,

.5 z = a + b + c n.6 = a sin t y = b cos t dy d a e e b e + e c e e e + e 3 s36 3 a + y = a, b > b 3 s363.7 y = + 3 y = + 3 s364.8 cos a 3 s365.9 y =, [ ] IC. r, θ r, θ π, y y = 3 3 = r cos θ r sin θ D D = {, y ; y }, y D r, θ ep y yddy D D 9 s96. d y dt + 3dy + y = cos t dt t = y = e π + e π +. t = π y =.9 s6.3 d y d + dy d + y = y =, dy d = 3 a, b

More information

untitled

untitled Power Wall HPL1 10 B/F EXTREMETECH Supercomputing director bets $2,000 that we won t have exascale computing by 2020 One of the biggest problems standing in our way is power. [] http://www.extremetech.com/computing/155941

More information

36 th IChO : - 3 ( ) , G O O D L U C K final 1

36 th IChO : - 3 ( ) , G O O D L U C K final 1 36 th ICh - - 5 - - : - 3 ( ) - 169 - -, - - - - - - - G D L U C K final 1 1 1.01 2 e 4.00 3 Li 6.94 4 Be 9.01 5 B 10.81 6 C 12.01 7 N 14.01 8 16.00 9 F 19.00 10 Ne 20.18 11 Na 22.99 12 Mg 24.31 Periodic

More information

untitled

untitled LVDS 1 ( LVDS) / 50% 2 ( LVDS) / 50% 3 USB2.0 480Mbps Serial ATA Gen1 1.5Gbps PCI Express Gen1 2.5Gbps 4 Host Data Device Clock 5 Data Skew Host Data Device Clock Setup Hold Data Skew 6 Host Data Device

More information

10 IDM NEC

10 IDM NEC No.29 1 29 SEAJ SEAJ 2 3 63 1 1 2 2002 2003 6 News 9 IEDM 11 13 15 16 17 10 IDM NEC 3 12 3 10 10 2 3 3 20 110 1985 1995 1988 912001 1 1993 95 9798 199010 90 200 2 1950 2 1950 3 1311 10 3 4 4 5 51929 3

More information

2 3 v v S i i L L S i i E i v L E i v 3. L urren (A) approx. 60% E = V = 0 Ω L = 00 mh urren (A) app

2 3 v v S i i L L S i i E i v L E i v 3. L urren (A) approx. 60% E = V = 0 Ω L = 00 mh urren (A) app 3 ON ON L * 3. v() = i() (3.) 3.2 L 3. L = 0 S i() = i () = i L () v () L v L () = 0 L v () = i(), (3.4) v L () = L d i(). (3.5) d v () + v L () = E, (3.6) i () = i L () = i(). (3.7) L d i() + i() = E.

More information

MAX665S//X ABSOLUTE MAXIMUM ATINGS B4P to PKN (MAX665X) to 24 B3P to PKN (MAX665) to 8 B2P to PKN (MAX665S) to 2 BP to PKN, B2P to B

MAX665S//X ABSOLUTE MAXIMUM ATINGS B4P to PKN (MAX665X) to 24 B3P to PKN (MAX665) to 8 B2P to PKN (MAX665S) to 2 BP to PKN, B2P to B 9-65; ev ; / µ µ MAX665S//X PAT MAX665SESA MAX665ESA MAX665XESA TEMP. ANGE -4 C to 85 C -4 C to 85 C -4 C to 85 C PIN- PACKAGE 8 SO 8 SO 8 SO CELL COUNT 2 3 4 TOP IEW () I.C. (B4P) 8 I.C. [B3P] B4P B3P

More information

電子回路I_4.ppt

電子回路I_4.ppt 電子回路 Ⅰ 第 4 回 電子回路 Ⅰ 5 1 講義内容 1. 半導体素子 ( ダイオードとトランジスタ ) 2. 基本回路 3. 増幅回路 電界効果トランジスタ (FET) 基本構造 基本動作動作原理 静特性 電子回路 Ⅰ 5 2 半導体素子 ( ダイオードとトランジスタ ) ダイオード (2 端子素子 ) トランジスタ (3 端子素子 ) バイポーラトランジスタ (Biolar) 電界効果トランジスタ

More information

Taro12-イノベ-ション経営研究会

Taro12-イノベ-ション経営研究会 1 3 4 25. 31 46 54 63 63 71 79 90 BP 101 112 126 135 10 1990 21 1970 80 Made In America 80 90 1987 52 93 98-1 - (1) (2) (3) (4) - 2 - - 3 - ( 1980 1990 1990 10 21 PHP 1998. - 4 - 80 1976~1980 1987 52 1988

More information

N/m f x x L dl U 1 du = T ds pdv + fdl (2.1)

N/m f x x L dl U 1 du = T ds pdv + fdl (2.1) 23 2 2.1 10 5 6 N/m 2 2.1.1 f x x L dl U 1 du = T ds pdv + fdl (2.1) 24 2 dv = 0 dl ( ) U f = T L p,t ( ) S L p,t (2.2) 2 ( ) ( ) S f = L T p,t p,l (2.3) ( ) U f = L p,t + T ( ) f T p,l (2.4) 1 f e ( U/

More information

(4.15a) Hurwitz (4.15a) {a j } (s ) {a j } n n Hurwitz a n 1 a n 3 a n 5 a n a n 2 a n 4 a n 1 a n 3 H = a n a n 2. (4.16)..... a Hurwitz H i H i i H

(4.15a) Hurwitz (4.15a) {a j } (s ) {a j } n n Hurwitz a n 1 a n 3 a n 5 a n a n 2 a n 4 a n 1 a n 3 H = a n a n 2. (4.16)..... a Hurwitz H i H i i H 6 ( ) 218 1 28 4.2.6 4.1 u(t) w(t) K w(t) = Ku(t τ) (4.1) τ Ξ(iω) = exp[ α(ω) iβ(ω)] (4.11) (4.1) exp[ α(ω) iβ(ω)] = K exp( iωτ) (4.12) α(ω) = ln(k), β(ω) = ωτ (4.13) dϕ/dω f T 4.3 ( ) OP-amp Nyquist Hurwitz

More information

富士通セミコンダクター株式会社発表資料

富士通セミコンダクター株式会社発表資料 安心 安全を実現する安全を実現する FM3 マイコン 2012 年 6 月富士通セミコンダクター株式会社マイコンソリューション事業本部五十嵐稔行 Copyright 2010 FUJITSU LIMITED 目次 FM3 ロードマップ 安心 安全への取り組み安全への取り組み 1 Copyright 2010 FUJITSU LIMITED CPUロードマップとITRON系RTOS製品 T-Kernel/μT-Kernel

More information

51505agj.PDF

51505agj.PDF Type No. 2002 7 3 ******** 1.... 2 2.... 3 3.... 7 4. I/O... 9 5.... 11 6.... 12 7.... 16 8.... 16 9.... 16 10.... 17 11.... 18 CORPORATION Page 1/18 1. min. -20max. 70 min. -20max. 70 20 2 5 8 1 83.0

More information

DS

DS FUJITSU SEMICONDUCTOR DATA SHEET DS4 272 1 ASSP (AC / DC ) BIPOLAR, IC,, 2 ma, 5 V SOP 16 1 AC/DC Copyright 1986-211 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 211.5 (TOP VIEW) IN1 1 16 IN2 IN1

More information

1 239 1 1 1 1 1 50 50 2 2 2 1 J1 G 2 20 50 J L AF 2 Y B 2 1 0 20 25 50 3 20 2 50 1 20 50 2 1 1 5 111 115 5 11 11 1 1 5 5 5 1 5 1 5 211 215 2 2 3 3 2 1 5 50 0 50 5 115 2 2 00 5 2 2 252 0 0 1 1 150 13 0

More information

LM193/LM293/LM393/LM 回路入り低動作電圧低オフセット電圧コンパレータ

LM193/LM293/LM393/LM 回路入り低動作電圧低オフセット電圧コンパレータ LM193,LM2903,LM293,LM393 LM193/ Low Power Low Offset Voltage Dual Comparators Literature Number: JAJSB74 2 LM293 2.0mV 2 A/D VCO MOS LM293 TTL CMOS LM293 MOS LM393 LM2903 Micro SMD 8 ( 0.3mm) Squarewave

More information

Microsoft PowerPoint - 集積回路工学(5)_ pptm

Microsoft PowerPoint - 集積回路工学(5)_ pptm 集積回路工学 東京工業大学大学院理工学研究科電子物理工学専攻 松澤昭 2009/0/4 集積回路工学 A.Matuzawa (5MOS 論理回路の電気特性とスケーリング則 資料は松澤研のホームページ htt://c.e.titech.ac.j にあります 2009/0/4 集積回路工学 A.Matuzawa 2 インバータ回路 このようなインバータ回路をシミュレーションした 2009/0/4 集積回路工学

More information

TULを用いたVisual ScalerとTDCの開発

TULを用いたVisual ScalerとTDCの開発 TUL を用いた Visual Scaler と TDC の開発 2009/3/23 原子核物理 4 年 永尾翔 目次 目的と内容 開発環境 J-Lab におけるハイパー核分光 Visual Scaler TDC まとめ & 今後 目的と内容 目的 TUL, QuartusⅡ を用いて実験におけるトリガーを組めるようになる Digital Logic を組んでみる 内容 特徴 TUL,QuartusⅡ

More information

スライド 1

スライド 1 STRJ WS: March 9, 2006, 0.35µm 0.8µm 0.3µm STRJ WS: March 9, 2006, 2 0.35µm Lot-to-Lot, Wafer-to-Wafer, Die-to-Die(D2D) D2D 0.8µm (WID: Within Die) D2D vs. WID 0.3µm D2Dvs. WID STRJ WS: March 9, 2006,

More information

untitled

untitled 0. =. =. (999). 3(983). (980). (985). (966). 3. := :=. A A. A A. := := 4 5 A B A B A B. A = B A B A B B A. A B A B, A B, B. AP { A, P } = { : A, P } = { A P }. A = {0, }, A, {0, }, {0}, {}, A {0}, {}.

More information

1 1 x y = y(x) y, y,..., y (n) : n y F (x, y, y,..., y (n) ) = 0 n F (x, y, y ) = 0 1 y(x) y y = G(x, y) y, y y + p(x)y = q(x) 1 p(x) q(

1 1 x y = y(x) y, y,..., y (n) : n y F (x, y, y,..., y (n) ) = 0 n F (x, y, y ) = 0 1 y(x) y y = G(x, y) y, y y + p(x)y = q(x) 1 p(x) q( 1 1 y = y() y, y,..., y (n) : n y F (, y, y,..., y (n) ) = 0 n F (, y, y ) = 0 1 y() 1.1 1 y y = G(, y) 1.1.1 1 y, y y + p()y = q() 1 p() q() (q() = 0) y + p()y = 0 y y + py = 0 y y = p (log y) = p log

More information

1 osana@eee.u-ryukyu.ac.jp : FPGA : HDL, Xilinx Vivado + Digilent Nexys4 (Artix-7 100T) LSI / PC clock accurate / Artix-7 XC7A100T Kintex-7 XC7K325T : CAD Hands-on: HDL (Verilog) CAD (Vivado HLx) : 28y4

More information

PowerPoint Presentation

PowerPoint Presentation 半導体電子工学 II 神戸大学工学部 電気電子工学科 12/08/'10 半導体電子工学 Ⅱ 1 全体の内容 日付内容 ( 予定 ) 備考 1 10 月 6 日半導体電子工学 I の基礎 ( 復習 ) 11/24/'10 2 10 月 13 日 pn 接合ダイオード (1) 3 10 月 20 日 4 10 月 27 日 5 11 月 10 日 pn 接合ダイオード (2) pn 接合ダイオード (3)

More information

スライド 1

スライド 1 SoC -SWG ATE -SWG 2004 2005 1 SEAJ 2 VLSI 3 How can we improve manageability of the divergence between validation and manufacturing equipment? What is the cost and capability optimal SOC test approach?

More information

Microsoft Word - 11問題表紙(選択).docx

Microsoft Word - 11問題表紙(選択).docx A B A.70g/cm 3 B.74g/cm 3 B C 70at% %A C B at% 80at% %B 350 C γ δ y=00 x-y ρ l S ρ C p k C p ρ C p T ρ l t l S S ξ S t = ( k T ) ξ ( ) S = ( k T) ( ) t y ξ S ξ / t S v T T / t = v T / y 00 x v S dy dx

More information

プロセッサ・アーキテクチャ

プロセッサ・アーキテクチャ 2. NII51002-8.0.0 Nios II Nios II Nios II 2-3 2-4 2-4 2-6 2-7 2-9 I/O 2-18 JTAG Nios II ISA ISA Nios II Nios II Nios II 2 1 Nios II Altera Corporation 2 1 2 1. Nios II Nios II Processor Core JTAG interface

More information

µ

µ MPEG Applications 10000 HDTV HDTV: High Definition TV 1000 SDTV: SDTV Standard Definition TV 100 DVD DVD: Digital Video Decoder VP VP: 10 Video Phone 0 16 32 64 128 256 Memory Capacity (Mbit) Data Rate

More information

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp)

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp) ADC121S625 ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter Literature Number: JAJSAB8 ADC121S625 12 50kSPS 200kSPS A/D ADC121S625 50kSPS 200kSPS 12 A/D 500mV

More information

genron-3

genron-3 " ( K p( pasals! ( kg / m 3 " ( K! v M V! M / V v V / M! 3 ( kg / m v ( v "! v p v # v v pd v ( J / kg p ( $ 3! % S $ ( pv" 3 ( ( 5 pv" pv R" p R!" R " ( K ( 6 ( 7 " pv pv % p % w ' p% S & $ p% v ( J /

More information

sm1ck.eps

sm1ck.eps DATA SHEET DS0 0 ASSP, IC,,,,, (VS =. V.%) (VCC = 0. V ) (VR =. V.%) ( ) DIP, SIP, SOP, (DIP-P-M0) (SIP-P-M0) (FPT-P-M0) (FRONT VIEW) (TOP VIEW) C T C T V S V REF V CC V CC V REF V S (DIP-P-M0) (FPT-P-M0)

More information

LTC ビット、200ksps シリアル・サンプリングADC

LTC ビット、200ksps シリアル・サンプリングADC µ CBUSY ANALOG INPUT 10V TO 10V 2. 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V DIG V ANA PWRD BUSY CS R/C TAG SB/BTC DATA EXT/INT DATACLK DGND SY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10µF 0.1µF SERIAL INTERFACE

More information

M51995AP/AFP データシート

M51995AP/AFP データシート お客様各位 カタログ等資料中の旧社名の扱いについて 21 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

D = [a, b] [c, d] D ij P ij (ξ ij, η ij ) f S(f,, {P ij }) S(f,, {P ij }) = = k m i=1 j=1 m n f(ξ ij, η ij )(x i x i 1 )(y j y j 1 ) = i=1 j

D = [a, b] [c, d] D ij P ij (ξ ij, η ij ) f S(f,, {P ij }) S(f,, {P ij }) = = k m i=1 j=1 m n f(ξ ij, η ij )(x i x i 1 )(y j y j 1 ) = i=1 j 6 6.. [, b] [, d] ij P ij ξ ij, η ij f Sf,, {P ij } Sf,, {P ij } k m i j m fξ ij, η ij i i j j i j i m i j k i i j j m i i j j k i i j j kb d {P ij } lim Sf,, {P ij} kb d f, k [, b] [, d] f, d kb d 6..

More information

ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter (jp)

ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter (jp) 8-Channel, 500 ksps, 12-Bit A/D Converter Literature Number: JAJSA63 8 500kSPS 12 A/D 8 12 CMOS A/D 500kSPS / AIN1 AIN8 8 SPI QSPI MICROWIRE DSP (AV DD ) 2.7V 5.25V (DV DD ) 2.7V AV DD 3V 1.5mW 5V 8.3mW

More information

mobicom.dvi

mobicom.dvi 13Dynamic Voltage Scaling on a Low-Power Microprocessor Johan Pouwelse 5 Koen Langendoen Henk Sips Faculty of Information Technology and Systems Delft University of Technology, The Netherlands 1 78724

More information

橡松下発表資料.PDF

橡松下発表資料.PDF ... TV TV MPEG2 1394 JAVA HTML BML LSI Bluetooth 802.11 Linux PLC Internet ITRON 1. 2. TV -1-2 -3 3. 1. 2. TV -1-2 -3 3. 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 96/9 PerfecTV 98/4 SkyPerfecTV

More information

DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter (jp)

DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter (jp) DAC121S101 DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter Literature Number: JAJSA89 DAC121S101 12 D/A DAC121S101 12 D/A (DAC) 2.7V 5.5V 3.6V 177 A 30MHz 3 SPI TM QSPI MICROWIRE

More information

P361

P361 ΣAD -RFDAC - High-Speed Continuous-Time Bandpass ΣAD Modulator Architecture Employing Sub-Sampling Technnique with 376-8515 1-5-1 Masafumi Uemori Tomonari Ichikawa Haruo Kobayashi Department of Electronic

More information

2015/4/13 10: C C C C John C. Hull,, Steven E. Shreve, (1), Peter E. Kloeden, Eckhard Platen Num

2015/4/13 10: C C C C John C. Hull,, Steven E. Shreve, (1), Peter E. Kloeden, Eckhard Platen Num 2015/4/13 10:56 0 0.1 http://cm.hit-u.ac.jp/~kobayashi/lecture/ 0.2 C C C C John C. Hull,, Steven E. Shreve, (1, Peter E. Kloeden, Eckhard Platen Numerical Solution of Stochastic Differential Equations,

More information

LCR e ix LC AM m k x m x x > 0 x < 0 F x > 0 x < 0 F = k x (k > 0) k x = x(t)

LCR e ix LC AM m k x m x x > 0 x < 0 F x > 0 x < 0 F = k x (k > 0) k x = x(t) 338 7 7.3 LCR 2.4.3 e ix LC AM 7.3.1 7.3.1.1 m k x m x x > 0 x < 0 F x > 0 x < 0 F = k x k > 0 k 5.3.1.1 x = xt 7.3 339 m 2 x t 2 = k x 2 x t 2 = ω 2 0 x ω0 = k m ω 0 1.4.4.3 2 +α 14.9.3.1 5.3.2.1 2 x

More information

研修コーナー

研修コーナー l l l l l l l l l l l α α β l µ l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l

More information

TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA Vac/10 A [85-AA-0003] m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A [ ] 2016

TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA Vac/10 A [85-AA-0003] m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A [ ] 2016 No. IB028901 Nov. 2016 1. 11 TOS7200 2. 14 3. 19 4. 23 5. 39 6. 49 7. 51 TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA5-15 125 Vac/10 A [85-AA-0003] 1 2.5 m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A

More information

1 I

1 I 1 I 3 1 1.1 R x, y R x + y R x y R x, y, z, a, b R (1.1) (x + y) + z = x + (y + z) (1.2) x + y = y + x (1.3) 0 R : 0 + x = x x R (1.4) x R, 1 ( x) R : x + ( x) = 0 (1.5) (x y) z = x (y z) (1.6) x y =

More information

スライド 1

スライド 1 CMOS : swk(at)ic.is.tohoku.ac.jp [ 2003] [Wong1999] 2 : CCD CMOS 3 : CCD Q Q V 4 : CMOS V C 5 6 CMOS light input photon shot noise α quantum efficiency dark current dark current shot noise dt time integration

More information

pc725v0nszxf_j

pc725v0nszxf_j PC725NSZXF PC725NSZXF PC725NSZXF PC725 DE file PC725 Date Jun. 3. 25 SHARP Corporation PC725NSZXF 2 6 5 2 3 4 Anode Cathode NC Emitter 3 4 5 Collector 6 Base PC725NSZXF PC725YSZXF.6 ±.2.2 ±.3 SHARP "S"

More information

NL-22/NL-32取扱説明書_操作編

NL-22/NL-32取扱説明書_操作編 MIC / Preamp ATT NL-32 A C ATT AMP 1 AMP 2 AMP 3 FLAT FLAT CAL.SIG. OVER LOAD DET. AMP 4 AMP 5 A/D D/A CONV. AMP 6 AMP 7 A/D CONV. Vref. AMP 8 AMP 10 DC OUT AMP 9 FILTER OUT AC DC OUT AC OUT KEY SW Start

More information

Acrobat Distiller, Job 2

Acrobat Distiller, Job 2 2 3 4 5 Eg φm s M f 2 qv ( q qφ ) = qφ qχ + + qφ 0 0 = 6 p p ( Ei E f ) kt = n e i Q SC = qn W A n p ( E f Ei ) kt = n e i 7 8 2 d φ( x) qn = A 2 dx ε ε 0 s φ qn s 2ε ε A ( x) = ( x W ) 2 0 E s A 2 EOX

More information

橡EN1165.PDF

橡EN1165.PDF G780(7ZMMP-KK F1C) BIOS Setup 1 G780(7ZMMP-KK F1C) 2 G780(7ZMMP-KK F1C) 3 G780(7ZMMP-KK F1C) 4 G780(7ZMMP-KK F1C) 1st Boot Device 2nd Boot Device 3rd Boot Device S.M.A.R.T. for Hard Disks BootUp Num-Lock

More information

AN5637

AN5637 IC SECAM IC SECAM IC 1 SECAM Unit : mm 19.2±0.3 16 9 1 8 (0.71) 0.5±0.1 Seating plane 2.54 1.22±0.25 DIP016-P-0300D 6.2±0.3 5.20±0.25 1.10±0.25 3.05±0.25 7.62±0.25 3 to 15 0.30 +0.10 ) (DIP016- P-0300M)

More information

eto-vol1.dvi

eto-vol1.dvi ( 1) 1 ( [1] ) [] ( ) (AC) [3] [4, 5, 6] 3 (i) AC (ii) (iii) 3 AC [3, 7] [4, 5, 6] 1.1 ( e; e>0) Ze r v [ 1(a)] v [ 1(a )] B = μ 0 4π Zer v r 3 = μ 0 4π 1 Ze l m r 3, μ 0 l = mr v ( l s ) s μ s = μ B s

More information

LMC6022 Low Power CMOS Dual Operational Amplifier (jp)

LMC6022 Low Power CMOS Dual Operational Amplifier (jp) Low Power CMOS Dual Operational Amplifier Literature Number: JAJS754 CMOS CMOS (100k 5k ) 0.5mW CMOS CMOS LMC6024 100k 5k 120dB 2.5 V/ 40fA Low Power CMOS Dual Operational Amplifier 19910530 33020 23900

More information

4 Mindlin -Reissner 4 δ T T T εσdω= δ ubdω+ δ utd Γ Ω Ω Γ T εσ (1.1) ε σ u b t 3 σ ε. u T T T = = = { σx σ y σ z τxy τ yz τzx} { εx εy εz γ xy γ yz γ

4 Mindlin -Reissner 4 δ T T T εσdω= δ ubdω+ δ utd Γ Ω Ω Γ T εσ (1.1) ε σ u b t 3 σ ε. u T T T = = = { σx σ y σ z τxy τ yz τzx} { εx εy εz γ xy γ yz γ Mindlin -Rissnr δ εσd δ ubd+ δ utd Γ Γ εσ (.) ε σ u b t σ ε. u { σ σ σ z τ τ z τz} { ε ε εz γ γ z γ z} { u u uz} { b b bz} b t { t t tz}. ε u u u u z u u u z u u z ε + + + (.) z z z (.) u u NU (.) N U

More information

U.C. Berkeley SPICE Simulation Program with Integrated Circuit Emphasis 1) SPICE SPICE netli

U.C. Berkeley SPICE Simulation Program with Integrated Circuit Emphasis 1) SPICE SPICE netli 1 -- 7 7 2008 12 7-1 7-2 c 2011 1/(12) 1 -- 7 -- 7 7--1 2008 12 1960 1970 1972 U.C. Berkeley SPICE Simulation Program with Integrated Circuit Emphasis 1) SPICE SPICE 7--1--1 7 1 7 1 1 netlist SPICE 2)

More information