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- かおり おおはし
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1
2
3 :
4 1. : : 3 : 4 : 2 2.
5 : : load: store: : : ( )
6
7 ( ) : 101 x
8 ( ): : 32 ( ) 32 ( ) : log 2 32
9 : : ( F) ( D) E W 1 4 :
10 F D E W F D E W F D E W F D E W F D E W F D E W F D E W
11 :
12 F D E W F D E W F D E W F D E W F D E W F D E W F D E W F D E W F D E W F D E W F D E W F D E W
13 Intel P Out-of-order execution /
14 : memory wall : : (load) DRAM CPU ( ) : Intel P4, C2D 64 bit, 1066 MHz (DRAM ) AMD K8 128 bit, 667 MHz CPU
15 : CPU CPU ( )
16 CPU CPU CPU
17 do i=1, a(i) = b(i) + c(i) enddo : 1970 (CDC 7600)
18 : 30 CDC 6600 load-store (CDC) IBM 360/85 OOO CDC 6600 ( )
19 ( ) : : do i=1, a(i) = b(i) + c(i) enddo
20 64 8 =
21 : : 8086 : 10 4 P4 : 10 8 :
22 : Cray-1 (1976) CDC Cyber 205, CPU+ Cray-2, Cray-(X/Y)MP
23 CPU ( ) : : CPU?
24 ( ) : 1 CPU + ( ) =
25 QCD (Caltech Hypercube) - PACS/PAX ILLIAC IV ( )
26 CPU CPU CPU CPU ILLIAC IV : SIMD ( CPU ) MIMD ( ) : Massively-Parallel Highly-Parallel
27 1970 : 1980 : / SIMD/MIMD / /AllCache/...
28 1990 : (2) NEC Cray T3x Alpha Beowulf Intel x :??? Beowulf SMP?
29
30 : 2002 : < 10 4 LSI: MHz Intel Pentium 4:??? : 1 : 2GHz 10
31 : : message-passing :
32 Beowulf : OS, : Linux, gcc, MPICH
33 Early Beowulfs
34 Beowulf ( ) > 100µs 3 GbE 100MB/s
35
36 FMM
37 :
38 2
39 The copy algorithm P0 0,1 2,3 4,5 6,7 P1 0,1 2,3 4,5 6,7 P2 0,1 2,3 4,5 6,7 P3 0,1 2,3 4,5 6,7 Step 0 P0 0,1 2,3 4,5 6,7 P1 0,1 2,3 4,5 6,7 P2 0,1 2,3 4,5 6,7 P3 0,1 2,3 4,5 6,7 Step 1
40 The ring algorithm P0 0,1 P1 2,3 P2 4,5 P3 6,7 Stage 0 P0 0,1 P1 2,3 P2 4,5 P3 6,7 Stage 1 6,7 0,1 2,3 4,5 P0 0,1 P1 2,3 P2 4,5 P3 6,7 Stage 2 4,5 6,7 0,1 2,3
41 N p T ring = C f N 2 /p + C c N + C s p. (1) C f C c C s 1 p O(N)
42 1
43 2 1-D decomposition 2-D decomposition 1 1 2
44 i j 1 2
45 2 i j
46 q q q q 10 q 11 q 12 q 20 q 21 q 22 2D
47 Step 1 Step 2 q 00 q 01 q 02 q 00 q 01 q 02 0,1,2 3,4,5 6,7,8 0,1,2 0,1,2 0,1,2 0,1,2 3,4,5 6,7,8 0,1,2 0,1,2 0,1,2 q 10 q 11 q 12 q 10 q 11 q 12 0,1,2 3,4,5 6,7,8 3,4,5 3,4,5 3,4,5 0,1,2 3,4,5 6,7,8 3,4,5 3,4,5 3,4,5 q 20 q 21 q 22 q 20 q 21 q 22 0,1,2 3,4,5 6,7,8 6,7,8 6,7,8 6,7,8 0,1,2 3,4,5 6,7,8 6,7,8 6,7,8 6,7,8
48 r 2 T 2Dbcast = C f N 2 /r 2 + 2(C c N/r + C s log 2 r). (2) (N/r) 2 N/r r N N 2
49 50 % p half,2dbcast (NC f /2C c ) 2 (3) ( )
50 p half,ind,2d N 5/3 C f /[C s log 2 (N 5/3 C f /2C s )] (4) N 2 1
51 N 2 Barnes and Hillis (1987?) Hyper-systolic algorithm (Lippert et al. 1998) 1 + non-unit-stride communication
52 FMM N Salmon & Warren
53 2 Caltech Hypercube Salmon Warren Orthogonal Recursive Bysection (ORB) Hashed Oct Tree (HOT)
54 ORB x y 3 z 2 x
55 ORB ORB Dubinski ORB
56 (local essential tree, LET)
57 Dubinski ORB
58 ORB tree ORB tree local tree LET
59
60 HOT N 1
61 HOT Morton Ordering
62 HOT LET
63 HOT and/or
64 ORB HOT ORB ) 2 n HOT
65 ORB , 4, 8 ORB
66 ORB ORB Dubinski ORB
67 Brackston & Suel 0 0
68 (local essential tree, LET)
69 LET LET Barnes
70
71
72 10 ( ) ( )?
73 :?
74
75 :
76 N N =
77 = = (???) (?) =
78 1 =
79 PS2, SH4 : 3D Intel SSE, AMD 3DNow!, Motorola AltiVec: SIMD VLIW
80 GRAPE Host Computer GRAPE Time integration etc. Interaction calculation : :
81
82 (Fortran, C, C++...)
83 1988 GRAPE
84 GRAPE 1 1 GRAPE 2 (i ) (j )
85 i j Pipe 0 (i0) Memory (j0) Pipe 0 (i) Memory Pipe 1 (i1) Memory (j1) Pipe 1 (i) j Pipe 2 (i2) Memory (j2) Pipe 2 (i) Pipe 3 (i3) Memory (j3) Pipe 3 (i) i-parallel j-parallel
86 i j i GRAPE-4: i j GRAPE-6: i j
87 GRAPE 1989 GRAPE-1 EPROM 1990 GRAPE-2 LSI 1991 GRAPE-3 LSI 1995 GRAPE-4 LSI 1998 GRAPE GRAPE-6
88
89 GRAPE-1
90 GRAPE-2
91 GRAPE-3
92 GRAPE-4
93 GRAPE-4 TURBOchannel Host Interface Host Interface Host Host Interface Host Interface Control Board Control Board Control Board Control Board Processor Board Processor Board Processor Board Processor Board Processor Board Processor Board Processor Board Processor Board Processor Board
94 GRAPE-4 Xi Xi sqrt Pcut Fcut Xi Xi m/r FiFiPi m j Xi Xi r 2 Xi Xi Func. eval. Xi Xi Xi Xi Xi Xi Xi Xi m/r 3 Xi Xi Xi FiFiFi Xj Xi Xi Vi Xi Xi r. v m/r 5 Xi Xi Vj Xi Xi Xi Xi FiFiJi Xi Xi Xi Xi
95 GRAPE-4 Control Logic HARP LSI #0 Particle Data Memory PROMETHEUS LSI HARP LSI #15 HARP LSI #16 LSI HARP LSI #31 HARP LSI #32 HARP LSI #47
96 GRAPE-6
97 パイプライン LSI 0.25 µm ルール (東芝 TC-240, 1.8M ゲート) 90 MHz 動作 6 パイプラインを集積 チップあたり 31 Gflops
98 RST CLK BCLK MEMA 21 MEMD IPD IPWE JPD 36 JPWE CALC UNIT PDATA 36 VD PREDICTOR PIPELINE UNIT LSI IPW UNIT JPW UNIT VMPSYNC 352 XP,VP,M,I ADDRESS, DATA, WEs To other units MEMA MEMD MEMOE MEMWE RUN INTERACTION INTERACTION PIPELINE INTERACTION PIPELINE UNIT INTERACTION PIPELINE UNIT INTERACTION PIPELINE UNIT INTERACTION PIPELINE UNIT PIPELINE UNIT UNIT NEIGHBOR LIST NEIGHBOR UNIT LIST NEIGHBOR UNIT LIST UNIT FO UNIT 36 STS VD ND FODATA WD GRAPE-4 IF IF
99 GRAPE-6 processor module
100 GRAPE-6 processor module G6 Chip SSRAM SSRAM 36 Reduction Unit (FPGA) G6 Chip G6 Chip SSRAM SSRAM SSRAM SSRAM G6 Chip SSRAM SSRAM
101 GRAPE-6 Processor board 3.3V 2.5V sum unit proc module proc module output port input port LVDS Tx LVDS Rx sum unit sum unit proc module proc module 1 32 sum unit proc module proc module (LVDS) sum unit proc module proc module (350MHz 4 wires) clock,
102 GRAPE-6 processor board
103 GRAPE-6 network board
104 GRAPE-6 host interface board
105 The full 64 Tflops GRAPE-6 system PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB 4-host, 16-board block with dedicated network H H H H H H Gigabit Ethernet Switch H H 4 (currently 3) blocks connected H H H H H H H H through GbE network PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB Combination of host network solution and PB PB PB PB PB PB PB PB dedicated network PB PB PB PB PB PB PB PB solution.
106 The 48-Tflops GRAPE-6 system Present 48-Tflops system. Three blocks with 16 host computers. The fourth block will be operational by the end of this month.
107 The host PC Cluster
108 13 GRAPE GRAPE
109 GRAPE OS
110 1
111 Case Study GRAPE-6 GRAPE-4
112 >>
113 GRAPE GRAPE
114 2
115 2 10µs 1ms 1 70A 140A
116
117
118 Case Study
119 2 DMDP (Delft) FASTRUN GRAPE MD-Engine MDM Digital Orrery Transputer-based projects... HaMM
120 (1) (2)
121
122 : Beowulf DSP (QCDSP) Dreamcast, PS2???
123 : : 3-5 1/
124 OK 10 7
125 GRAPE on-chip multiprocessor
126 GRAPE GRAPE
127 FPGA FPGA
128 GRAPE: 5 10
129 GRAPE 5-10 GRAPE
GRAPE-DR /
GRAPE-DR / GRAPE GRAPE-DR GRAPE ( ): (Barnes-Hut tree, FMM, Particle- Mesh Ewald(PPPM)...): ( ) 1988 32 IC 200 0.1m 3 400 GRAPE-1(1989) 16 8 32 48 240Mflops GRAPE-2(1990) 8 ( ) 40Mflops GRAPE-3(1991) 24
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