Agenda GRAPE-MPの紹介と性能評価 GRAPE-MPの概要 OpenCLによる四倍精度演算 (preliminary) 4倍精度演算用SIM 加速ボード 6 processor elem with 128 bit logic Peak: 1.2Gflops
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2 Agenda GRAPE-MPの紹介と性能評価 GRAPE-MPの概要 OpenCLによる四倍精度演算 (preliminary) 4倍精度演算用SIM 加速ボード 6 processor elem with 128 bit logic Peak: 1.2Gflops
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5 ボードの概要 Control processor (FPGA by Altera) GRAPE-MP chip[nextreme NX2500] (structured ASIC by easic)
6 GRAPE-MP チップのブロック図 転送 :800MB/s 128bit, 128 words 2 演算 x 100MHz x 6 PE = 1.2 Gflops 4 論理 pipelines x 6 PE = 24 pipelines /chip
7 inst BM out BM in GRF1 128w GRF2 128w add treg 4w mul tt ss rsq
8 ( 0 ) : nop if 0 ( 1 ) : sub? ( 2-8) : grf_a adr 7 bit ( 9-15) : grf_b adr 7 bit (16-22) : grf_c adr 7 bit (23-29) : grf_d adr 7 bit (30-31) : TREG adr 2 bit (32-34) : ADD 1st arg : a,b,bm,t,ti (35-37) : ADD 2nd arg : a,b,bm,t,ti (38-40) : MUL 1st arg : a,b,bm,t,ti (41-43) : MUL 2nd arg : a,b,bm,t,ti (44 ) : RSQ 1st arg : t,ti (45-46) : grf_c write : add, mul, rsq (47-48) : grf_d write : add, mul, rsq (49-50) : treg write : add, mul, rsq (51 ) : bm out (52-55) : bm mask : 1000 => 0, 1001 => 1, 1010 => 2 etc. (56-62) : bm adr 7 bit (128 words)
9 bit exponents 116bit mantissa 1bit for sign
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14 GRAPE-MP ボードのブロック図 64bit 16k ワード IO control processor をGRAPE-MP チップから分離 MP チップのPE 数を最大にするため 開発を簡単にするため
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16 sub bm16v ra0v rb40v sub bm20v ra4v rb44v sub bm24v ra8v rb48v mul rb40v rb40v ra36v mul rb44v rb44v tt add ra36v ts ra32v mul rb48v rb48v tt add ra32v ts tt b f b f a b b f a a a a e e a e c e240c0005e d e e e e240c e e
17 VARI xi, yi, zi, e2; VARJ xj, yj, zj, mj; VARF ax, ay, az, pt; dx = xj - xi; dy = yj - yi; dz = zj - zi; r1i = rsqrt(dx**2 + dy**2 + dz**2 + e2); pf = mj*r1i; pt += pf; af = pf*r1i**2; ax += af*dx; bm_in bm12v ra12v pe0 bm_in bm8v ra8v pe0 bm_in bm4v ra4v pe0 bm_in bm0v ra0v pe0 mov zz ra16v mov zz ra28v mov zz ra24v mov zz ra20v sub bm16v ra0v rb40v sub bm20v ra4v rb44v sub bm24v ra8v rb48v mul rb40v rb40v ra36v mul rb44v rb44v tt add ra36v ts ra32v mul rb48v rb48v tt add ra32v ts tt
18 GRAPE-MPの性能評価 テスト環境 CPU:Intel Core i7 920 (OC 3GHz) MEM: DDR GB (1208MHz動作) MB: Asus P6T6 WS Revolution (6PCIe スロット) 6ボードを搭載して性能評価
19 ファインマンループ積分 1 I = 0 1 x dx 0 1 x y dy 0 dz 1 D 2 D= xys tz 1 x y z x y 2 1 x y z 1 x y m e 2 z 1 x y m f 2 x,yを与える 一番内側のzの和を計算 同時に (x,y) の24 組を計算 積分のポイント数 Nを変えて計算 41 N 3 演算
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21 i 並列 146 pipelines(6 台 ) 96 pipelines(4 台 ) 48 pipelines(2 台 ) 性能 (N=3900) Gflops (5.30 倍 ) Gflops (3.75 倍 ) Gflops (1.95) Number of particles/points
22 ( i Number of particles 42 %
23 M A RAM-A (RA[1]) M B RAM-B (RB[1]) Multiplier[1] (64 64)... M A RAM-A (RA[p]) M B RAM-B (RB[p]) Multiplier[p] (64 64) Op 1024 bits 2048 bits MPFR Our Speedup MPFR Our Speedup x ± y x y x/y x Sin(x) Cos(x) Exp(x) Ln(x) Accumulator[1] 70bits(high) E A + E B MUX + Sum 64bits(low) RAM-C (RC) Normalization Result Accumulator[p] S A * S B (B) Structure of VP_Mult unit
24 POWER7 FPGA 400 Mop/s e e+08 1e+07 vector length 7 8 FPGA
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26 100 Performance of C AB + C on CPU-GPU Systems 2000 Performa in Differe 600 Performance [GFlop/s] Performance [GFlop/s] Matrix size [n=m=k] SGEMM on System A (HD 5870 GPU + Core i7 970 CPU) SGEMM on System B (HD 6970 GPU + Core i7 2600k CPU) DGEMM on System C (2 HD 5870 GPUs + Core i7 960 CPU) DGEMM on System A (HD 5870 GPU + Core i7 970 CPU) DGEMM on System B (HD 6970 GPU + Core i7 2600k CPU) 0
27 Blocking factor [b] (n=m=k=10b) Maximum Performance DGEMM SGEMM Variant System A System B Perf. [GFlop/s] Perf. [GFlop/s] C A T B + C C AB + C C A T B T + C C AB T + C C A T B + C C AB + C C A T B T + C C AB T + C
( ) ( ) HPC SPH FPGA Web http://galaxy.u-aizu.ac.jp/trac/note/ : 1 4 : 2 6 : 3 6 GPU : ~ 100 1000 : ~ 1000-100000 Google : ~ 10000 : ~ 100000000 GPU, Cell, FPGA GRAPE-DR/GRAPE-MP ( ) GPU GPU : Matsumoto,
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![4 倍精度基本線形代数ルーチン群 QPBLAS の紹介 [index] 1. Introduction 2. Double-double algorithm 3. QPBLAS 4. QPBLAS-GPU 5. Summary 佐々成正 1, 山田進 1, 町田昌彦 1, 今村俊幸 2, 奥田洋司](/thumbs/97/131936032.jpg "4 倍精度基本線形代数ルーチン群 QPBLAS の紹介 [index] 1. Introduction 2. Double-double algorithm 3. QPBLAS 4. QPBLAS-GPU 5. Summary 佐々成正 1, 山田進 1, 町田昌彦 1, 今村俊幸 2, 奥田洋司")
4 倍精度基本線形代数ルーチン群 QPBLAS の紹介 [index] 1. Introduction 2. Double-double algorithm 3. QPBLAS 4. QPBLAS-GPU 5. Summary 佐々成正 1, 山田進 1, 町田昌彦 1, 今村俊幸 2, 奥田洋司 3 1 1 日本原子力研究開発機構システム計算科学センター 2 理科学研究所計算科学研究機構 3 東京大学新領域創成科学研究科
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1 28 6 12 7 1 7.1...................................... 2 7.1.1............................... 2 7.1.2........................... 2 7.2...................................... 3 7.3...................................
スライド 1
GPU クラスタによる格子 QCD 計算 広大理尾崎裕介 石川健一 1.1 Introduction Graphic Processing Units 1 チップに数百個の演算器 多数の演算器による並列計算 ~TFLOPS ( 単精度 ) CPU 数十 GFLOPS バンド幅 ~100GB/s コストパフォーマンス ~$400 GPU の開発環境 NVIDIA CUDA http://www.nvidia.co.jp/object/cuda_home_new_jp.html
「FPGAを用いたプロセッサ検証システムの製作」
FPGA 2210010149-5 2005 2 21 RISC Verilog-HDL FPGA (celoxica RC100 ) LSI LSI HDL CAD HDL 3 HDL FPGA MPU i 1. 1 2. 3 2.1 HDL FPGA 3 2.2 5 2.3 6 2.3.1 FPGA 6 2.3.2 Flash Memory 6 2.3.3 Flash Memory 7 2.3.4
fx-3650P_fx-3950P_J
SA1109-E J fx-3650p fx-3950p http://edu.casio.jp RCA500002-001V04 AB2 Mode
HP Workstation 総合カタログ
HP Workstation E5 v2 Z Z SFF E5 v2 2 HP Windows Z 3 Performance Innovation Reliability 3 HPZ HP HP Z820 Workstation P.11 HP Z620 Workstation & CPU P.12 HP Z420 Workstation P.13 17.3in WIDE HP ZBook 17
No2 4 y =sinx (5) y = p sin(2x +3) (6) y = 1 tan(3x 2) (7) y =cos 2 (4x +5) (8) y = cos x 1+sinx 5 (1) y =sinx cos x 6 f(x) = sin(sin x) f 0 (π) (2) y
No1 1 (1) 2 f(x) =1+x + x 2 + + x n, g(x) = 1 (n +1)xn + nx n+1 (1 x) 2 x 6= 1 f 0 (x) =g(x) y = f(x)g(x) y 0 = f 0 (x)g(x)+f(x)g 0 (x) 3 (1) y = x2 x +1 x (2) y = 1 g(x) y0 = g0 (x) {g(x)} 2 (2) y = µ
< 1 > (1) f 0 (a) =6a ; g 0 (a) =6a 2 (2) y = f(x) x = 1 f( 1) = 3 ( 1) 2 =3 ; f 0 ( 1) = 6 ( 1) = 6 ; ( 1; 3) 6 x =1 f(1) = 3 ; f 0 (1) = 6 ; (1; 3)
< 1 > (1) f 0 (a) =6a ; g 0 (a) =6a 2 (2) y = f(x) x = 1 f( 1) = 3 ( 1) 2 =3 ; f 0 ( 1) = 6 ( 1) = 6 ; ( 1; 3) 6 x =1 f(1) = 3 ; f 0 (1) = 6 ; (1; 3) 6 y = g(x) x = 1 g( 1) = 2 ( 1) 3 = 2 ; g 0 ( 1) =
RW1097-0A-001_V0.1_170106
INTRODUCTION RW1097 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1line/2line/3line/4line/5line/6lines x 12 (16 x 16 dot format) with the
(1.2) T D = 0 T = D = 30 kn 1.2 (1.4) 2F W = 0 F = W/2 = 300 kn/2 = 150 kn 1.3 (1.9) R = W 1 + W 2 = = 1100 N. (1.9) W 2 b W 1 a = 0
1 1 1.1 1.) T D = T = D = kn 1. 1.4) F W = F = W/ = kn/ = 15 kn 1. 1.9) R = W 1 + W = 6 + 5 = 11 N. 1.9) W b W 1 a = a = W /W 1 )b = 5/6) = 5 cm 1.4 AB AC P 1, P x, y x, y y x 1.4.) P sin 6 + P 1 sin 45
lll
lll HA8000/30W アーキテクチャー HA8000/30W A8,B8,C8 Intel Intel845 Pentium 4(2.60GHz/2.40GHz) celeron (2.0GHz) Intel Intel845 1way 2GB Pentium 4 Celeron CPU Host Bus 64bit Bus:400MHz:MAX 3.2GB/s PCI AGP (Intel845)
P33W・P28X カタログ
P33WP28X Windows 10 24 FC-PM IoT 24 Windows 10Windows 7 2 FC98-NXP33WP28X PC FC-PM P33WP28X PC ACC 1 1HDD1 1 2HDD2 1 AC 1 2 USB 3 USB3.0 USB 4 USB3.0 USB 5 USB3.0 USB 6 USB3.0 USB 7 USB3.0 USB 8 USB3.0
main.dvi
2 f(z) 0 f(z 0 ) lim z!z 0 z 0 z 0 z z 1z = z 0 z 0 1z z z 0 1z 21 22 2 2 (1642-1727) (1646-1716) (1777-1855) (1789-1857) (1826-1866) 18 19 2.1 2.1.1 12 z w w = f (z) (2.1) f(z) z w = f(z) z z 0 w w 0
sec13.dvi
13 13.1 O r F R = m d 2 r dt 2 m r m = F = m r M M d2 R dt 2 = m d 2 r dt 2 = F = F (13.1) F O L = r p = m r ṙ dl dt = m ṙ ṙ + m r r = r (m r ) = r F N. (13.2) N N = R F 13.2 O ˆn ω L O r u u = ω r 1 1:
II (10 4 ) 1. p (x, y) (a, b) ε(x, y; a, b) 0 f (x, y) f (a, b) A, B (6.5) y = b f (x, b) f (a, b) x a = A + ε(x, b; a, b) x a 2 x a 0 A = f x (
II (1 4 ) 1. p.13 1 (x, y) (a, b) ε(x, y; a, b) f (x, y) f (a, b) A, B (6.5) y = b f (x, b) f (a, b) x a = A + ε(x, b; a, b) x a x a A = f x (a, b) y x 3 3y 3 (x, y) (, ) f (x, y) = x + y (x, y) = (, )