IEEE1394 LSI SBP-2 IEEE1394LSI SBP2 IEEE1394-1995 PHY LINK LSI LSI DVD-ROM/RAM, CD-ROM, HDD IEEE1394 I/F IEEE1394-1995 S100/S200 PHY S400 : 1 SBP2 Page Table Async transmit FIFO : 48 quadlet Async receive FIFO : 48 quadlet Data transmit/receive FIFO : 4128 (1032 quadlet) 8 8 16 DMA SBP2 LINK PHY IEEE1394 1
IEEE1394 LSI LINKRESET PHYDATA[7 : 0] PCTL[1 : 0] LREQ PHYTEST[1 : 0] SYSCLK ARF Rxfilter PHY TEST LINK CORE ATF SYS_MODE[2 : 0] SYS_D[7 : 0] SYS_A[7 : 0] SYS_NWE SYS_NRE SYS_NCS SYS_WAIT SYS_ALE Txfilter MCU interface Register DTRF Engine PHY Timer DATA FIFO SYS_INT Interrupt control PC[2 : 0] CMC PHYRESET XO XI DIRECT FILTER CPS PD LPS R1 R0 CNA NTPB TPB NTPA TPA TPBIAS TESTM2 TESTM1 DMA interface SCANTEST MINTEST RAMTEST DMARQ NIORE NIOWR DD[15 : 0] 2
IEEE1394 LSI 3 88 89 90 91 92 93 94 95 96 56 57 58 59 60 61 62 63 64 TPA1 81 TPBIAS1 82 N.C. 83 AVSS 84 AVDD 85 PLLVSS 86 PHYVER 87 FILTER AVDD XO XI PLLVDD R0 R1 AVSS NSTANDBY NTPA1 80 TPB1 79 NTPB1 78 AVSS 77 N.C. 76 N.C. 75 N.C. 74 N.C. 73 AVSS 72 CNA 71 PC2 70 PC1 69 PC0 68 CMC 67 AVDD DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 VREFODC DD3 DD2 DD1 DD0 LDVDD VREFODC DD12 DD13 DD14 DD15 NIORD NIOWR DMARQ TESTIO VREFODC 66 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 17 18 19 20 21 22 23 24 25 26 27 AVSS LDVDD LINKNRST SCANTEST MINTEST 65 28 29 30 31 32 PHYDATA0 49 PHYDATA1 50 51 PHYDATA2 52 PHYDATA3 53 PDVDD 54 PHYDATA4 55 PHYDATA5 PHYDATA6 PHYDATA7 PDVDD SYSCLK PD CPS PDVDD 48 PCTL0 47 PCTL1 46 45 PHYNRST 44 LPS 43 LREQ 42 NISO 41 TESTM2 40 39 38 37 36 35 TESTM1 PDVDD PHYTEST1 PHYTEST0 TEST DIRECT SYS_D7 SYS_D6 SYS_D5 SYS_D4 VREFSYS SYS_D3 SYS_D2 SYS_D1 SYS_D0 SYS_INT LDVDD SYS_MODE2 SYS_MODE1 SYS_MODE0 SYS_NWE SYS_ALE VREFSYS SYS_A0 SYS_A1 SYS_A2 SYS_A3 SYS_A4 SYS_A5 SYS_A6 SYS_A7 VREFSYS SYS_NCS SYS_NRE 34 105 104 103 102 101 100 99 98 97 112 111 110 109 108 107 106 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 SYS_WAIT 33 128
IEEE1394 LSI Pin No. I/O (25 ) 99 SYS_INT O INT Active "L" SYS_A[7 : 0] *1 I SYS_D[7 : 0] *1 I/O 保守廃止 111 SYS_NWE I Write enable Active "L" 127 SYS_NRE I Read enable Active "L" 126 SYS_NCS I Active "L" 128 SYS_WAIT O Active "L" 110 SYS_ALE I ALE Fix "L" 112 SYS_MODE0 I I/F 0 Fix "H" 113 SYS_MODE1 I I/F 1 Fix "H" 114 SYS_MODE2 I I/F 2 Fix "L" VREFSYS 3 I Reference 3/5 V I/F ODC DMA (19 ) DD[15 : 0] I/O 24 NIORD I DMA_I/F Active "L" 23 NIOWR I DMA_I/F Active "L" 25 DMARQ O DMA Active "H" VREFODC 3 I Reference 3/5 V ODCI/F LINK TEST (4 ) 31 SCANTEN I Fix "L" 32 MINTEST I ASIC Fix "L" 35 TEST I TEST Fix "L" ) *1: 0 LSB 26 TESTIO I/O TEST Open LINK (3 ) 96 NSTANDBY I LINK (0 : Link stop, 1 : Link on) 33 DIRECT I LINK Isolation Fix "H" 30 LINKNRST I LINK Active "L" 保守予定品種 保守品種 廃品種を 4
IEEE1394 LSI ( ) Pin No. I/O PHY_LINK (13 ) PHYDATA I/O PHY LINK PHY PHY [7 : 0] ( LINK PHY Open ) PCTL[1 : 0] I/O PHY LINK PHY CTL ( LINK PHY CTL ) LREQ I/O PHY-LINK LREQ PHY LINK PHY Open PHY LINK ( ) 36 PHYTEST0 I PHY-LINK PHYTEST0 PHYTEST1 0 0 : PHY + LINK 37 PHYTEST1 0 1 : LINK PHY 1 0 : PHY LINK 1 1 : PHY 1394 (5 ) 82 TPBIAS1 O Port1 TPBIAS PHY 81 TPA1 I/O Port1 TPA Open 80 NTPA1 I/O Port1 NTPA 79 TPB1 I/O Port1 TPB 78 NTPB1 I/O Port1 NTPB LINK/ODC / (11 ) LVDD 3 I V DD (3 V)LINK 8 I GND PHY Power (18 ) AVDD 3 I V DD AVSS 5 I GND PDVDD 4 I V DD (3 V) 4 I GND PLLVDD I PLL V DD PHY PLLGND I PLL GND 5
IEEE1394 LSI ( ) Pin No. I/O ( PHY ) PHY (19 ) 61 SYSCLK I/O 49.152 MHz 93 R0 [5.9 kω( = ±2%)] 94 R1 [5.9 kω( = ±2%)] 43 LPS I LINK Power Status Fix "H" (IEEE1394-1995Std. 4.3.4.1 Self-ID Packet ) 63 PD I Power Down : "H" Fix "L" *2 64 CPS I Cable Power Status : [400 Ω( = ±10%)] Fix "H" 71 CNA O Cable Not Active : "H" 88 FILTER I/O PLL ( ) 44 PHYNRST I PHY Fix "H" 39 TESTM1 I PHY 1 Fix "H" 40 TESTM2 I PHY 2 Fix "H" 87 PHYVER O PHY ( ) 90 XI I 25 MHz 91 XO O 25 MHz 41 NISO I PHY Isolation Fix "H" (L Isolation ) 67 CMC I/O Configuration Manager Capable Link-on Fix "L" (IEEE1394-1995 Std. 4.3.4.1 Self-ID packet ) 68 PC0 I/O Power Class 69 PC1 I/O (IEEE1394-1995 Std. 4.3.4.1 Self-ID packet ) 70 PC2 I/O ) *2: PHY "H" 6
IEEE1394 LSI 1. V SS = 0 V V DD 0.3 +4.6 V 5 V V ref5 0.3 +5.7 V VI 0.3 V DD +0.3 V 5V VI5 0.3 +6.0 V VO 0.3 V DD +0.3 V VO5 0.3 6.0 V 5V 0.3 V ref5 +0.3 V (TYPE-HL4) IO ±12 ma (TYPE-HL8) IO ±24 ma (TYPE-HL16) IO ±48 ma PD 1.05 mw T opr 40 +70 C T stg 55 +150 C TYPE-HL4 : DD0 DD15, NIORD, NIOWR, DMARQ, TESTIO, SYS_INT, SYS_D0 SYS_D7, SYS_ALE, SYS_NWE, MODE0 MODE2, SYS_A0 SYS_A7, SYS_NCS, SYS_NRE, SYS_WAIT TYPE-HL8 : PHYVER, LREQ, SYSCLK, CMC, PC0, PC1, CNA TYPE-HL16 : PCTL0, PCTL1, PHYDATA0 PHYDATA7 ) 1. 2. V DD (LDVDD, PDVDD, AVDD, PLLVDD) V SS 7
IEEE1394 LSI ( ) 2. LDVDD 3.0 3.3 3.6 V PDVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V PLLVDD 3.0 3.3 3.6 V 5 V VREFODC 4.75 5.0 5.25 V VREFSYS 4.75 5.0 5.25 V T a 0 70 C t r 0 4 ns t f 0 4 ns f OSC1 24.576 MHz Xtal 24.576 MHz CXI V DD = 3.3 V 33 pf XI XO CXO 33 ) 1. 2. AVDD, PLLVDD CXO CXI 8
IEEE1394 LSI ( ) 3. DC V DD = 3.0 V 3.6 V, V SS = 0.00 V, ftest = 50 MHz, T a = 0 C 70 C LINK IDD0 134 ma VI5 = 5.0 V V SS PHY_Digital IDD1 f = 50 MHz 30 ma V DD = 3.3 V, PHY_Analog IDD2 V ref5 = 5.0 V 40 ma : XO Rf7 313 940 2820 kω V DD = 3.3 V CMOS : SCANTEST, DIRECT, TEST, PHYTEST0, PHYTEST1, TESTM0, TESTM1, NISO "H" VIH V DD 0.8 V DD V "L" VIL 0 V DD 0.2 V ILI 5 +5 µa CMOS : MINTEST "H" VIH V DD 0.8 V DD V "L" VIL 0 V DD 0.2 V RIL VI = V DD 10 30 90 kω ILIPD VI = V SS 10 +10 µa LVTTL : PD "H" VIH 2.0 V DD V "L" VIL 0 0.8 V ILI VI = V SS 5 +5 µa TLL 5V : LINKNRST, LPS, PHYNRST, NSTANBY "H" VIH 2.0 5.25 V "L" VIL 0 0.8 V ILI5 VI = V SS 10 +10 µa N-ch. : SYS_WAIT 保守廃止 保守予定品種 保守品種 廃品種を "L" VOL IOL = 4.0 ma 0.4 V IOZ5 VO5 = Hi-Z 10 +10 µa VO5 = 5.25 V V SS 9
IEEE1394 LSI ( ) 3. DC ( ) V DD = 3.0 V 3.6 V, V SS = 0.00 V, ftest = 50 MHz, T a = 0 C 70 C CMOS : SYSCLK "H" VIH V DD 0.8 V DD V "L" VIL 0 V DD 0.2 V "H" VOH IOH = 8.0 ma V DD 0.6 V "L" VOL IOL = 8.0 ma 0.4 V IOZ VO = Hi-Z 5 +5 µa VO = V DD V SS TTL : PHYVER, LREQ, CMC, PC0 PC2, CNA "H" VIH 2.0 V DD V "L" VIL 0 0.8 V "H" VOH IOH = 8.0 ma 2.4 V "L" VOL IOL = 8.0 ma 0.4 V IOZ VO = Hi-Z 5 +5 µa VO = V DD V SS TTL : PCTL0, PCTL1, PHYDATA0 PHYDATA7 "H" VIH 2.0 V DD V "L" VIL 0 0.8 V "H" VOH IOH = 16.0 ma 2.4 V "L" VOL IOL = 16.0 ma 0.4 V IOZ VO = Hi-Z 5 +5 µa VO = V DD V SS 10
IEEE1394 LSI ( ) 3. DC ( ) V DD = 3.0 V 3.6 V, V SS = 0.00 V, ftest = 50 MHz, T a = 0 C 70 C TTL 5V LVCMOS : DD0 DD15, NIORD, NIOWR, DMARQ, DMAACK, SYS_INT, SYS_D0 SYS_ D7, SYS_ALE, SYS_NWE, MODE0 MODE2, SYS_A0 SYS_A7, SYS_NCS, SYS_NRE "H" VIH 2.0 V ref5 V "L" VIL 0 0.8 V "H" VOH IOH = 4.0 ma 2.4 V "L" VOL IOL = 4.0 ma 0.4 V IOZ5 VO5 = Hi-Z 10 +10 µa VO5 = 5.25V V SS PHY VID 100 (S100) 142 260 mv VID 200 (S200) 132 260 mv VID ARB 171 262 mv ( ) TPBIAS VCMA 1.665 2.015 V VDO 172 265 mv TPBIAS ICMA 4.84 ma ISS 200 S200 2.52 4.84 ma ISS 200 S200 1.62 5.06 ma VIH+ "1" 89 168 mv ( ) VIL "0" 168 89 mv ( ) 4. AC SYSCLK tcyc 49.152 MHz dclk 50 % 11
IEEE1394 LSI ( ) 4. AC ( ) tcyc thi Vclk/2 Vclk DMARQ tsu thd VDD/2 tod dclk = thi/tcyc 100 VDD/2 1. DMA 1)READ ( : SBP2 ODC) DMARQ negate time t rdrq 25 ns DMARQ assert time t rdrd 0 ns NIORD "L" level pulsed width t wrd 29 ns Data output defined time t vdd 20 ns Data output hold time t hddd 10 ns t rdrd t rdrq NIORD t wrd t hddd DD[15 : 0] t vdd Valid data Valid data Valid data 12
IEEE1394 LSI ( ) 1. DMA ( ) 1)READ ( : SBP2 ODC)( ) LSI wait DMARQ t = 0 s t DMARQ NIORD 2)Write ( : ODC SBP2) DMARQ negate time t wrrq 25 ns DMARQ assert time t wrrd 0 ns NIOWR "L" level pulsed width t wwd 29 ns Input data set up time t sudd 10 ns Input data hold time t hddd 10 ns DMARQ NIOWD DD[15 : 0] t wrrd t wwd t sudd t hddd t wrrq Data Data Data LSI wait DMARQ t = 0 s t DMARQ NIOWD 13
IEEE1394 LSI ( ) 1. DMA ( ) 3)Data register access cycle time Data register access cycle time (NIORD) t dcy_rd 58 ns : 64 Kbyte 91 ns : 64 Kbyte Data register access cycle time (NIOWR) t dcy_wr 58 ns Fall time (NIORD/NIOWR) t d 10 ns NIORD/NIOWR 4)DMA NIORD : Rx : DD[15 : 0] OUTPUT : t dcy OUTPUT t d 14
IEEE1394 LSI ( ) 2. PHY SETUP(SYSYCLK PHYDATA[3 : 0]) T su1 6.0 ns SETUP(SYSYCLK PCTL[1 : 0]) T su2 6.0 ns HOLD(SYSYCLK PHYDATA[3 : 0]) T hd1 6.0 ns HOLD(SYSYCLK PCTL[1 : 0]) T hd2 6.0 ns SYSCLK PHYDATA[3 : 0] Valid Valid PCTL[1 : 0] SYSCLK Tsu1 Tsu2 Valid PHY input from LINK PHYDATA[3 : 0] Valid Valid PCTL[1 : 0] Thd1 Thd2 Valid PHY output to LINK Tc1 Valid Valid 15
IEEE1394 LSI 8 bit MCU (MN10200 ) SYS_MODE2 SYS_MODE1 SYS_MODE0 SYS_INT SYS_WAIT SYS_NCS SYS_A[7 : 0] SYS_D[7 : 0] SYS_NRD SYS_NWE MCU I/F Register DMA I/F DMARQ NIORD NIOWR DD[15 : 0] [7 : 0] [7 : 0] ODC DMARQ NIORD NIOWR DD[15 : 0] [17 : 0] NWR NRD CPUDT[7: 0] CPUADR[17 : 0] NCS NWAITODC NINT[1 : 0] NMRST CLKOUT1 SYSIF MINI0300CORE DMA controller 16
IEEE1394 LSI ( : mm) LQFP128-P-1818C 97 128 20.00±0.20 18.00±0.10 96 65 1 32 (1.25) 0.50 0.20±0.05 0.10 Seating plane 64 (1.25) 33 18.00±0.10 20.00±0.20 0.10 M 0.10±0.10 1.40±0.10 1.70max 0.15±0.05 (1.00) 0 to 10 0.50±0.20 17
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