Nios II ver. 7.1 2007 8 1. Nios II FPGA Nios II Quaruts II 7.1 Nios II 7.1 Nios II Cyclone II count_binary 2. 2-1. http://www.altera.com/literature/lit-nio2.jsp 2-2. Nios II Quartus II FEATURE Nios II IP Nios II Nios II FEATURE Nios II FPGA *_timelimited.sof Nios II Nios II Page 1 of 28 Altima Corporation
Nios II 2-3. Nios II FPGA PC USB-Blaster Rev B Nios II StratixII RoHS PC USB-Blaster J24 J26 Nios II Nios Development Board Reference Manual http://www.altera.com/literature/lit-nio2.jsp FPGAFPGA Stratix III Stratix II Stratix EP1S10 Cyclone III Cyclone II Cyclone EP1C12 3. Quartus II Quartus II Web Quartus II File Open Project ver. 7.1 2007 8 Page 2 of 28 Altima Corporation
Nios II Web Nios II Quartus II nios2_quartus2_project.qpf.bdf.bdf File Open nios2_quartus2_project.bdf Nios II ver. 7.1 2007 8 Page 3 of 28 Altima Corporation
Nios II 4. SOPC Builder Nios II SOPC Builder Nios II Nios II HDL SOPC Builder Nios II STEP1 SOPC Builder STEP2 STEP3 CPU STEP4 SOPC Builder generate STEP5.bdf ( ) Nios II 4-1. SOPC Builder Tools SOPC Builder II SOPC Builder System Name (first_nios2_system) SOPC Builder HDL Verilog VHDL OK ver. 7.1 2007 8 Page 4 of 28 Altima Corporation
Nios II 4-2. System Contents Nios II Nios II Cyclone II 50MHz 4-3. CPU CPU Nios II Nios II CPU JTAG UART ID LED I/O (PIO) System Contents ver. 7.1 2007 8 Page 5 of 28 Altima Corporation
Nios II 4-3-1. 1 20 KByte 1 Memories and Memory Controers On-Chip On-Chip Memory(RAM or ROM) Add On-Chip Memory Total Memory Size 20 Kbytes Stratix, Stratix II Stratix III Block Type: M4K Finish Stratix Stratix II Stratix III ver. 7.1 2007 8 Page 6 of 28 Altima Corporation
Nios II 4-3-2. Nios II CPU Nios II Processor Add Nios II Nios II/s Hardware Multiply None Hardware Divide Reset Vector Exception Vector onchip_mem Offset 0x0 0x20 Next Cache & Tightly Coupled memories ver. 7.1 2007 8 Page 7 of 28 Altima Corporation
Nios II Instruction Cache 2 Kbytes Include Tightly Coupled Instruction Master Port(s) Advanced Features JTAG Debug Module Custom Instruction Finish ver. 7.1 2007 8 Page 8 of 28 Altima Corporation
Nios II SOPC Builder Nios II 4-3-3. JTAG UART PC Nios II JTAG UART PC USB-Blaster Intertace Protocols Serial JTAG UART Add ver. 7.1 2007 8 Page 9 of 28 Altima Corporation
Nios II JTAG UART finish 4-3-4. HAL JTAG_UART Peripherals Microcontroller Peripherals Interval Timer Add ver. 7.1 2007 8 Page 10 of 28 Altima Corporation
Nios II Avalon Timer Finish SOPC Builder timer Rename sys_clk_timer ver. 7.1 2007 8 Page 11 of 28 Altima Corporation
Nios II 4-3-5. ID ID PC Peripherals Debug and Performance System ID Peripheral Add Sustem ID Peripheral Finish ver. 7.1 2007 8 Page 12 of 28 Altima Corporation
Nios II 4-3-6. LED I/O PIO Nios II 8 LED PIO Other PIO (Parallel I/O) Add Avalon PIO width 8 output ports only Finish ver. 7.1 2007 8 Page 13 of 28 Altima Corporation
Nios II PIO SOPC Builder PIO pio Rename led_pio 4-4. SOPC Builder generate 4-4-1. SOPC Builder Nios II 1 Auto-Assign Base Addresses ver. 7.1 2007 8 Page 14 of 28 Altima Corporation
Nios II tag_uart_0 IRQ 16 4-4-2. generate Nios II HDL System Generation Next Simulation. Create project simulator files. Generate ver. 7.1 2007 8 Page 15 of 28 Altima Corporation
Nios II Generate SYSTEM GENERATION COMPLETED Exit 4-5. BDF ( ) Nios II SOPC Builder first_nios2_system.bdf Quartus II.bdf Symbol Libraries Project first_nios2_system Symbol OK first_nios2_system ver. 7.1 2007 8 Page 16 of 28 Altima Corporation
Nios II Nios II.bdf File Save.bdf 5. Quartus II 5-1. Nios II 5 2 5-1-1. Assignments Device Family Device family selection has changed. Do you want to remove all location assignments? Y Target device Specific device selected in Available devices list ver. 7.1 2007 8 Page 17 of 28 Altima Corporation
Nios II Available devices N Setting OK 5-1-2. Assignments Assignment Editor Assignment Editor Category Pin To PLD_CLOCKINPUT[1] Location LED LEDG[0] LEDG[7] ver. 7.1 2007 8 Page 18 of 28 Altima Corporation
Nios II File Save ver. 7.1 2007 8 Page 19 of 28 Altima Corporation
Nios II 5-2. Quartus II Quartus II FPGA.sof Quartus II Processing Start Compilation Compilation Report 6..sof FPGA USB-Blaster Nios II JTAG 10 Quartus II Tools Programmer nios2_quartus2_project.sof Mode JTAG Hardware Setup Currently Selected hardware USB-Blaster Close ver. 7.1 2007 8 Page 20 of 28 Altima Corporation
Nios II Programmer Program/Configure Start Progress 100 *_time_limited.sof Cancel FPGA Nios II first_nios2_system nios2_quartus2_project 7. Nios II 7-1. Nios II IDE Nios II Nios II IDE Nios II Nios II IDE Windows Altera Nios II EDS 7.1 Nios II 7.1 IDE ver. 7.1 2007 8 Page 21 of 28 Altima Corporation
Nios II Workspace Nios II IDE File Switch Workspace Workspace Launcher Workspace OK ver. 7.1 2007 8 Page 22 of 28 Altima Corporation
Nios II Welcome to the Altera Nios II IDE Workbench File New Nios II C/C++ Application Select Target Hardware SOPC Builder System PTF File Browse first_nios2_system.ptf Select Target Hardware CPU cpu ver. 7.1 2007 8 Page 23 of 28 Altima Corporation
Nios II Select Project Template Count Binary Name count_binary_0 Finish Nios II IDE Nios II IDE count_binary_0 System Library Properties Properties for count_binary_0_syslib ver. 7.1 2007 8 Page 24 of 28 Altima Corporation
Nios II Clean exit (flush buffers) Small C library OK count_binary_0 Builde Project.elf ver. 7.1 2007 8 Page 25 of 28 Altima Corporation
Nios II 7-2. Count Binary count_binary_0 Run As Nios II Hardware Nios II IDE FPGA Nios II IDE LED ver. 7.1 2007 8 Page 26 of 28 Altima Corporation
Nios II Terminate ( ) Nios II Nios II IDE LED Nios II IDE Console ver. 7.1 2007 8 Page 27 of 28 Altima Corporation
Nios II 6. 1. 7. 2. 8. 3. 9. 4. 10. 5. ver. 7.1 2007 8 Page 28 of 28 Altima Corporation