VLD Kazutoshi Kobayashi

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1 VLD Kazutoshi Kobayashi

2 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d) ,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape file:///home/users11/kobayasi/refresh/index.html # / 3.,, View Encoding Japanese (Auto-Detect). 1

3 2 2

4 BCD 2,. % cd % mkdir binshifttop, binshifttop,. 5.1 binshiftreg module endmodule verilog/binshiftreg1.v module binshiftreg(out,decimal,clk,rst,ce); output [6:0] out; input [9:0] decimal; input CLK,RST,CE; // input, output endmodule assign function binshiftreg function dectobin d verilog/binshiftreg2.v module binshiftreg(out,decimal,clk,rst,ce); output [6:0] out; input [9:0] decimal; input CLK,RST,CE; wire [3:0] d; // 1 wire. assign d=dectobin(decimal); // function dectobin d function [3:0] dectobin; // [3:0] input [9:0] in; // function if(in[9]) // function if, case dectobin = 9; else if(in[8]) dectobin = 8; else if(in[7]) dectobin = 7; 3

5 // else if(in[0]) dectobin = 0; // else endfunction endmodule count REGA always binshiftreg 5.4 out assign. verilog/binshiftreg.v module binshiftreg(out,decimal,clk,rst,ce); output [6:0] out; input [9:0] decimal; input CLK,RST,CE; wire [3:0] d; reg [1:0] count; reg [6:0] REGA; assign d=dectobin(decimal); function [3:0] dectobin; input [9:0] in; if(in[9]) dectobin = 9; else if(in[8]) dectobin = 8; else if(in[7]) dectobin = 7; else if(in[6]) dectobin = 6; else if(in[5]) dectobin = 5; else if(in[4]) dectobin = 4; else if(in[3]) dectobin = 3; else if(in[2]) dectobin = 2; else if(in[1]) dectobin = 1; else if(in[0]) dectobin = 0; endfunction CLK or negedge RST) begin if(!rst) begin REGA<=0; count<=0; end else if((decimal!= 0) && (count < 2)) begin REGA<=(REGA*10)+d; 4

6 count<=count+1; end else if(ce) begin REGA<=0; count<=0; end end assign out=rega; endmodule (syncro) 2 BCD 7 LED (binled). verilog/other.v: syncro, ledout, bintobcd verilog module syncro(out,in,clk,rst); parameter WIDTH = 1; input [WIDTH-1:0] in; output [WIDTH-1:0] out; input CLK,RST; reg [ WIDTH-1:0] q0,q1,q2; CLK or negedge RST) begin if(!rst) q0<=0; else q0<= in; end CLK or negedge RST) begin if(!rst) q1<=0; else q1<=q0; end CLK or negedge RST) begin if(!rst) q2<=0; else q2<=q1; end assign out=q1&( q2); endmodule module binled(in,ledh,ledl); input [6:0] in; output [6:0] ledh,ledl; wire [3:0] outh,outl; bintobcd I0(.in(in),.outl(outl),.outh(outh)); ledout I1(.in(outl),.out(ledl)); ledout I2(.in(outh),.out(ledh)); endmodule 5

7 module bintobcd(in,outl,outh); input [6:0] in; output [3:0] outl,outh; wire [6:0] tmp1,tmp2,tmp3; assign outh[3] = (in>=80)? 1 : 0; assign tmp1 = (in>=80)? in-80 : in; assign outh[2] = (tmp1>=40)? 1 : 0; assign tmp2 = (tmp1>=40)? tmp1-40 : tmp1; assign outh[1] = (tmp2>=20)? 1 : 0; assign tmp3 = (tmp2>=20)? tmp2-20 : tmp2; assign outh[0] = (tmp3>=10)? 1 : 0; assign outl = (tmp3>=10)? tmp3-10 : tmp3; endmodule define SEG_OUT_0 7 b011_1111 define SEG_OUT_1 7 b000_0110 define SEG_OUT_2 7 b101_1011 define SEG_OUT_3 7 b100_1111 define SEG_OUT_4 7 b110_0110 define SEG_OUT_5 7 b110_1101 define SEG_OUT_6 7 b111_1101 define SEG_OUT_7 7 b010_0111 define SEG_OUT_8 7 b111_1111 define SEG_OUT_9 7 b110_1111 define SEG_OUT_ERR 7 b011_1001 module ledout(out,in); input [3:0] in; output [6:0] out; function [6:0] convert; input [3:0] in ; case (in) 0: convert = SEG_OUT_0; 1: convert = SEG_OUT_1; 2: convert = SEG_OUT_2; 3: convert = SEG_OUT_3; 4: convert = SEG_OUT_4; 5: convert = SEG_OUT_5; 6: convert = SEG_OUT_6; 7: convert = SEG_OUT_7; 8: convert = SEG_OUT_8; 9: convert = SEG_OUT_9; default: convert = SEG_OUT_ERR; // If the above line is omitted, A warning messsage is shown in Synplify Pro endcase endfunction assign out=convert(in); endmodule 5.6 binshifttop verilog/skel/binshifttop.v binshifttop verilog/binshifttop.v binshifttop verilog/binshiftsimgtk.v GTK 6

3.1: GUI 3.1.1,, X Window GUI., GUI, verilog PLI(Programming Language Interface) C. GUI, verilog. gtksim.sh Verilog. binshifttop, UNIX. % gtksim.sh binshiftsimgtk.v binshifttop.v binshiftreg.v other.

8 3.1: GUI 3.1.1,, X Window GUI., GUI, verilog PLI(Programming Language Interface) C. GUI, verilog. gtksim.sh Verilog. binshifttop, UNIX. % gtksim.sh binshiftsimgtk.v binshifttop.v binshiftreg.v other.v, GUI( 3.1). Q,,,., binshifttop 10 CE RST. 7 LED LED, overflow Quartus binshifttop 1. Quartus II. (*unresolved reference*??), *unresolved reference*??, Yes., No, File New Project Wizard. % cd /binshifttop % quartus 2. Project Wizard (*unresolved reference*??), Next. Project Wizard, File Project Wizard. 7

3.2: Select Family 3. Working Directory,./, What is the name of project, binshifttop, What is the name of top-level entry, binshifttop Next. 4. binshifttop.v, binshiftreg.v, other.v File Name, Finish.

9 3.2: Select Family 3. Working Directory,./, What is the name of project, binshifttop, What is the name of top-level entry, binshifttop Next. 4. binshifttop.v, binshiftreg.v, other.v File Name, Finish., Finish, Project Add/Remove Files in Project,. 5. Select Family, Cyclone. 6. binshifttop.tcl 1, binshifttop/. 7. Tools->Tcl Scripts, Project binshifttop.tcl, Run., FPGA. 8. (Start Compilation) enzan Verilog-HDL verilog/enzan part1.v module verilog/enzan part2.v + verilog/enzan part3.v = verilog/enzan part4.v out verilog/enzan.v enzan.v 5.8 enzantop verilog/skel/enzantop.v enzantop verilog/enzantop.v enzantop verilog/enzansimgtk.v GTK verilog/binshifttop.tcl 8

10 3.1: enzantop push[9:0] CE 23 RST 240 CLK 28 plus 5 equal 17 ledl[6:0] ledh[6:0] % gtksim.sh enzansimgtk.v enzantop.v enzan.v other.v verilog/inverse.v module inverse; reg [4:0] A,B,C;// 5 initial begin A=3;B=-2; $display("a=%d,%b, B=%d,%b",A,A,B,B); C=8-5; // 3 #100 C=5-8; // -3 #100 C=-10-8; // -18( ) #100 C=10+10; // 20( ) end initial $monitor("%d: ",$time,"c=%d, -%d, %b",c, C+5 b00001,c); // C+1, 32. endmodule verilog/inversesigned.v(signed ) module inverse; reg signed [4:0] A,B,C;// 5 initial begin A=3;B=-2; 9

11 $display("a=%d,%b, B=%d,%b",A,A,B,B); C=8-5; // 3 #100 C=5-8; // -3 #100 C=-10-8; // -18( ) #100 C=10+10; // 20( ) end initial $monitor("%d: ",$time,"c=%d, %b",c,c); // C endmodule verilog/skel/calc.v verilog/calc.v verilog/calcsigned.v (signed ) verilog/calctop.v (calctop.v) verilog/calcsimgtk.v GTK : calctop push[9:0] CE 23 RST 240 CLK 28 plus 5 minus 12 equal 17 ledl[6:0] ledh[6:0] ledsign[6:0] overflow % gtksim.sh calcsimgtk.v calctop.v calcsigned.v other.v 10

12 4 FPGA 4.1, Power Medusa MU200-EC6S.. FPGA, Altera Cyclone. Cyclone FPGA,., SUN,,, USB,. 4.2, LED( ) 4.1, 4.2.,, 4.2, LED 7 LED FPGA. 1 LED. LED FPGA., 4.3., SW26(1 ) , 0. 11

13 4.1: ( 1) 28 CLK 7 A 7 E 240 RST 133 A0 87 E0 134 A1 88 E1 2 A0 135 A2 93 E2 3 A1 136 A3 94 E3 4 A2 137 A4 95 E4 5 A3 138 A5 98 E5 6 A4 139 A6 99 E6 7 B0 140 A7 100 E7 8 B1 7 B 7 F 11 B2 123 B0 77 F0 12 B3 124 B1 78 F1 13 B4 125 B2 79 F2 14 C0 126 B3 82 F3 15 C1 127 B4 83 F4 16 C2 128 B5 84 F5 17 C3 131 B6 85 F6 18 C4 132 B7 86 F7 12

14 4.2: ( 2) 7 C 7 G 19 D0 115 C0 65 G0 20 D1 116 C1 66 G1 21 D2 117 C2 67 G2 23 D3 118 C3 68 G3 41 D4 119 C4 73 G4 LED 120 C5 74 G5 47 LED C6 75 G6 48 LED C7 76 G7 49 LED-2 7 D 7 H 50 LED D0 57 H0 53 LED D1 58 H1 54 LED D2 59 H2 55 LED D3 60 H3 56 LED D4 61 H4 108 D5 62 H5 113 D6 63 H6 114 D7 64 H7 4.3: MHz 20MHz 10MHz 5MHz 1.25MHz 3125kHz 78.1kHz 19.5kHz 8 9 A B C D E F 9.8kHz 4.9kHz 2.44kHz 1.22kHz 610Hz 305Hz 1.0Hz 13

15 7 LED A B C D E F G H ABC ON EP1C6Q240C8 SW SW FPGA LED RST 4.1: FPGA 0 ( ) 4.2: (.) 14

16 A7 A2 A3 A1 A6 A5 A4 A0 4.3: 7 LED A0 A1 A2 A3 A B0 B1 B2 B3 B = C0 C1 C2 C3 C FPGA 0 CE D0 D1 D2 D3 D : 15

17 5 5.1,, GUI PLI,.,.,, PLI, kobayasi/refresh. 5.2 Verilog, signed,. Verilg-XL, NC-verilog Cadence : Solaris, HP-UX, Windows VCS Synopsys : Solaris, HP-UX, Windows, Linux modelsim Mentor Graphics : Solaris, HP-UX, Windows, Linux GPL Cver Antrim Design Systems PLI,,., GPL Cver, GPL Verilog Simulator. Verilog 2001,.,, Windows Cygwin GPL Cver, PLI., Solaris, Linux Verilog-XL PLI. 5.3 Cver on Cygwin Cygwin 1. cygwin. Install or update now!. 2. Select Packages, Devel, gcc make Skip, Install

18 5.3.2 GPL Cver 1. GPL Cver 1,gplcver-2.11a.src.tar.bz cygwin. $ tar xfj gplcver-2.11a.src.tar.bz2 3. gplcver-2.11a.src/src, make. $ cd gplcver-2.11a.src/src $ make -f makefile.cygwin 4. objs, PLI cver. $ cd../objs $ make -f makefile.dll dll exe 5., makefile,. 3 $ cd../tests_and_examples/examples.vpi/ # makefile.cygwin, $ make -f makefile.cygwin dll run #. tmp_channel GTK, Cygwin GTK. 1. 4, Gtk+ Win32 Development Environment., C:\cygwin\GTK. 2., Makefile 5, helloworld.c cver/makefile.cygwin cver/makefile.tex 6 cver/helloworld.c 17

19 3. cygwin make # Makefile, helloworld.c $ make $./helloworld.exe # windows, hello world PLI 1. gtkcalc cver.tgz 7 2. gplcver-2.11a.src.tar.bz #, gplcver-2.11a.src.tar.bz2 $ tar xfz gtkcalc_cver.tgz 4., $ cd gtkcalc $./gtksim.sh 5., $ make clean $ make dll $./gtksim.sh 5.4 Verilog-XL on Solaris GTK+.gtkcalc/gtklib.tgz,.,, 7 cver/gtkcalc cver.tgz 18

20 5.4.2 gtkcalc/solaris/libvpi.so gtkcalc/solaris/gtksim.sh, CALCLIB= GTKLIB= CALCLIB=, libvpi.so, GTKLIB= GTK. gtksim.sh, chmod +x gtksim.sh. 5.5 Verilog-XL on Linux Linux,, GTK+,, GTK+., libvpi.so, gtkcalc/linux/libvpi.so gtkcalc/linux/gtksim.sh, CALCLIB= CALCLIB=, libvpi.so. gtksim.sh, chmod +x gtksim.sh. 5.6 PLI PLI gtkcalc/gtkcalc.tgz. 19

21 6 6.1 FPGA, Quartus II. MU200-EC6S Cyclone, Quartus II Web Edition, Verilog HDL., GPL Cver, FPGA, MU200-EC6S,,. 6.2 FPGA. /, KITE, FPGA., Power Medusa MU200-AP, Verilog-HDL 3., SFL, FPGA,., Celoxica DK-II, C FPGA. 20

, FPGA Verilog-HDL

, FPGA Verilog-HDL Kazutoshi Kobayashi (kobayasi@kuee.kyoto-u.ac.jp) 2007 12 19-20 1 1 1.1...................................... 1 1.2,................................. 1 2 2 2.1 FPGA......................... 2 2.2 Verilog-HDL.............................