Cache Cache Cache cache cache 17.10.2007 1
17.10.2007 2
Cache Register:FF circuits Cache:Bipolar,CMOS SRAM Main Storage:SRAM,DRAM Disk Cache:DRAM 17.10.2007 3
SRAM Cell Structure (1 bit) 17.10.2007 4
temporal locality spatial locality 17.10.2007 5
Cache Cache 17.10.2007 6
Cache Cache tag Cache tag 17.10.2007 7
10bit addr 16/ 64Byte 16 cache 16 validity bit invalid bit cache tag 10bit address sector addr. tag data 17.10.2007 8
17.10.2007 9
row. row Column Tag row cache column tag Tag 10bit column 1 row 1 cache row 17.10.2007 10
cache 64Byte cache tag 17.10.2007 11
(n-way) cache 1 row 1 way 2-way,row addr. 6 bit, column addr. 8 bit, 64Byte 17.10.2007 12
16-way 17.10.2007 13
Cache Cache Capacity way row set replacement restore - Compulsory Conflict 17.10.2007 14
cache capacity miss conflict miss way conflict miss rate cache miss rate 1-way miss rate 2-way cache 1/2 cache miss rate 1/1.4 17.10.2007 15
cache invalid bit LRU Least Recently Used tag bit FIFO First-In First-Out LRU cache 17.10.2007 16
Store-Through or Write-Through Store-In,Write-Back or Copy-Back 17.10.2007 17
Store Write -Through cache cache Write cache cache cache Write Buffer CPU 17.10.2007 18
Store In or Write Copy -Back cache cache cache cache clean bit OFF irty cache clean bit ON lean 17.10.2007 19
17.10.2007 20
cache L1 L2 Victim 17.10.2007 21
cache 1 cache cache 17.10.2007 22
cache 2 17.10.2007 23