DA DA シンポジウム 25 27 DAS25 Design Automation Symposium 25/8/26 28nm UTBB FDSOI SOI 28nm UTBB FDSOI Analysis of Soft Error Rates in a 28nm UTBB FDSOI Structure by DeviceLevel Simulation Shigehiro Umehara Kuiyuan Zhang Masashi Hifumi Jun Furuta Kazutoshi Kobayashi Abstract: The impact of soft errors has been serious with process scaling of integrated circuits. Redundant circuits or SOI strucutes are used for radiation hardened circuits. In this paper, we build a device model and estimate static and dynamic characteristics and the soft error tolerance of 28nm UTBB FDSOI process by devicelevel simulation. The soft error tolerance is decreased by reducing supply voltage or by applying reverse body bias.. Department of Electronics, Kyoto Institute of Technology [] SOI (Silicon On Insulator) SOI (BOX (Buried OXide)) SOI (FD Fully Depleted) SOI BOX UTBB (Ultra Thin Body and Box) UTBB BOX 25 Information Processing Society of Japan 4 c 25 Information Processing Society of Japan
DA DA シンポジウム 25 27 DAS25 Design Automation Symposium 25/8/26 Gate Gate Source n Drain n Source n BOX Drain n 2 SOI 2 3 TCAD 4 PHITSTCAD 5 2. 2. (LSI) LSI [2] [3] [] 2.2 SEE (Single Event Effect) SEE SEU (Single Event Upset) SET (Single Event Transient) [4] SEU MCU (Multiple Cell Upset) [5] NMOS PMOS NMOS 2.3 [6] SOI SOI (Silicon On Insulator) CMOS (BOX Buried OXide) SiO 2 SOI BOX 2 SOI SOI SOI BOX SOI LSI SOI (PDSOI: Partially Depleted SOI) SOI (FDSOI: Fully Depleted SOI) [7] 2.4 UTBB (Ultra Thin Body and BOX) UTBB 3 [8] BOX UTBB (Ultra Thin Body and BOX) FDSOI SOI BOX nm UTBB 25nm BOX 25 Information Processing Society of Japan 42 c 25 Information Processing Society of Japan 2
DA DA シンポジウム 25 27 DAS25 Design Automation Symposium 25/8/26 Drain Current [a.u.].75.5.25 SPICE Simulation Device Simulation 3 28nmUTBB [8].2.4.6.8 Gate Voltage [a.u.] (a) NMOS (a) NMOS Drain Current [a.u.].75.5.25 SPICE Simulation Device Simulation (b) PMOS 4 FDSOI Highk Metal 3. TCAD TCAD 3. 28nm UTBB FDSOI 3D 4 I d V g 5 V gs =V I d V g NMOS, PMOS I d % 2 V in.4ff t LH.2.4.6.8 5 Gate Voltage[a.u.] (b) PMOS I d V g [a.u.] SPICE[a.u.] t LH.764 t HL.852 23.6% t HL 4.8% 3.2 NMOS LET V.4V LET 6 LET.4V LET V /5 V NMOS PMOS LET 7 NMOS 2MeV PMOS MeV LET V..9 PMOS PMOS 25 Information Processing Society of Japan 43 c 25 Information Processing Society of Japan 3
DA DA シンポジウム 25 27 DAS25 Design Automation Symposium 25/8/26 25 LET [MeVcm2/mg] 2 5 5 Gate Oxide STI S/D Spacer Substrate Gate.4.5.6.7.8.9 [V] 8 PHITS LET [MeVcm2/mg] 3 28 26 24 22 2 6 PMOS NMOS LET 8.6.4.2.2.4 7 [V] LET PMOS 4. PHITSTCAD PHITSTCAD [9] PHYSERD[] PHITSTCAD TCAD PHITS PHYSERD PHITS TCAD 4. PHITS PHITS Particle and Heavy Ion Transport code System 4.2 PHITSTCAD PHITS 8 PHITS 9 Deposit Energy TCAD Deposit charge Deposit Q 5fC Deposit Q MeV Deposit Energy [] LET Deposit Q Deposit Energy Deposit Energy PHITS Deposit Energy Deposit Energy PHITS SER SEU [FIT/Mbit] = 3.6 9 A n N SEU F 6 N n () A n PHITS N SEU N n F Flux 4.3 V.4V V 2.FIT/Mbit.4V 48.2FIT/Mbit V 22.5 4.4 2 V PMOS 25 Information Processing Society of Japan 44 c 25 Information Processing Society of Japan 4
DA DA シンポジウム 25 27 DAS25 Design Automation Symposium 25/8/26 Area of Neutrons.9um.2um 5 4 Nuclear Reaction Si Secondary Ion SiO2 (4um) SER [FIT/Mbit] 3 2 Sensitive Volume Si (5um) 25 2.9um 2.4um 9 PHITS.4.5.6.7.8.9 4 [V] Number of Errors 5 5 5 4 3 2 Threshould Deposit Energy [MeV] Deposit Energy SER [FIT/Mbit] 3 2.6.4.2.2.4 [V].4V.7FIT/Mbit.33.6V 3.2FIT/Mbit.5.4V 4.5 3.4V PMOS 5. 28nm UTBB FDSOI V.4V LET.2 22.5 No of errors 45 4 35 3 25 2 5 2 5 PMOS.6.4.2.2.4 3 [V] PMOS LET.9.5 JSPS 5H2677, 2688937 STARC 25 Information Processing Society of Japan 45 c 25 Information Processing Society of Japan 5
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