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みいかふくだ
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1 ITRS2005 DFM STRJ : () 1

2 ITRS STRJ ITRS2005DFM STRJ DFM ITRS: International Technology Roadmap for Semiconductors STRJ: Semiconductor Technology Roadmap committee of Japan 2

ITRS STRJ 1990 1998 2000 2005 1991 MicroTech 2000 Workshop Report 1992NTRS 1994NTRS 1997NTRS SIA Roadmap Europe Japan Korea Taiwan USA ITRS 1998 Update 1999 ITRS 2000

3 ITRS STRJ MicroTech 2000 Workshop Report 1992NTRS 1994NTRS 1997NTRS SIA Roadmap Europe Japan Korea Taiwan USA ITRS 1998 Update 1999 ITRS 2000 Update 2001 ITRS 2002 Update 2003 ITRS 2004 Update 2005 ITRS [1] STRJ STRJ STRJ STRJ STRJ STRJ STRJ [1] 3

4 WG, ITRS, STRJ WG WG Design Test Process Integration, Devices, and Structures ITRS Design Session DFM System Drivers Test PIDS STRJ WG WG1 Session 2004SoC WG2 WG6 2004RAM 4

5 ITRS STRJ ITRS2005DFM STRJ DFM ITRS: International Technology Roadmap for Semiconductors STRJ: Semiconductor Technology Roadmap committee of Japan 5

6 ITRS2005DFM DFM Critical Dimension NRE MOSFET Critical Dimension Cost NRE: Non-recurring engineering Design for Manufacturability (DFM) Challenge Source Gate Lg Lg Drain Design Methodology 6

7 Critical Dimension Critical Dimension MOSFET ITRS200310% Year of Production MPU Physical Gate Length (nm) Lgate 3s variation (nm) Critical Dimension10% DFM ITRS200512% Year of Production MPU Physical Gate Length (nm) Lgate 3s variation (nm) Manufacturable solution exist, and are being optimized Manufacturable solution are known Manufacturable solution are NOT known Source: ITRS

8 CD10 12% DFM 8

9 NRE Year of Production MPU/ASIC Metal1 ½ Pitch (nm) (Contacted) Mask cost ($m) from publicity available data SoC (System on a Chip) SoC Workaround FPGAConfigurable Logic Structured ASIC NRE: Non-recurring engineering Source: ITRS

10 Design for Manufacturability (DFM) TAT Challenge 10

11 DFM:, Challenge Tool Characterize Model 11

12 DFM: Challenge (MDR) 2MDR Rule 3MDRMDR (Pass/Fail MDR vsmdr MDR Critical RTL to GDS2RET OPC OPC 12

13 DFM: Challenge InteractionMDR Yeild Post P&R RET Yield 13

14 250~190nm 130~90nm 65nm~ Source: ITRS

15 65nm Source: ITRS

16 ITRS STRJ ITRS2005DFM STRJ DFM ITRS: International Technology Roadmap for Semiconductors STRJ: Semiconductor Technology Roadmap committee of Japan 16

17 STRJDFM LSI SoC RAM WG6: Process Integration, and Devices Structures 17

18 TFSoC 0.18 m, 140min. 200Hr MM MP3 JPEG MPEG4 Java RF Baseband SoC RAM ROM Flash 133MHz 0.18um 133MHz 170mW (typ.) CPU Cache 32KB MFI DSP URAM 128KB XYRAM 16KB MEM Cnt. CPG WDT CMT DMAC RAM VIF SCIF SIOF FLC MMC KEYIF RAM ROM Flash LCD 33MHz CMOS camera Bluetooth Sound NAND/AND Flash MMC KEY 66MHz 18

19 ITRS 19

20 STRJ TF, [2] I ON MOSFET CgVdd/Ion Ion Cg Ig Ioff L g t OX V th N A ITRS DC Ioff, Temp. V dd W t R sheet t ILD 20

21 [2] MOSFET Vth, ( L ) + V ( N ) + V ( Temp. ) V = V ( LER) th th g th A th V th Lg Lg Source mV/K -0.8mV/K Drain LER (Line Edge Roughness) - - Gate Source Drain Source Drain 21

22 (LOP) Typ. 27 Tr Typ Typ W = 0.36W(AC) W(Leak) 0.65W = 0.36W(AC) +0.29W(Leak) Typ s 100 Typ s 100 Typ s 100 Typ s W = 1.1W(AC) +10.5W(Leak) 1.27W =1.1W(AC) +0.17W(Leak) Typ s 100

23 STRJ PIDS SNM Line Edge Roughness (LER) SNMSRAM Static Noise Margin V L V R F. Tachibana and T. Hiramoto, Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin, SSDM, pp ,

24 SNM 2003 ITRS LOP45nmSNM 2 SNM Lg, Vdd, Vth, DIBL 4 SNM Lg nm) NA ( cm -3 ) DIBL (mv/v) Vdd (V) Vtsat@Vdd =0.7V (V) ITRS ITRS F. Tachibana and T. Hiramoto, Re-examination of Impact of Intrinsic Dopant Fluctuations on SRAM Static Noise Margin, SSDM, pp ,

25 LERSNM Line Edge Roughness (LER)SRAM SNM LER LER =2nm, LER SRAM a-P

26 ITRS2005DFM Critical Dimension NRE DFM STRJDFM TF LOP-Tr % WG6 PIDS 45nmRAM LER 26

27 1. International Technology Roadmap for Semiconductors 2005 (ITRS2005) ITRS2005 Design 2. JEITA STRJ ITRS

STRJ WS: March 4, 2003, 設計 TF/PIDS/FEP クロスカット設計 TF/PIDS/FEP クロスカット報告低電力 SoC のロードマップ - モバイルマルチメディアへのアプローチ - 設計 TF 主査日立製作所内山邦男

STRJ WS: March 4, 2003, 設計 TF/PIDS/FEP クロスカット設計 TF/PIDS/FEP クロスカット報告低電力 SoC のロードマップ - モバイルマルチメディアへのアプローチ - 設計 TF 主査日立製作所内山邦男設計 TF/PIDS/FEP クロスカット報告低電力 SoC のロードマップ - モバイルマルチメディアへのアプローチ - 設計 TF 主査日立製作所内山邦男本クロスカットの目的と活動内容低電力 SoCのロードマップ作成と問題点技術課題の明確化 (1) モバイルマルチメディアの動向調査 (2) 現状 (0.18um) の低電力 SoCの分析 (3) 低電力 SoC 設計モデルの作成 ( 初期モデル