STRJ WS: March 9, 2006,
0.35µm 0.8µm 0.3µm STRJ WS: March 9, 2006, 2
0.35µm Lot-to-Lot, Wafer-to-Wafer, Die-to-Die(D2D) D2D 0.8µm (WID: Within Die) D2D vs. WID 0.3µm D2Dvs. WID STRJ WS: March 9, 2006, 3
0.35µm:Good Old Days Ids (ma) 5 All Lots 0 Single Lot 5 58 Lots, 0 2 3 Vds(V) STRJ WS: March 9, 2006, 4 797 Wafers
0.35µm, D2D Ids (ma) 5 All Lots 0 Single Wafer 5 58 Lots, 0 2 3 Vds(V) STRJ WS: March 9, 2006, 5 797 Wafers
0.35µm Id_sat (pmos vs nmos) (?) STRJ WS: March 9, 2006, 6
0.8µm TEG 0.8µm, 2.9 mm, 20 TEG Ids 6 Transistors/chip Ring OSC TEGs Transistor TEG 20 RO 2,800 RO TEG 2 RO TEG STRJ WS: March 9, 2006, 7
WID 0.8µm, ~5% ~5% 5% 5% ( ) STRJ WS: March 9, 2006, 8
0.8µm: Ring OSC TEG 7 0 Sections Inv RO :7,3,9,29 : 5,0,20,40,60, NAND2 NAND4 RO 0 types of ROs STRJ WS: March 9, 2006, 9
: (WID) 3% : 9 :00 70 STRJ WS: March 9, 2006, 0
(WID) :00, 9 3% (D2D) (WID) (D2D) STRJ WS: March 9, 2006,
: Ids: : % TEG < TEG 2 % TEG < TEG 2 2% TEG Layout TEG2 STRJ WS: March 9, 2006, 2
0.3µm µ 3σ in a chip Drain Current 6 transistors/chip 56 chips/wafer (D2D) (WID) # (WID) (D2D) STRJ WS: March 9, 2006, 3
0.3µm: Ids (WID) (D2D) W 0µm 34 5 6 7 0.36µm 2 Transistor sizes 0 9 8 0.µm 0µm L STRJ WS: March 9, 2006, 4
Ids (WID) VDS=0.(V), VGS=.0(V) WL [Pelgrom, et al., J-SSC 989] Okada et.al., JJAP, p.3, 2005 STRJ WS: March 9, 2006, 5
STRJ WS: March 9, 2006, 6
C, R S W H T C R ( ) STRJ WS: March 9, 2006, 7
ITRS2005 Intermediate W,T,H : 3σ=30% 40 40 resistance variation[%] 20 0-20 resistance variation[%] 20 0-20 -40-40 -30-20 -0 0 0 20 30 40 50-30 -20-0 0 0 20 30 40 50 capacitance variation[%] capacitance variation[%] S=W S=7W ( 00%) ( 25%) STRJ WS: March 9, 2006, 8
0.5 Xp 0-0.5 SF=(-0.8,0.4) TT FF FS=(0.6,-0.5) FF, SS, TT, SF, FS Idsat nmos pmos SS - - -0.5 0 0.5 Xn STRJ WS: March 9, 2006, 9
+ STRJ WS: March 9, 2006, 20
Monte Carlo (CDF) ( ) 0.8 0.8 probability 0.6 0.4 probability 0.6 0.4 0.2 0.2 0 Id(sat) 0 delay time nmos Idsat CDF Inv (FO4) CDF STRJ WS: March 9, 2006, 2
( + ) Rtr R C CL W,T,H (Rtr) D = 0.4RC + 0.7( RtrC + RtrCL + RCL ) STRJ WS: March 9, 2006, 22
Intermediate S=W (lopt = 94µm, Xopt=32) regression coefficient 0.5 0-0.5 - output resistance width thickness height 0 00 000 0000 regression coefficient 0.5 0-0.5 - output resistance width thickness height 0 00 000 0000 wire length [um] wire length [um] X X6 STRJ WS: March 9, 2006, 23
Global S=W (lopt = 60 µm, Xopt = 67) regression coefficient 0.5 0-0.5 - output resistance width thickness height 0 00 000 0000 regression coefficient 0.5 0-0.5 - output resistance width thickness height 0 00 000 0000 wire length [um] wire length [um] X4 X32 STRJ WS: March 9, 2006, 24
Probability Density.2 0.8 0.6 0.4 0.2 D n= = max D i,2 n i circuit =,..., i n=0 n=00 n=000 D i : N(5, ) n 0 2 3 4 5 6 7 8 9 0 D circuit STRJ WS: March 9, 2006, 25
Probability Density 2.0.5.0 0.5 D circuit σ = 0.5 = max D,2,..., 00 i σ =.0 σ = 2.0 i= 0 5 6 7 8 9 0 2 3 D circuit i D i : N(5, σ) STRJ WS: March 9, 2006, 26
Probability Density.2 0.8 0.6 0.4 0.2 D circuit = max D,2,..., 00 i i= 0 2 3 4 5 6 7 8 9 0 D circuit i ρ = 0.0 ρ = 0.2 ρ = 0.4 ρ = 0.6 ρ = 0.8 ρ =.0 D i : N(5, σ) : ρ P,V,T STRJ WS: March 9, 2006, 27
Good News Bad News ( ) ( ) STRJ WS: March 9, 2006, 28
0.35µm 0.8µm 0.3µm STRJ WS: March 9, 2006, 29
(D2D,WID) ( ) (WID) / (Yamaoka et.al., ISSCC04/05) STRJ WS: March 9, 2006, 30
D2D, WID ACV ( ) LUT/ /PE STRJ WS: March 9, 2006, 3
P BC TYP WC L eff Cell Cell delay/si delay/si models models STRJ WS: March 9, 2006, 32
STA P WC P WC P WC L eff L eff L eff P P P L eff L eff L eff STRJ WS: March 9, 2006, 33
( STA) 2 3 2 2 3 2 2 3 3 2 3 4 4 3 4 3 P PDF(CDF) STRJ WS: March 9, 2006, 34
vs. DFF STRJ WS: March 9, 2006, 35
vs. vs. STRJ WS: March 9, 2006, 36
( ) LUT Katsuki, et.al. CICC05 Processing Unit (): LUT,, PE, etc. STRJ WS: March 9, 2006, 37
(0.35, 0.8, 0.3 µm) ( ) + LUT/ /PE STRJ WS: March 9, 2006, 38
STRJ WS: March 9, 2006, 39