RTN, (Random Telegraph ise: RTN) RTN charge trapping model ( ) RTN, RTN, MOSFET Verilog-A MOSFET, RTN MOSFET,, RTN,, RTN BSIM 42%, HiSIM 4%, Random Telegraph ise Simulation Method for Analog Circuits Takuya Komawaki MichitarouYabuuchi Ryo Kishida Kazutoshi Kobayashi Abstract: As device sizes are downscaled to the nanometer process, Rondom Telegraph ise (RTN) becomes dominant. It is necessary to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage flctuation to connect a DC voltage source to the gate of MOSFET implemented by using Verilog-A. We confirm that drain current of MOSFETs fluctuates temporally. Temporal fluctuations of RTN are defferent for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. However, noises are injected when a carrier captured or emitted. The amplitude of noises are 42% on the BSIM and 4% on the HiSIM. Those values are relatively large that can not be ignored.. MOSFET,,, [].,, RDF (Random Dopant Fluctuation), Depertment of Electronics, Kyoto Institute of Technology (Random Telegraph ise: RTN) RTN MOSFET, [2]. RTN CMOS [3], [4], SRAM[5] LW RTN /LW [6], RTN RTN RTN 8
[7], [8],, [7] MOSFET, V th,, MOSFET,,, RTN 2 RTN, 3 RTN 4, 5 2. (RTN), RTN 2. RTN RTN MOSFET,, [2]. τ c, τ e, τ τ, τ e, τ c [9]., 2, 2, V th trap [0]., charge trapping model ( ) BTI (Bias Temperature Instability) RTN []., RTN MOSFET n V th trap, τ, n, [2]. N P (n) () Gate Oxide Channel Capture Trap Emission Carrier : MOSFET RTN Vth Capture τ e (Time to emission) Emission Time τ (Time to capture) 2: RTN V th trap, τ V th trap, τ [][3]. V th trap η, PDF (Probability Density Function, ) (2) f single trap ( V th trap, η) = η exp ( Vth trap η c ) (2), 2.2 RTN τ, RTN, MOSFET MOSFET BSIM (Berkeley Shortchannel IGFET Model) HiSIM (Hiroshima-University Starc IGFET Model) BSIM, SPICE. 3(a) BSIM MOSFET, V OV = V GS V th RTN [7]. RTN Verilog-A, HiSIM 3(b) Verilog-A, P (n) = N n e N n! () 82
VOV BSIM (a) Verilog-A V th (t) HiSIM (b) Verilog-A V th (t)=v th0 + V th (t) 3: NMOSFET RTN BSIM(a) MOSFET Verilog-A RTN, V OV HiSIM (b) Verilog-A, PLH > P_rnd A j = High state (Capture) initial n Vth_trap_ j τ c_ j τ e_ j V th (t) = Σ ( j :, 2, n) Aj = 0 j = n n A j Vth_trap_ j j= j ++ PHL > P_rnd A j = 0 Low state (Emission) 4: RTN P LH (P HL ) P rnd, V th 3. RTN RTN (RTN ) RTN Verilog-A 4, RTN MOSFET n, V th trap, τ L = 60 nm, W = µm NMOSFET MOSFET 65 nm FDSOI : RTN L W n N D V th trap η s τ c τ e T unit P LH P HL n N [2], [2], D = 4.0 0 3 nm 2 N D, N = LW D = 240 V th trap η (3) η = s LW (3) s, [4] s = 9 V nm 2 τ 0 9 0 9 s [3]. τ V th trap τ,, [7]. Low,, High 4 A j j High, Low 0 Low High P LH, High Low P LH, High, Low P HL High P HL P LH P HL P LH = exp P HL = exp ( Tunit τ c ( Tunit τ e ) ) (4) (5) T unit τ, 83
0 P rnd, (6) V th k V th = A j V th trap j (6) j= k, V th trap j j V th SPICE 4. RTN SPICE, NMOS- FET NMOSFET, ps µs 3.5 Captured Defects 3 2.5 2.5 0.5 0-0.5 5: RTN V GS, V DS V, BSIM NMOS 5, 6 (a) RTN, RTN, RTN,. RTN,, MOSFET RTN RTN MOSFET, MOSFET, 6 (b) 6 (a) 6 (a).5%, 6 (b) 4.6%, RTN BSIM HiSIM. 3 HiSIM MOSFET RTN, MOSFET Verilog-A, BSIM rmalized Drain Current.0 0.99 0.98 0.97 0.96 BSIM 0.95 BSIM 0.95 (a) (b) 6: 2 (a) 5, rmalized Drain Current.0 0.99 0.98 0.97 0.96 84
Drain Current [a.u.] HiSIM 7: HiSIM BSIM, 7, BSIM 6 (a), BSIM 42%, RTN, 7 HiSIM, 4% BSIM, RTN [7], RTN 5., RTN BSIM,, RTN V OV HiSIM Verilog-A, RTN NMOSFET, BSIM, HiSIM, RTN MOSFET,, RTN.,, RTN BSIM 42%, HiSIM 4%, RTN, RTN RTN, RTN JSPS 5H02677,,,,, [] N. Weste and D. Harris, CMOS VLSI DESIGN A circuits and systems perspective Forth edition Addison Wesley, pp.20, 360-365, 200. [2] T. Grasser, B. Kaczer, W. Goes, H. Reisinger, T. Aichinger, P. Hehenberger, P.-J. Wagner, F. Schanovsky, J. Franco, P. Roussel, M. Nelhiebel, Recent advances in understanding the bias temperature instability Electron Devices Meeting (IEDM), 200 IEEE International, pp.4.4.-4.4.4, Dec., 200. [3] Jun-Myung Woo, Hong-Hyun Park, Hong Shick Min, Y. J. Park, Sung-Min Hong and Chan Hyeong Park, Statistical analysis of random telegraph noise in CMOS image sensors SISPAD, pp.77-80, Sep., 2008. [4] H. Kurata, K. Otsuga, A. Kotabe, S. Kajiyama, T. Osabe, Y. Sasago, S. Narumi, K. Tokami, S. Kamohara and O. Tsuchiya, Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm de JSSC, pp.362-369, June, 2007. [5] M. Tanizawa, S. Ohbayashi, T. Okagaki, K. Sonoda, K. Eikyu, Y. Hirano, K. Ishikawa, O. Tsuchiya and Y. Inoue, Application of a statistical compact model for Random Telegraph ise to scaled-sram Vmin analysis VLSIT, pp.95-96, June, 200. [6] J. Franco, B. Kaczer, M. Toledano-Luque, P. J. Roussel, J. Mitard, L. Å Ragnarsson, L. Witters, T. Chiarella, M. Togo, N. Horiguchi, G. Groeseneken, M. F. Bukhori, T. Grasser and A. Asenov, Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs IRPS, pp.5a.4.-5a.4.6, Apr., 202. [7] K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi and H. Onodera, Modeling of Random Telegraph ise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation ISQED, pp.-6, Mar., 20. [8] K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi and H. Onodera, The impact of RTN on performance fluctuation in CMOS logic circuits IRPS, pp.-6, Apr., 20. [9] M. Tanizawa, S. Ohbayashi, T. Okagaki, K. Sonoda, K. Eikyu, Y. Hirano, K. Ishikawa, O. Tsuchiya and Y. Inoue, Application of a statistical compact model for Random Telegraph ise to scaled-sram Vmin analysis [0] T. Matsumoto, K. Kobayashi and H. Onodera, Impact of Random Telegraph ise on CMOS Logic Circuit Re- 85
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