IC : = 2 MHz Max 2 : : TSSOP-20 RJJ03D0873-0200 Rev.2.00 2008.07.01 VIN Vout + DC 5 V DC 5 V DC 5 V DC 5 V DC 5 V Vbias (DC 12 V) VCC OUT -A GND OUT -B CS RAMP R2A20121 RT SYNC SS FB (+) OUT -C DELAY -1 OUT -D OUT OUT -E -F COMP FB ( ) DELAY DELAY -2-3 HAT3043C HAT3042C HAT3004R Page 1 of 27
SYNC RAMP CS COMP FB (+) FB ( ) SS DELAY-1 DELAY-2 DELAY-3 1 2 3 4 5 6 7 8 9 10 20 RT 19 GND 18 OUT-A 17 OUT-B 16 OUT-C 15 OUT-D 14 OUT-E 13 OUT-F 12 VCC 11 ( ) No. 1 SYNC 2 RAMP 3 CS 4 COMP 5 FB (+) (+) 6 FB ( ) ( ) 7 SS 8 DELAY-1 (OUT-A and B) 9 DELAY-2 (OUT-C and D) 10 DELAY-3 (OUT-E and F) 11 5 V / 20 ma 12 VCC 13 OUT-F 2 14 OUT-E 2 15 OUT-D 16 OUT-C 17 OUT-B 18 OUT-A 19 GND GND 20 RT Page 2 of 27
+ R2A20121SP VCC H UVLO L VCC > 8.4 V High UVL 5 V GENERATOR H GOOD L > 4.6 V High RT Current Ref. Generator START-UP COUNTER 32 CLOCK GOOD CIRCUIT BIAS OSCILLATOR RES DELAY OUT-A SYNC SYNC. I/O Q DELAY-1 FB ( ) FB (+) COMP ERROR AMP + 500 μ COMPARATOR 1.135 V R S Q DELAY DELAY DELAY OUT-B OUT-C DELAY-2 OUT-D RAMP CLAMP CIRCUIT + 1.55 V 1.46 V GOOD R S Q Zero Delay 4 V 10 μ SS GOOD DELAY OUT-E CS 1.4 V + PULSE BY PULSE Zero Delay DELAY DELAY-3 OUT-F GND Page 3 of 27
(Ta = 25 C) Vcc 20 V 1 Ipk-out ±50 ma 2, 3 Idc-out ±5 ma 3 Iref-out 20 ma 3 COMP Isink-comp 2 ma 3 Iset-delay 0.3 ma 3 RT Iset-rt 0.3 ma 3 Vter-ref 0.3 6 V 1, 4 Vter-1 0.3 (Vref + 0.3) V 1, 5 Tj-opr 40 +125 C 6 Tstg 55 +150 C 1. GND 2. 3. IC (+) ( ) 4. VCC 5. CS, RAMP, COMP, FB (+), FB ( ), SS, RT, SYNC, DELAY-1 3, OUT-A F 6. θja; 228 C/W 55 mm 45 mm 1.6 mm, 10% Page 4 of 27
SUPPLY OSCILLATOR SYNC (Ta = 25 C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.) Min Typ Max Start threshold VH 7.7 8.4 9.1 V Shutdown threshold VL 7.4 8.0 8.6 V UVLO hysteresis dvuvl 0.3 0.4 0.5 V Start-up current Is 90 150 μa Vcc = 7.5 V Operating current Icc 7 10 ma No load on pin Output voltage Vref 4.9 5.0 5.1 V Line regulation Vref-line 0 10 mv Vcc = 10 V to 16 V Load regulation Vref-load 6 20 mv Iref = 1 ma to 20 ma Temperature stability dvref/dta ±80 * 1 ppm/ C Ta = 40 to 105 C Oscillator frequency fosc 960 * 1 khz Switching frequency fsw 412 480 547 khz Measured on OUT-A, -B Line stability fsw-line 1.5 0 1.5 % Vcc = 10 V to 16 V Temperature stability dfsw/dta ±0.1 * 1 %/ C Ta = 40 to 105 C RT voltage VRT 2.5 2.7 2.9 V Input threshold VTH-SYNC 2.5 2.85 3.2 V Output high VOH-SYNC 3.5 4.0 V RSYNC = 33 kω to GND Output low VOL-SYNC 0.05 0.15 V RSYNC = 33kΩ to Minimum input pulse TI-MIN 50 ns Output pulse width TO-SYNC 500 ns 1. ( ) Page 5 of 27
ERROR AMPLIFIER (Ta = 25 C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.) Min Typ Max Input offset voltage Vos 2 3 8 mv FB ( ) and COMP are shorted. VFB (+) = 1.25 V FB (+) input current IFB (+) 2.0 0 2.0 μa FB (+) = FB ( ) = 1.25 V FB ( ) input current IFB ( ) 2.0 0 2.0 μa FB (+) = FB ( ) = 1.25 V Open-loop DC gain Av 80 * 1 db Unity gain bandwidth BW 2 * 1 MHz Output source current ISOURCE 650 500 390 μa FB (+) = 1.25 V, FB ( ) = 0.75 V, COMP = 2 V Output sink current ISINK 2.0 6.5 ma FB (+) = 1.25 V, FB ( ) = 1.75 V, COMP = 2 V Output high voltage VOH-EO 3.7 3.9 V FB (+) = 1.25 V, FB ( ) = 0.75 V, COMP; Open Output low voltage VOL-EO 0.1 0.4 V FB (+) = 1.25 V, FB ( ) = 1.75 V, COMP; Open Output clamp voltage * 4 VCLAMP-EO 0.16 0.07 0.0 V FB (+) = 1.25 V, FB ( ) = 0.75 V, COMP; Open, SS = 1 V PHASE RAMP offset voltage VRAMP 1.035 1.135 1.235 V MODULATOR RAMP bias current IRAMP 5 0.8 5 μa RAMP = 0.3 V RAMP sink current * 1 ISINK-RAMP 8 26 ma RAMP = 1 V, COMP = 0 V Minimum phase shift Dmin 0 * 1 * 5 % RAMP = 1 V, COMP = 0 V Maximum phase shift Dmax 97.0 * 1 * 5 % RAMP = 0 V, COMP = 2.1 V Delay to OUT-C, -D * 2 Tpd 30 60 ns COMP = 1.6 V RAMP discharge time * 1 Tdis 40 80 120 ns DELAY DELAY-1, -2, -3 * 3 TD1, 2, 3 22 33.5 45 ns Delay set R = 51 k DELAY2-1, -2, -3 * 1 * 3 TD2_1, _2, _3 70 100 130 ns Delay set R = 180 k Terminal voltage VD1, 2, 3 1.9 2.0 2.1 V Delay set R = 51 k 1. 2. Tpd RAMP 1 V 0 V 50% OUT-C/D 5 V 0 V 50% Tpd 3. TD1, 2, 3 TD1 TD1 OUT-A For primary control OUT-B OUT-C OUT-D 50% TD2 TD2 For secondary control OUT-E OUT-F TD3 TD3 4. VCLAMP-EO = VCOMP SS voltage (1 V) 5. Maximum/Minimum phase shift T2 D = 2 100 (%) T1 OUT-A OUT-B OUT-D T2 OUT-C T2 T1 Page 6 of 27 T1 ( )
(Ta = 25 C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.) Min Typ Max SOFT START Source current ISS 14 10 6 μa SS = 1 V SS high voltage VOH-SS 3.9 4.0 4.1 V OVER CURRENT PROTECTION Pulse-by-pulse current limit threshold Delay to OUT pins * 2 VCS-PP Tpd-cs 1.26 1.4 40 1.54 80 V ns CS = 0 V to 1.57 V OUTPUT High voltage VOH-OUT 4.3 4.8 V IOUT = 5 ma Low voltage VOL-OUT 0.1 0.4 V IOUT = 5 ma Rise time tr 5 15 ns COUT = 33 pf Fall time tf 5 15 ns COUT = 33 pf Timing offset * 3 TD4 3 20 ns 1. 2. Tpd-cs CS 1.57 V 0 50% OUT-C/D 50% Tpd-cs 3. TD4 OUT-D 50% OUT-C 50% OUT-E 50% OUT-F 50% TD4 TD4 Page 7 of 27
2 COMP RAMP + 1.135 V ( ) 1.135 V RAMP CS TD1 TD1 OUT-A OUT-B OUT-C OUT-D OUT-E TD3 TD2 TD3 TD2 OUT-F VIN OUT-A DRIVE MA MC DRIVE OUT-C OUT-B DRIVE MB MD DRIVE OUT-D RAMP DRIVE ME MF DRIVE OUT-E OUT-F Page 8 of 27
+ R2A20121SP VCC 8.4 V 8 V 0 V 5 V RES ( ) GOOD ( ) High Low 32 counts SS 0 V 4.0 V DISCHARGE ( ) High Low From Error Amp COMP COMPARATOR RAMP 1.135 V FOR PHASE MODULATION Current information CLAMP Css SS 4.0 V Iss 10 μa DISCHARGE SS IN Page 9 of 27
UVLO UVLO Under Voltage Lockout Operation IC IC IC 5 V () UVLO IC UVLO VCC VCC VCC ICC ICC Is 5 V 0 7.5 V 8.0 V 8.4 V 12 V 20 V VCC 0 8.0 V 8.4 V 20 V VCC 1 Start-up Counter GOOD ( ) Low R2A20121 GOOD VERFGOOD 32 CLOCK Start-up Counter VCC H L UVLO 5 V Generator GOOD H L From Oscillator Start-up Counter 32 clock GOOD Circuit Bias 2 IC UVLO 32 COUNT 1 MHz 32 μs UVLO (5 V) Start-up Counter (Start-up Counter ) VCC 8.4 V 8.0 V RES ( ) 4.6 V 32 counts 4.4 V GOOD ( ) 3 Page 10 of 27
Oscillator RT GND typical fosc = 1 25 [pf] RT [Ω] + 150 [ns] [Hz] 10000 fosc vs. RT R2A20121 fosc (khz) 1000 100 RT (2.7 V) SYNC RT GND 10 10 100 1000 RT (kω) 4 RT RT Synchronized Operation R2A20121 SYNC IC 1 4 IC IC RT RT 2 R2A20121 MASTER R2A20121 MASTER (2.7 V) RT SYNC SYNC RT (2.7 V) RT GND GND 2 RT R2A20121 MASTER SYNC RT (2.7 V) Max 4 slaves GND 2 RT 5 Page 11 of 27
R2A20121 SYNC R2A20121 1/2 SYNC 2 ma MASTER 2 ma SLAVE 5 R2A20121 MASTER LOGIC 10 ma (Vsync = 2.5 V ) 2 MHz 7 TTL or CMOS MASTER MASTER CLOCK R2A20121 MASTER SYNC RT (2.7 V) GND RT R2A20121 MASTER SYNC RT (2.7 V) GND RT 6 TIH-SYNC TIL-SYNC TCYCLE TI-MIN TIL-MIN Item TCYCLE TI-MIN TIL-MIN VIH-SYNC VIL-SYNC Input Range 500 ns Min 50 ns Min 100 ns Min 3.2 V to 0 V to 2.5 V 7 SYNC Page 12 of 27
R2A20121 SYNC SYNC 11 R2A20121 SYNC [V/μs] 10 9 8 7 6 5 4 3 2 1 0 100 150 200 250 300 350 400 Vref [mv] Page 13 of 27
RAMP RAMP RAMP 140 R2A20121 RAMP 120 [ns] 100 80 60 40 20 0 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 RAMP [pf] Page 14 of 27
Synchronous Phase Shift Full-Bridge Control R2A20121 Full-bridge OUT-A OUT-D 2 OUT-E, OUT-F OUT-A OUT-D TD1, TD2 ZVS (Zero Voltage Switching) OUT-E, OUT-F 2 Full-bridge ZVS + Current doubler RES pulse ( ) Full-Bridge (High ) SA SB SC SD TD2 TD1 (High ) SE SF TD3 1 VIN 0 VIN 2 VIN/N VIN/N 0 Subinterval : Time : 1 2 3 4 5 t0 t1 t2 t3 t4 t5 8 Subinterval: 1 1 SA, SD 1 VIN 2 1 2 SE SF VIN L1 SA SC SE Cr1 V11 SB Lr V12 SD Cr2 SF VOUT L2 Subinterval: 1 Page 15 of 27
Subinterval: 2 t1 SD 1 Cr2 Cr2 V12 L1, L2 Io V12 dv12 0.5 Io 1 = [ V/s ] (1) dt N Cr2 N 1 2 N = N1 / N2 Io SE, SF 2 VIN L1 SA SC SE Cr1 V11 SB Lr V12 SD Cr2 SF VOUT Subinterval: 2 Subinterval: 3 t2 SC SD (t1) SC (t2) ZVS (2) N TD2 = Cr2 VIN [s] (2) 0.5 Io SC 1 SC L2 VIN L1 SA SC SE Cr1 V11 SB Lr V12 SD Cr2 SF VOUT Subinterval: 3 Subinterval: 4 t3 SA 1 Cr1 V11 Lr Cr1, Lr V11 (3) fr = 1 [Hz] (3) 2 π (Cr1 Lr) L2 VIN L1 SA SC SE Cr1 V11 SB Lr V12 SD Cr2 SF VOUT L2 Subinterval: 4 Page 16 of 27
Subinterval: 5 t4 SF SF SF SF Lr Lr SF 2 1 2 SF R2A20121 TD3 Lr tr Lr Cr1 (4) 1 1 Treset (Lr) vpp VIN = 4 fr = 0.5 π (Lr Cr1) [s] (4) vpp vpp = Io 1 2 N (Lr / Cr1) [V] (5) VIN L1 SA SC SE Cr1 V11 SB Lr V12 SD Cr2 SF VOUT Subinterval: 5 Time: t5 t5 SB SB ( ) SB SB SB R2A20121 TD1 (4) t5 Subinterval 1 5 L2 VIN L1 SA SC SE Cr1 V11 SB Lr V12 SD Cr2 SF VOUT L2 Time: t5 Page 17 of 27
Delay Setting (TD1, TD2, TD3) DELAY-1 (-2, -3) GND typical TD = 0.5 [pf] RD [Ω] + 8 [ns] RD [s] 1.00E+03 TD vs. RD R2A20121 TD (ns) 1.00E+02 1.00E+01 1.00E+00 1 10 100 1000 RD (kω) (2.0 V) RD DELAY-1 (DELAY-2) (DELAY-3) GND 9 DELAY-1 (-2, -3) DELAY-3 (TD3) 2 OUT-E, OUT-F TD3 2 0 s (Typ) TD3 IC OUT-E, OUT-F Light load COMP < 1.55 V TD3 = 0 1, 3 Pulse by pulse OCL CS 1.4 V TD3 = 0 2, 3 1. FB ( ) FB (+) Error Amp. + 500 μ + Light Load Detector TD3 TD3 COMP RAMP + 1.135 V Comparator 0 1.46 V 1.55 V COMP Light Load Detector 2. (PBP OCL) OUT-E OUT-F TD3 0 s (Typ) PBP OCL Comparator OUT-C, OUT-D TD3 DELAY-3 3. IC SS 3.9 V TD3 = 0 SS Page 18 of 27
Slope Compensation 5 V () R2A20121 OUT-A OUT-B OUT-D OUT-C Current sense signal Compensated signal RAMP Comparator + 1.135 V S Q RES R 10 Driving a Pulse Transformer IC OUT-A OUT-F Vref CMOS Vref Vref Case 1 (NG) Vref R2A20121 Vref Cref Vref Internal Circuitry OUT-E Case 1 (NG) Case 2 Blocking diode CB Cref IC IC Blocking diode R2A20121 CB Cref Vref Internal Circuitry OUT-E Case 2 Page 19 of 27
Case 3 Cref R2A20121 CB Cref Internal Circuitry OUT-E Case 3 R2A20121 IC GOOD GOOD 4.6 V (Typ) 4.4 V IC 5 V Vext 5 V ± 2% Vcc R2A20121 11 Page 20 of 27
9.0 UVL 8.8 8.6 VH VH/VL [V] 8.4 8.2 8.0 VL 7.8 7.6 7.4 40 25 0 25 50 75 100 Ta [ C] 125 140 120 Vcc = 7.5 V 100 80 Is [μa] 60 40 20 0 40 25 0 25 50 75 100 125 Ta [ C] Page 21 of 27
12 10 8 Icc [ma] 6 4 2 0 40 25 0 25 50 75 100 125 Ta [ C] 5.20 5.15 5.10 5.05 [V] 5.00 4.95 4.90 4.85 4.80 40 25 0 25 50 75 100 125 Ta [ C] Page 22 of 27
10.0 8.0 6.0 Vos [mv] 4.0 2.0 0.0 2.0 4.0 6.0 40 25 0 25 50 75 100 125 Ta [ C] 100 FB (+) = 1.25 V, FB ( ) = 0.75 V, COMP = 2 V 200 ISOURCE [μa] 300 400 500 600 700 40 25 0 25 50 75 100 125 Ta [ C] Page 23 of 27
20 18 FB (+) = 1.25 V, FB ( ) = 1.75 V, COMP = 2 V 16 14 ISINK [ma] 12 10 8 6 4 2 0 40 25 0 25 50 75 100 125 Ta [ C] Iss [μa] 5 6 7 8 9 10 11 12 13 14 SS = 1 V 15 40 25 0 25 50 75 100 125 Ta [ C] Page 24 of 27
580 fsw [khz] 560 540 520 500 480 460 440 420 400 380 40 25 0 25 50 75 100 125 Ta [ C] 50 TD1 45 40 35 TD1 [ns] 30 25 20 15 40 25 0 25 50 75 100 125 Ta [ C] Page 25 of 27
70 60 50 Tpd [ns] 40 30 20 10 0 40 25 0 25 50 75 100 125 Ta [ C] 100 80 Tpd_cs [ns] 60 40 20 0 40 25 0 25 50 75 100 125 Ta [ C] Page 26 of 27
E R2A20121SP *1 D 20 11 F NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. b p *2 E H 1 c JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TSSOP20-4.4x6.5-0.65 PTSP0020JB-A TTP-20DAV 0.07g Index mark Z 1 e *3 b p 10 x M A y A Terminal cross section ( Ni/Pd/Au plating ) Detail F L 1 L θ Dimension in Millimeters Min Nom Max D 6.50 6.80 E 4.40 A 2 A 1 0.03 0.07 0.10 A 1.10 b p 0.15 0.20 0.25 b 1 c 0.10 0.15 0.20 c 1 θ 0 8 H E 6.20 6.40 6.60 e 0.65 x 0.13 y 0.10 Z 0.65 L 0.4 0.5 0.6 L 1 1.0 Reference Symbol Page 27 of 27
100-0004 2-6-2 100-0004 190-0023 980-0013 970-8026 312-0034 950-0087 390-0815 460-0008 541-0044 920-0031 730-0036 812-0011 2-6-2 ( ) 2-2-23 ( 2F) 1-1-20 ( 13F) 4-9 ( ) 832-2 ( 1F) 1-4-2 ( 3F) 1-2-11 ( 7F) -2-29 ( ) 4-1-1 ( ) 3-1-1 ( 8F) 5-25 ( 8F) 2-17-1 ( 5F) http://www.renesas.com (03) 5201-5350 (042) 524-8701 (022) 221-1351 (0246) 22-3222 (029) 271-9411 (025) 241-4361 (0263) 33-6622 (052) 249-3330 (06) 6233-9500 (076) 233-5980 (082) 244-2570 (092) 481-7695 E-Mail: csc@renesas.com 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 10.0