AK8857VQ Dual Channel Digital Video Decoder AK8857VQ NTSC, PAL, SECAM S(Y/C) 2 ITU-R BT.601 Y, Cb, Cr ITU-R BT.656 NTSC-J,M, NTSC-4.43 / PAL-B,D,G,H,I,N, Nc, M, PAL-60 / SECAM 2 S(Y/C) 1 4ch 11-bit 54MHz ADC 1ch PGA ( 3dB +10dB) Auto Gain Control (AGC) Auto Color Control (ACC) IP ( ) (Contrast, Saturation, Brightness, Hue, Sharpness) 2 YC ITU-R BT.601 (4:2:2_8bit) ITU-R BT.656 (4:2:2_8bit _EAV/SAV )* 720x487, 720x576, WVGA, VGA, WQVGA, QVGA,,, ( ) VBID(CGMS-A) (CRCC ) ( ) WSS ( ) I2C 1.70 2.00V 1.70 3.60V 40 C 85 C 64 LQFP ITU-R BT.656-1-
[1.]...6 [2.]...7 [3.]...8 [4.]...13 [4.1.]...13 [4.2.]...13 [4.3.]DC...14 [4.4.]...15 [4.5.]...15 [4.6.]...16 [5.]AC...17 [5.1.]...17 [5.2.] (DTCLK )...17 [5.3.]...18 [5.4.] ( )...18 [5.5.] /...19 [5.6.]...20 [5.7.]I2C...21 [5.7.1.] 1...21 [5.7.2.] 2...21 [6.]...22 [6.1.]...22 [6.2.],...23 [6.2.1.]...23 [6.2.2.]...23 [6.3.] ( )...25 [6.3.1.]720x487, 720x576(ITU-R BT.601)...26 [6.3.2.]640x480(VGA)...26 [6.3.3.]800x480(WVGA)...27 [6.3.4.]320x240(QVGA)...27 [6.3.5.]400x240(WQVGA), 400x234(EGA)...27 [6.3.6.]480x240(WEGA1), 480x234(WEGA2)...28 [6.3.7.]525 487...29 [6.3.8.]525 487 (60frm/sec) *...30 [6.3.9.]525 487 (30frm/sec) (ODD ) *...31 [6.3.10.]525 487 (30frm/sec) (EVEN ) *..32 [6.3.11.]525 480...33 [6.3.12.]525 480 (60frm/sec)...34-2-
[6.3.13.]525 480 (30frm/sec) (ODD )...35 [6.3.14.]525 480 (30frm/sec) (EVEN )...36 [6.3.15.]525 240 234 (ODD )...37 [6.3.16.]525 240 234 (EVEN )...38 [6.3.17.]625 576...39 [6.3.18.]625 576 (60frm/sec) *...40 [6.3.19.]625 576 (30frm/sec) (ODD )*...41 [6.3.20.]625 576 (30frm/sec) (EVEN )*...42 [6.3.21.]625 480...43 [6.3.22.]625 480 (60frm/sec) *...44 [6.3.23.]625 480 (30frm/sec) (ODD )*...45 [6.3.24.]625 480 (30frm/sec) (EVEN )*...46 [6.3.25.]625 240 234 (ODD )...47 [6.3.26.]625 240 234 (EVEN )...48 [6.4.]...49 [6.5.]...50 [6.6.]...51 [6.7.]...52 [6.8.]...55 [6.9.]...55 [6.10.]...56 [6.11.]VLOCK...57 [6.12.]Auto Gain Control (AGC)...58 [6.13.]Auto Color Control (ACC)...59 [6.14.]...59 [6.15.]Y/C...60 [6.16.]C...60 [6.17.]U/ V...61 [6.18.]...61 [6.19.]...62 [6.20.]...62 [6.21.]...62 [6.21.1.]EAV/SAV...62 [6.21.2.]...63 [6.22] Setup...64 [6.23.]PGA (Programable Gain Amp)...64 [6.24.]...65 [6.25.]...65 [6.26.]...66 [6.27.]...68-3-
[6.27.1.]...68 [6.27.2.]...68 [6.27.3.] (Saturation)...69 [6.27.4.] (HUE)...69 [6.27.5.]...69 [6.27.6.]...70 [6.27.7.]...70 [6.28.]VBI Information...71 [6.29.]...72 [6.30.]...73 [7.]...74 [7.1.] I2C SLAVE Address...74 [7.2.] I2C...74 [7.2.1.] Write...74 [7.2.2.] Read...74 [8.]...75 [9.]...77 [9.1.] Channel Select Register (R/W) [Sub Address 0x00]...77 [9.2.] AFE Control Register (R/W) [Sub Address 0x01] ( )...79 [9.3.] Output Control Register (R/W) [Sub Address 0x02] ( )...80 [9.4.] Start and Delay Control Register (R/W) [Sub Address 0x03] ( )...81 [9.5.] Control 1 Register (R/W) [Sub Address 0x04] ( )...82 [9.6.] Control 2 Register (R/W) [Sub Address 0x05] ( )...83 [9.7.] Pedestal Level Control Register (R/W) [Sub Address 0x06] ( )...84 [9.8.] Color Killer Control Register (R/W) [Sub Address 0x07] ( )...85 [9.9.] Image Control Register (R/W) [Sub Address 0x08] ( )...86 [9.10.] High Slice Data Set Register (R/W) [Sub Address 0x09] ( )...87 [9.11.] Low Slice Data Set Register (R/W) [Sub Address 0x0A] ( )...87 [9.12.] PGA Control 1 Register (R/W) [Sub Address 0x0B]...88 [9.13.] PGA Control 2 Register (R/W) [Sub Address 0x0C]...88 [9.14.] Output Data Format A Register (R/W) [Sub Address 0x0D] (A )...89 [9.15.] Output Data Format B Register (R/W) [Sub Address 0x25] (B )...89 [9.16.] Video Standard A Register (R/W) [Sub Address 0x0E] (A )...90 [9.17.] Video Standard B Register (R/W) [Sub Address 0x26] (B )...90 [9.18.] NDMODE A Register (R/W) [Sub Address 0x0F] (A )...91 [9.19.] NDMODE B Register (R/W) [Sub Address 0x27] (B )...91 [9.20.] Output Pin Control 0 A Register (R/W) [Sub Address 0x10] (A )...92 [9.21.] Output Pin Control 0 B Register (R/W) [Sub Address 0x28] (B )...92 [9.22.] Output Pin Control 1 A Register (R/W) [Sub Address 0x11] (A )...93 [9.23.] Output Pin Control 1 B Register (R/W) [Sub Address 0x29] (B )...93-4-
[9.24.] AGC & ACC A Control Register (R/W) [Sub Address 0x12] (A )...94 [9.25.] AGC & ACC B Control Register (R/W) [Sub Address 0x2A] (B )...94 [9.26.] Control 0 A Register (R/W) [Sub Address 0x13] (A )...95 [9.27.] Control 0 B Register (R/W) [Sub Address 0x2B] (B )...95 [9.28.] Contrast Control A Register (R/W) [Sub Address 0x14] (A )...96 [9.29.] Contrast Control B Register (R/W) [Sub Address 0x2C] (B )...96 [9.30.] Brightness Control A Register (R/W) [Sub Address 0x15] (A )...96 [9.31.] Brightness Control B Register (R/W) [Sub Address 0x2D] (B )...96 [9.32.] Saturation Control A Register (R/W) [Sub Address 0x16] (A )...97 [9.33.] Saturation Control B Register (R/W) [Sub Address 0x2E] (B )...97 [9.34.] HUE Control A Register (R/W) [Sub Address 0x17] (A )...97 [9.35.] HUE Control B Register (R/W) [Sub Address 0x2F] (B )...97 [9.36.] Request VBI Infomation A Register (R/W) [Sub Address 0x18] (A )...98 [9.37.] Request VBI Infomation B Register (R/W) [Sub Address 0x30] (B )...98 [9.38.] Status 1 A Register (R) [Sub Address 0x19] (A )...99 [9.39.] Status 1 B Register (R) [Sub Address 0x31] (B )...99 [9.40.] Status 2 A Register (R) [Sub Address 0x1A] (A )...100 [9.41.] Status 2 B Register (R) [Sub Address 0x32] (B )...100 [9.43.] Video Status A Register (R) [Sub Address 0x34] (B )...101 [9.44.] Closed Caption 1 A Register (R) [Sub Address 0x1D] (A )...102 [9.45.] Closed Caption 1 B Register (R) [Sub Address 0x35] (B )...102 [9.46.] Closed Caption 2 A Register (R) [Sub Address 0x1E] (A )...102 [9.47.] Closed Caption 2 B Register (R) [Sub Address 0x36] (B )...102 [9.48.] WSS 1 A Register (R) [Sub Address 0x1F] (A )...102 [9.49.] WSS 1 B Register (R) [Sub Address 0x37] (B )...102 [9.50.] WSS 2 A Register (R) [Sub Address 0x20] (A )...102 [9.51.] WSS 2 B Register (R) [Sub Address 0x38] (B )...102 [9.52.] Extended Data 1 A Register (R) [Sub Address 0x21] (A )...103 [9.53.] Extended Data 1 B Register (R) [Sub Address 0x39] (B )...103 [9.54.] Extended Data 2 A Register (R) [Sub Address 0x22] (A )...103 [9.55.] Extended Data 2 B Register (R) [Sub Address 0x3A] (B )...103 [9.56.] VBID 1 A Register (R) [Sub Address 0x23] (A )...103 [9.57.] VBID 1 B Register (R) [Sub Address 0x3B] (B )...103 [9.58.] VBID 2 A Register (R) [Sub Address 0x24] (A )...103 [9.59.] VBID 2 B Register (R) [Sub Address 0x3C] (B )...103 [9.60.] Device and Revision ID Register (R) [Sub Address 0x3D]...104 [10.]...105 [11.]...106 [12.]...107-5-
[1.] TEST0 TEST1 XTI XTO SELA SDA SCL PDN RSTN OE_A OE_B TEST LOGIC Clock Module PLL Microprocessor Interface DATA_A[7:0] _ACT_A _ACT_A AIN1 _A AIN2 AIN3 MUX CLAMP CLAMP AAF AAF MUX 11-bit ADC MUX Digital PGA1 Digital PGA2 Decimation Filter Decimation Filter Sync Separation Composite Decode x 2 Sync Separation or Y/C Docode x 1 Scaling & I/P Buffer _A DTCLK DATA_B[7:0] _ACT_B AIN4 _ACT_B _B _B VREF NSIG_A NSIG_B VRP VCOM VRN IREF AD AVSS DD DVSS PD1 PD2 DTCLK A DTCLK B -6-
[2.] DVSS PD1 DATA_B6 DATA_B5 DATA_B4 DATA_B3 DATA_B2 DATA_B1 DATA_B0 PD1 DVSS DD TEST0 TEST1 NSIG_B NSIG_A 48 47 46 45 444342414039 383736353433 OE_B OE_A PD2 RSTN PDN SDA SCL SELA AD XTO AVSS XTI VRN IREF VRP VCOM 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DATA_B7 _ACT_B _ACT_B _B _B DTCLK PD1 _A _A _ACT_A _ACT_A DATA_A7 DATA_A6 PD1 DVSS DD 1 2 3 4 5 6 7 8 9 10 111213141516 DATA_A5 DATA_A4 DATA_A3 DATA_A2 DATA_A1 DATA_A0 PD1 DVSS AVSS AIN4 AD AIN3 AVSS AIN2 AD AIN1-7-
[3.] I/O 1 AIN1 A I 2 AD A P 3 AIN2 A I 4 AVSS A G 5 AIN3 A I 6 AD A P 7 AIN4 A I 8 AVSS A G 9 DVSS D G 10 PD1 P1 P I/O 11 DATA_A0 P1 12 DATA_A1 P1 13 DATA_A2 P1 14 DATA_A3 P1 15 DATA_A4 P1 16 DATA_A5 P1 O ( I ) O ( I ) O ( I ) O ( I ) O ( I ) O ( I ) 17 DD D P 18 DVSS D G [ ] 39%( 8.19dB) 0.033uF NC [ ] 39%( 8.19dB) 0.033uF NC [ ] 39%( 8.19dB) 0.033uF NC [ ] 39%( 8.19dB) 0.033uF NC A OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) -8-
I/O 19 PD1 P1 P I/O 20 DATA_A6 P1 21 DATA_A7 P1 22 _ACT_A P1 23 _ACT_A P1 24 _A P1 25 _A P1 O ( I ) O ( I ) O ( I ) O ( I ) O ( I ) O ( I ) 26 PD1 P1 P I/O 27 DTCLK P1 O 28 _B P1 29 _B P1 30 _ACT_B P1 31 _ACT_B P1 O ( I ) O ( I ) O ( I ) O ( I ) A OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) A (Vertical Drive) / (Vertical Active) / OE_A / PDN / RSTN (*1) ( ) A (Horizontal Drive) / (Horizontal Active) / OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) A OE_A / PDN / RSTN (*1) ( ) I/F 27MHz 54MHz OE_A / OE_B / PDN / RSTN (*1) B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) B (Horizontal Drive) / (Horizontal Active) / OE_B / PDN / RSTN (*1) ( ) B (Vertical Drive) / (Vertical Active) / OE_B / PDN / RSTN (*1) ( ) -9-
I/O 32 DATA_B7 P1 O ( I ) 33 DVSS D G 34 PD1 P1 P I/O 35 DATA_B6 P1 36 DATA_B5 P1 37 DATA_B4 P1 38 DATA_B3 P1 39 DATA_B2 P1 40 DATA_B1 P1 41 DATA_B0 P1 O ( I ) O ( I ) O ( I ) O ( I ) O ( I ) O ( I ) O ( I ) 42 PD1 P1 P I/O 43 DVSS D G 44 DD D P B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) B OE_B / PDN / RSTN (*1) ( ) 45 TEST0 P2 I DVSS 46 TEST1 P2 I DVSS 47 NSIG_B P2 48 NSIG_A P2 O ( I ) O ( I ) B Low : ( ) High : OE_B / PDN / RSTN (*1)( ) A Low : ( ) High : OE_A / PDN / RSTN (*1)( ) -10-
I/O 49 OE_B P2 I 50 OE_A P2 I B Output Enable L : B Hi-z (*2) H : OE_B Hi-z A Output Enable L : A Hi-z (*2) H : OE_A Hi-z 51 PD2 P2 P I/F 52 RSTN P2 I 53 PDN P2 I 54 SDA P2 I/O 55 SCL P2 I 56 SELA P2 I ( O ) 57 AD A P 58 XTO A O Hi-z L : H : Hi-z L : H : 59 AVSS A G 60 XTI A I 61 VRN A O 62 IREF A O I2C PD2 RSTN=L Hi-z SDA I2C PD2 PDN=L Hi-z SCL I2C PD2 : [0x8A] DVSS : [0x88] ( Output ) ( : 22pF ) 27MHz PDN=L AVSS AVSS ( : 22pF ) 27MHz 27MHz AD 0.1uF AVSS 6.8kΩ(±1% ) AVSS -11-
I/O 63 VRP A O 64 VCOM A O AD 0.1uF AVSS AD 0.1uF AVSS [ ] A: AD, D: DD, P1: PD1, P2: PD2 [I/O] I:, O:, I/O:, P:, G: (*1) OE_A, OE_B, PDN, RSTN OE_A, OE_B (*2) PDN RSTN Output1 (*2) Output2 (*2) L x x Hi-Z L H L x L L H H L L L H Default Data Out (*3) Default Data Out (*3) (*2) Output1 : (A ) DATA_A[7:0], _ACT_A, _ACT_A, _A, _A (B ) DATA_B[7:0], _ACT_B, _ACT_B, _B, _B DTCLK Output1 OE_A OE_B Low DTCLK Hi-Z Output2 : NSIG_A, NSIG_B (*3)AIN (Y=0x10, Cb/Cr=0x80) ( ) (OE_A=H OE_B=H) PDN=H -12-
[4.] [4.1.] AD, DD, PD1, PD2 A (VinA) P1 (VioP1) P2 (VioP2) (Iin) ( ) 0.3 0.3 2.2 4.2 0.3 AD + 0.3 ( 2.2) V 0.3 PD1 + 0.3 ( 4.2) V (*1) 0.3 PD2 + 0.3 ( 4.2) V (*2) V V 10 10 ma 40 125 ºC (DVSS=AVSS) 0V( ) (AVSS, DVSS) (*1) DATA_A[7:0], _ACT_A, _ACT_A, _A, _A, DATA_B[7:0], _ACT_B, _ACT_B, _B, _B, DTCLK (*2) OE_A, OE_B, SELA, PDN, RSTN, SDA, SCL, NSIG_A, NSIG_B, TEST0, TEST1 [4.2.] (AD) (DD) 1.70 1.80 2.00 V AD=DD I/O (PD1) I/F (PD2) 1.70 1.80 3.60 V PD1 DD PD2 DD (Ta) 40 85 ºC (DVSS=AVSS) 0V( ) (AVSS, DVSS) -13-
[4.3.]DC ( ) P2 H P2 L VPIH VPIL 0.8PD2 V *1 0.7PD2 V *2 0.2PD2 V *1 0.3PD2 V *2 XTI H VAIH 0.8AD V XTI L VAIL 0.2AD V IL ±10 ua P1 H VP1OH 0.8PD1 V IOH = 600uA P1 L VP1OL 0.2PD1 V IOL = 1mA P2 H VP2OH 0.8PD2 V IOH = 600uA P2 L VP2OL 0.2PD2 V IOL = 1mA I 2 C(SDA)L VOLC 0.4 0.2 PD2 V IOLC = 3mA PD2 2.0V PD2 2.0V *1: < DD = 1.70V2.00V, DD PD1 2.70V, DD PD2 2.70V, Ta: 4085 C > *2: < DD = 1.70V2.00V, 2.70V PD1 3.60V, 2.70V PD2 3.60V, Ta: 4085 C > P2 SDA, SCL, SELA, OE_A, OE_B, PDN, RSTN, TEST0, TEST1 P1 DATA_A[7:0], _ACT_A, _ACT_A, _A, _A, DATA_B[7:0], _ACT_B, _ACT_B, _B, _B, DTCLK P2 NSIG_A, NSIG_B SDA -14-
[4.4.] (AD=1.8V, 25 C) VIMX 0 0.50 0.60 V PP 0.6Vpp ADC RES 11 bit FS 27 MHz ADC 54MHz INL ±2.0 ±4.0 LSB FS=27MHz 0.5Vpp DNL ±0.5 +1.5 1.0 S/N SN 54 db S/(N+D) SND 52 db ADC VCOM 0.96 V ADC VREF VRP 1.28 V ADC VREF VRN 0.64 V LSB FS=27MHz 0.5Vpp Fin=1MHz, FS=27MHz 0.5Vpp (Fin = AIN ) AAF(Anti-Aliasing Filter) Gp 1 +1 db 6MHz Gs 20 35 db 27MHz [4.5.] (DD = AD = PD1 = PD2 = 1.8V, Ta = 40 85 C ) (*1) ( ) IDD1 86 130 ma CVBS (2ch) (*2) IDD2 63 ma CVBS (1ch) (*2) IDD3 75 112 ma S(Y/C) (*2) AIDD 39 ma DIDD 34 ma I/O PIDD 13 ma ( ) SIDD 1 20 ua ASIDD 1 ua DSIDD 1 ua CVBS (2ch) Xtal CVBS (2ch) : CL=12pF, 24pF* (*DTCLK ) PDN=L(DVSS) (*3) I/O PSIDD 1 ua (*1)NTSC-J 100% (*2) A B (*3) OE_A OE_B RSTN -15-
[4.6.] f 0 27 MHz Δf / f ±100 ppm CL 15 pf Re 100 Ω (*1) CO 0.9 pf (Ta : 4085 ) XTI CXI 22 pf CL=15pF XTO CXO 22 pf CL=15pF (*1) Re = R1 x (1+CO/CL) 2 [R1]: Rf AK8857VQ XTI pin XTO pin Rd (* 2) CXI = 22pF CXO = 22pF (*2) (Rd) AK8857VQ AK8857-16-
[5.]AC (DD=1.70V2.00V, PD1=DD3.60V, PD2=DD3.60V, 4085 ) CL=12pF, 24pF(DTCLK ) [5.1.] AK8857 fclk tclkl tclkh VIH 1/2 VIL CLK fclk 27 MHz CLK H tclkh 15 nsec CLK L tclkl 15 nsec ±100 ppm [5.2.] (DTCLK ) 54 601,VGA, WVGA DTCLK fdtclk MHz 27 601,VGA, WVGA fdtclk 0.5PD1-17-
[5.3.] DATA_A[7:0], _ACT_A, _ACT_A, _A, _A, DATA_B[7:0], _ACT_B, _ACT_B, _B, _B DTCLK 0.5PD1 tds tdh OUTPUT DATA 0.5PD1 DTCLK Output Data Setup Time Output Data Hold Time tds tdh 10 nsec 27MHz 5 nsec 54MHz 10 nsec 27MHz 5 nsec 54MHz [5.4.] ( ) RSTN VIL RESETTIMING fclk RSTN RESETTIMING 100 (3.7) CLK (usec) CLK * RSTN Low -18-
[5.5.] / PDN (PDN=Low) 2048 83.33usec PDN (PDN=Hi) 5msec CLKIN RSTN RESs RESh VIH VIL PDN GND VIH PDN RESs 2048 (75.85) CLK (usec) PDN=Hi RSTN=Hi RESh 5 msec VIH/VIL * AD/DD PD1/PD2 PDN RSTN XTI VCOM,VRP,VRN : 5 ms (max) * PDN RESh 5ms(min) * -19-
[5.6.] / (*1) PDN =Low 100msec D PDN PWUPTIME RSTN VIL VREF RESPON POWERUP TIME PWUPTIME 100 msec RSTN RESPON 5 msec (*1) -20-
[5.7.]I2C (DD=1.70V2.00V, PD1=DD3.60V, PD2=DD3.60V, 4085 ) [5.7.1.] 1 tbuf t : STA tr tf tsu : STO SDA VIH VIL tf tr SCL VIH VIL tlow tsu : STA Bus Free Time tbuf 1.3 usec Hold Time (Start Condition) t:sta 0.6 usec Clock Pulse Low Time tlow 1.3 usec Signal Rise Time tr 300 nsec Signal Fall Time tf 300 nsec Setup Time(Start Condition) tsu:sta 0.6 usec Setup Time(Stop Condition) tsu:sto 0.6 usec I2C I2C I2C [5.7.2.] 2 t : DAT SDA VIH VIL thigh SCL VIH VIL TSU : DAT Data Setup Time tsu:dat 100(*1) nsec Data Hold Time t:dat 0.0 0.9(*2) usec Clock Pulse High Time thigh 0.6 usec (*1)I2C tsu:dat 250nSec (*2)AK8857 tlow (tlow= ) -21-
[6.] [6.1.] AK8857 4ch (CVBS) S(Y/C) AINSEL[4:0] AK8857 2ch A B (Sub-Address 0x00[4:0]) Analog Select[4:0] Definition A B [AINSEL4: AINSEL0] [00000]: [A]: AIN1(CVBS) [B]: AIN4(CVBS) [00001]: [A]: AIN1(CVBS) [B]: AIN3(CVBS) [00010]: [A]: AIN1(CVBS) [B]: AIN2(CVBS) [00011]: [A]: AIN1(CVBS) [B]: AIN1(CVBS) [00100]: [A]: AIN1(CVBS) [B]: [00101]: [A]: AIN2(CVBS) [B]: AIN4(CVBS) [00110]: [A]: AIN2(CVBS) [B]: AIN3(CVBS) [00111]: [A]: AIN2(CVBS) [B]: AIN2(CVBS) [01000]: [A]: AIN2(CVBS) [B]: AIN1(CVBS) [01001]: [A]: AIN2(CVBS) [B]: [01010]: [A]: AIN3(CVBS) [B]: AIN4(CVBS) [01011]: [A]: AIN3(CVBS) [B]: AIN3(CVBS) [01100]: [A]: AIN3(CVBS) [B]: AIN2(CVBS) [01101]: [A]: AIN3(CVBS) [B]: AIN1(CVBS) [01110]: [A]: AIN3(CVBS) [B]: [01111]: [A]: AIN4(CVBS) [B]: AIN4(CVBS) [10000]: [A]: AIN4(CVBS) [B]: AIN3(CVBS) [10001]: [A]: AIN4(CVBS) [B]: AIN2(CVBS) [10010]: [A]: AIN4(CVBS) [B]: AIN1(CVBS) [10011]: [A]: AIN4(CVBS) [B]: [10100]: [A]: [B]: AIN4(CVBS) [10101]: [A]: [B]: AIN3(CVBS) [10110]: [A]: [B]: AIN2(CVBS) [10111]: [A]: [B]: AIN1(CVBS) [11000]: [A]: AIN1(Y) / AIN3(C) [B]: [11001]: [A]: AIN1(Y) / AIN3(C) [B]: AIN1(Y) / AIN3(C) [11010]: [A]: AIN2(Y) / AIN4(C) [B]: [11011]: [A]: AIN2(Y) / AIN4(C) [B]: AIN2(Y) / AIN4(C) [11100]: [A]: [B]: AIN1(Y) / AIN3(C) [11101]: [A]: [B]: AIN2(Y) / AIN4(C) Low DATA_A[7:0], _ACT_A, _ACT_A, _A, _A, DATA_B[7:0], _ACT_B, _ACT_B, _B, _B, NSIG_A, NSIG_B OE_A, OE_B, PDN, RSTN -22-
[6.2.], [6.2.1.] AK8857 AD ( ) フィルター特性 ±1dB ( 6MHz ) 35dB ( 27MHz ).Typical Gain[dB] 10 0-10 -20-30 -40-50 -60-70 -80 0.1 1 10 100 Frequency[MHz] [6.2.2.] AK8857 AK8857 ( ) AK8857 S(Y/C) (Y ) AK8857 Y AK8857 ( ) (C ) AK8857 C Y ( ) Y CVBS C -23-
CLPWIDTH[1:0] (Sub-Address 0x01[7:6]) CLPWIDTH[1:0]-bit [00] 296nsec ( ) [01] 593nsec [10] 1.1usec [11] 2.2usec CLPSTAT[1:0] CLPSTAT[1:0]-bit [00] ( ) [01] (1/128)H [10] (2/128)H [11] (1/128)H (Sub-Address 0x01[5:4]) CLPSTAT[1:0] = 00 CLPWIDTH[1:0] CLPSTAT[1:0] = 01 1/128H CLPSTAT[1:0] = 11 1/128H CLPSTAT[1:0] = 10 2/128H CLPG[1:0] (Sub-Address 0x01[1:0]) CLPG[1:0]-bit [00] Min. [01] Middle 1 ( ) [10] Middle 2 [11] Max. Middle 1 = (Min. x 3 ) Middle 2 = (Min. x 5 ) Max. = (Min. x 7 ) UDG[1:0] (Sub-Address 0x01[3:2]) UDG[1:0]-bit [00] Min. ( ) [01] Middle 1 [10] Middle 2 [11] Max. Middle 1 = (Min. x 2 ) Middle 2 = (Min. x 3 ) Max. = (Min. x 4 ) ADC -24-
[6.3.] ( ) AK8857 (Sub-Address 0x0D, 0x25[4:0]) 525 NTSC-M, J, NTSC-4.43, PAL-M, PAL-60 625 PAL-B,D,G,H,I,N, PAL-Nc SECAM 720x487 (ITU-R BT.601) 800x480 (WVGA) 640x480 (VGA) 27MHz 54MHz (*1) 27MHz 54MHz (*1) 27MHz 54MHz (*1) 400x240 (WQVGA) 27MHz (*2) 320x240 (QVGA) 27MHz (*2) 400x234(EGA) 27MHz (*2) 480x240(WEGA1) 27MHz (*2) 480x234(WEGA2) 27MHz (*2) 720x576 (ITU-R BT.601) 800x480 (WVGA) 640x480 (VGA) 27MHz 54MHz (*1) 27MHz 54MHz (*1) 27MHz 54MHz (*1) 400x240 (WQVGA) 27MHz (*2) 320x240 (QVGA) 27MHz (*2) 400x234(EGA) 27MHz (*2) 480x240(WEGA1) 27MHz (*2) 480x234(WEGA2) 27MHz (*2) (*1) 30frm/sec* 60frm/sec* (*2) *frm/sec 1-25-
1 1 EAV 625 [6.3.1.]720x487, 720x576(ITU-R BT.601) 128CLK 244CLK (264CLK) 1440CLK 32CLK (24CLK) [6.3.2.]640x480(VGA) 128CLK 324CLK (344CLK) 1280CLK 112CLK (104CLK) -26-
[6.3.3.]800x480(WVGA) 84CLK (104CLK) [6.3.4.]320x240(QVGA) 128CLK 1600CLK 32CLK (24CLK) 128CLK 644CLK (664CLK) [6.3.5.]400x240(WQVGA), 400x234(EGA) 640CLK 432CLK (424CLK) 128CLK 564CLK (584CLK) 800CLK 352CLK (344CLK) -27-
[6.3.6.]480x240(WEGA1), 480x234(WEGA2) 128CLK 484CLK (504CLK) 960CLK 272CLK (264CLK) 1-28-
[6.3.7.]525 487 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 EVEN ODD 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 ODD EVEN 276 277 278 279 280 281 282 283 284 285 286 287 288 522-29-
[6.3.8.]525 487 (60frm/sec) * 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 522 A B C D A B C D *ODD/ EVEN 486 487-30-
[6.3.9.]525 487 (30frm/sec) (ODD ) * 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260 A B C D 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 522 A B C D * 486 487-31-
[6.3.10.]525 487 (30frm/sec) (EVEN ) * 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 522 A B C D A B C D * 486 487-32-
[6.3.11.]525 480 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 EVEN ODD 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 ODD EVEN 276 277 278 279 280 281 282 283 284 285 286 287 288 522-33-
[6.3.12.]525 480 (60frm/sec) 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 522 A B C D A B C D -34-
[6.3.13.]525 480 (30frm/sec) (ODD ) 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260 A B C D 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 522 A B C D -35-
[6.3.14.]525 480 (30frm/sec) (EVEN ) 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 522 A B C D A B C D -36-
[6.3.15.]525 240 234 (ODD ) 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 EVEN ODD 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 ODD EVEN 276 277 278 279 280 281 282 283 284 285 286 287 288 522 234 22 24 259 261 (, [High] ) -37-
[6.3.16.]525 240 234 (EVEN ) 523 524 525 1 2 3 4 5 6 7 8 9 10 11 12 EVEN ODD 13 14 15 16 17 18 19 20 21 22 23 24 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 ODD EVEN 276 277 278 279 280 281 282 283 284 285 286 287 288 522 234 285 287 522 524 (, [High] ) -38-
[6.3.17.]625 576 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 EVEN ODD 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 ODD EVEN 322 277 334 335 336 337 338 339 340 341 342 343 344 619-39-
[6.3.18.]625 576 (60frm/sec) * 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 277 334 335 336 337 338 339 340 341 342 343 344 619 A B C D A B C D * ODD/ EVEN 574 576 VBIL[2:0] [001] -40-
[6.3.19.]625 576 (30frm/sec) (ODD )* 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 306 A B C D 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 277 334 335 336 337 338 339 340 341 342 343 344 619 A B C D * 574 576 VBIL[2:0] [001] -41-
[6.3.20.]625 576 (30frm/sec) (EVEN )* 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 277 334 335 336 337 338 339 340 341 342 343 344 619 A B C D A B C D * 574 576 VBIL[2:0] [001] -42-
[6.3.21.]625 480 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 EVEN ODD 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 ODD EVEN 322 277 334 335 336 337 338 339 340 341 342 343 344 619 25 338 5 ( [High] ) EAV SAV -43-
[6.3.22.]625 480 (60frm/sec) * 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 277 334 335 336 337 338 339 340 341 342 343 344 619 A B C D A B C D 25 338 10 ( [High] ) EAV SAV * ODD/ EVEN 478 480 VBIL[2:0] [001] -44-
[6.3.23.]625 480 (30frm/sec) (ODD )* 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 306 A B C D 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 277 334 335 336 337 338 339 340 341 342 343 344 619 A B C D 25 10 ( [High] ) EAV SAV * 478 480 VBIL[2:0] [001] -45-
[6.3.24.]625 480 (30frm/sec) (EVEN )* 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 277 334 335 336 337 338 339 340 341 342 343 344 619 A B C D A B C D 338 10 ( [High] ) EAV SAV * 478 480 VBIL[2:0] [001] -46-
[6.3.25.]625 240 234 (ODD ) 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 EVEN ODD 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 ODD EVEN 322 277 334 335 336 337 338 339 340 341 342 343 344 619 25 5 ( [High] ) EAV SAV 234 23 26 308 310 (, [High] ) -47-
[6.3.26.]625 240 234 (EVEN ) 620 621 622 623 624 625 1 2 3 4 5 6 7 8 9 EVEN ODD 10 21 22 23 24 25 26 27 28 29 30 31 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 ODD EVEN 322 277 334 335 336 337 338 339 340 341 342 343 344 619 338 5 ( [High] ) EAV SAV 234 336 339 621 623 (, [High] ) -48-
[6.4.] AK8857 NTSC-M, J / NTSC-4.43 / PAL-B, D, G, H, I, N / PAL-Nc / PAL-M / PAL-60 / SECAM VSCF[1:0]-bit VSCF[1:0]-bit (MHz) [00] 3.57954545 NTSC-M,J [01] 3.57561149 PAL-M [10] 3.58205625 PAL-Nc [11] 4.43361875 (Sub-Address 0x0E, 0x26[1:0]) PAL-B,D,G,H,I,N, NTSC-4.43, PAL-60 SECAM* * SECAM VSCF[1:0] [11] VCEN[1:0]-bit (Sub-Address 0x0E, 0x26[3:2]) VCEN[1:0]-bit [00] NTSC [01] PAL [10] SECAM [11] Reserved VLF-bit 1 (Sub-Address 0x0E, 0x26[4]) VLF-bit (Lines) [0] 525 NTSC-M,J, NTSC-4.43, PAL-M, PAL-60 [1] 625 PAL-B,D,G,H,I,N,Nc, SECAM BW-bit (Sub-Address 0x0E, 0x26[5]) BW-bit [0] ( OFF) [1] ( ON) AD YC Cb/Cr 0x80(601 ) S(Y/C) SETUP-bit Setup SETUP-bit SETUP [0] Setup [1] Setup 7.5IRE Setup Setup : Y=(Y 7.5)/0.925 : U=U/0.925, V=V/0.925 (Sub-Address 0x0E, 0x26[6]) -49-
[6.5.] AUTODET-bit (Sub-Address 0x0E, 0x26[7]) AUTODET-bit [0] OFF [1] ON 525 / 625 3.57954545 3.57561149 3.58205625 4.43361875 NTSC / PAL / SECAM * / * ON(Sub-Address0x07[7]=1) AK8857 Video Status Register ( ) NTSC-M,J / NTSC-4.43 / PAL-B,D,G,H,I,N / PAL-M / PAL-Nc / PAL-60 / SECAM NTSC-M NTSC-J PAL-B,D,G,H,I,N ( ) VLOCK(Sub-Address0x03[7]=1) -50-
[6.6.] AK8857 NDMODE Register (Sub-Address 0x0F, 0x27[7:0]) Register Name R/W Definition NDPALM No Detect PAL-M bit R/W NDPALNC No Detect PAL-Nc bit R/W NDSECAM No Detect SECAM bit R/W [0] : PAL-M [1] : PAL-M [0] : PAL-Nc [1] : PAL-Nc [0] : SECAM [1] : SECAM Reserved Reserved R/W Reserved NDNTSC443 No Detect NTSC-4.43 bit R/W NDPAL60 No Detect PAL-60 bit R/W ND525L No Detect 525Line bit R/W ND625L No Detect 625Line bit R/W [0] : NTSC-4.43 [1] : NTSC-4.43 [0] : PAL-60 [1] : PAL-60 [0] : 525Line [1] : 525Line [0] : 625Line [1] : 625Line [1] NDNTSC443(bit 4) NDPAL60(bit 5) [1] [2] ND525L(bit 6) ND625L(bit 7) [1] [3] OFF ON OFF Video Standard Register NDMODE Register ON -51-
[6.7.] AK8857 601LIMIT-bit Min / Max 601LIMIT-bit MinMax [0] [1] Y: 1254 Cb, Cr: 1254 Y: 16235 Cb, Cr: 16240 (Sub-Address 0x02[3]) Min=1,Max=254 601LIMIT-bit [1] 115,236254 16,235 115,241254 16,240 TRSVSEL-bit ITU-R BT.656 EAV/SAV V-bit (Sub-Address 0x02[4]) 525 625 TRSVSEL-bit V-bit=0 V-bit=1 V-bit=0 V-bit=1 [0] ITU-R BT.656-3 [1] ITU-R BT.656-4 SMPTE125M Line10Line263 Line273Line525 Line20Line263 Line283Line525 Line1Line9 Line264Line272 Line1Line19 Line264Line282 Line23Line310 Line336Line623 Line1Line22 Line311Line335 Line624Line625 TRSVSEL ITU-R BT.601 VBIL[2:0]-bit VBIL[2:0]-bit (Sub-Address 0x02[2:0]) VBIL[2:0]-bit [000] [001] [010] [011] [100] [101] [110] [111] 1Line *1 2Line *2 2Lines *1 4Lines *2 3Lines *1 6Lines *2 4Lines *1 8Lines *2 5Lines *1 10Lines *2 6Lines *1 12Lines *2 7Lines *1 14Lines *2 *1 ITU-R BT.601, VGA, WVGA *2 ITU-R BT.601, VGA, WVGA -52-
*1 18 19 20 21 22 23 24 25 VBIL=[000] VBIL=[001] *2 18 19 20 21 22 23 24 25 VBIL=[000] VBIL=[001] SLLVL-bit SLLVL-bit [0] 25IRE [1] 50IRE (Sub-Address 0x02[5]) AK8857 YCbCr VBI ITU-R BT.601 VBI VBI 601 Cb/Cr Hi/Low Slice Data Set Register Hi Slice Data Set Register* 2 High 0xEB(235) Low Slice Data Set Register* 2 Low 0x10(16) *0x00 0xFF 601-53-
VBIDEC[1:0]-bit VBI VBIDEC[1:0]-bit [00] [01] [10] Y=0x10 Cb=Cr=0x80 [11] Reserved Reserved Y= 601 Cb=Cr=0x80 (Sub-Address 0x02[7:6]) Y=Cb=Cr= (Hi/Low Slice Data Set Register ) * (525Line ) Line1 Line9 Line263.5 Line272.5 (625Line ) Line623.5 Line6.5 Line311 Line318 VBIDEC[1:0] * (mv) NTSC/PAL 601 Code 714/700 235 100% White 357/350 127 SLLVL=[1] 50IRE 180/175 63 SLLVL=[0] 25IRE L L ```` L L H H ```` H H L L: Low Slice Data Set Register H: High Slice Data Set Register ````` Cb/Y `````` Cr/Y Cb/Y `````` Cr/Y ``````` * (mv) Cb/Y Cr/Y -54-
[6.8.] Output Pin Control Register DATA_A[7:0], _ACT_A, _ACT_A, _A, _A, NSIG_A, DATA_B[7:0], _ACT_B, _ACT_B, _B, _B, NSIG_B Low DATA_A[7:0] DATA_B[7:0] (* OE_A, OE_B, PDN, RSTN AINSEL[4:0]( ) ) [6.9.] AK8857 _ACT_A, _ACT_A, _A, _A, _ACT_B, _ACT_B, _B, _B _ACT _ACT ACTSEL-bit / ACTSEL-bit _ACT [0] [1] (Sub-Address 0x11, 0x29[4]) ACTSEL-bit / ACTSEL-bit _ACT [0] [1] (Sub-Address 0x11, 0x29[5]) DATA_A[7:0] DATA_B[7:0] DTCLK CLKINV-bit DTCLK CLKINV-bit [0] [1] (Sub-Address 0x04[5]) A B 54MHz (IP ) DTCLK 54MHz IP 2CLK -55-
CLKINV-bit A, B 27MHz 54MHz A IP A : CLKINV=[0] B : CLKINV=[0] DTCLK DATA_A[7:0] DATA_B[7:0] D0 D1 D2 D3 D4 D0 D1 D2 D3 D4 DTCLK DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8D9 DATA_B[7:0] D0 D1 D2 D3 D4 A : CLKINV=[1] B : CLKINV=[0] DTCLK DATA_A[7:0] DATA_B[7:0] D0 D1 D2 D3 D0 D1 D2 D3 D4 DTCLK DATA_A[7:0] DATA_B[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D0 D1 D2 D3 D4 A : CLKINV=[0] B : CLKINV=[1] DTCLK DATA_A[7:0] DATA_B[7:0] D0 D1 D2 D3 D4 D0 D1 D2 D3 DTCLK DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8D9 DATA_B[7:0] D0 D1 D2 D3 D4 A : CLKINV=[1] B : CLKINV=[1] DTCLK DATA_A[7:0] DATA_B[7:0] DTCLK D0 D1 D2 D3 DATA_A[7:0] D0 D1 D2 D3 DATA_B[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D0 D1 D2 D3 D4 [6.10.] AK8857 YCDELAY[2:0]-bit YC (Sub-Address 0x03[2:0]) YCDELAY[2:0]-bit [001] Y C 1 2clk [010] Y C 2 4clk [011] Y C 3 6clk [000] Y/C [101] Y C 3 6clk [110] Y C 2 4clk [111] Y C 1 2clk [100] Reserved YCDELAY[2:0] = [000] Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5 Y/C default YCDELAY[2:0] = [111] Cb0 Y857 Cr0 Y0 Cb1 Y1 Cr1 Y2 Cb2 Y3 Cr2 Y4 1 pixel delay YCDELAY[2:0] = [001] Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 Y4 Cb2 Y5 Cr2 Y6 1 pixel adv. DTCLK -56-
ACTSTA[2:0]-bit (Sub-Address 0x03[6:4]) ACTSTA[2:0]-bit [001] 1 2clk [010] 2 4clk [011] 3 6clk [000] [101] 3 6clk [110] 2 4clk [111] 1 2clk [100] Reserved * ( ) 720x487, 720x576(ITU-R BT.601) ACTSTA[2:0] =[000] 128CLK 244CLK (264CLK) 1440CLK 32CLK (24CLK) ACTSTA[2:0] =[001] 1sample (2CLK) 1sample (2CLK) [6.11.]VLOCK AK8857 524 1 524 VLOCK 1 525 524 VLOCK UnLock UnLock (Sub-address 0x19[1], 0x31[1]) VLOCK 2 PLL VLOCK -57-
VLOCK (Sub-Address 0x03[7]) VLOCKSEL-bit [0] PLL VLOCK [1] VLOCK ( ) VLOCK (Sub-Address0x0E[7]=1, 0x26[7]=1) [6.12.]Auto Gain Control (AGC) AK8857 AGC ( ) 286mV / 300mV PGA ( AGC) PGA ( AGC) NTSC-M,J, NTSC-4.43, PAL-M..286mV PAL-B,D,G,H,I,N, PAL-Nc, PAL-60, SECAM. 300mV AGCT[1:0]-bit AGC (Sub-Address 0x12, 0x2A[1:0]) AGCT[1:0]-bit [00] Disable AGC OFF PGA [01] Fast T= 1Field [10] Middle T= 7Fields [11] Slow T= 29Fields T AGC Disable PGA AGCC-bit AGC (Sub-Address 0x12, 0x2A[3:2]) AGCC[1:0]-bit [00] ±2LSB [01] ±3LSB [10] ±4LSB [11] AGCFRZ-bit AGC (Sub-Address 0x12, 0x2A[4]) AGCFRZ-bit AGC [0] [1] PGA1,2 Control Register -58-
AGCTL-bit AGC AGC (Sub-Address 0x13, 0x2B[0]) AGCTL-bit AGC [0] Quick [1] Slow [6.13.]Auto Color Control (ACC) AK8857 ACC SECAM (286mV/ 300mV) AGC NTSC-M,J, NTSC-4.43, PAL-M..286mV PAL-B,D,G,H,I,N, PAL-Nc, PAL-60. 300mV ACCT[1:0]-bit ACC (Sub-Address 0x12, 0x2A[6:5]) ACCT[1:0]-bit [00] Disable ACC OFF [01] Fast T= 2Fields [10] Middle T= 8Fields [11] Slow T= 30Fields ACCFRZ-bit ACC (Sub-Address 0x12, 0x2A[7]) ACCFRZ-bit ACC [0] [1] ACC (Satulation) ACC Enable ACC [6.14.] ( ) ( ) ( ) NSIGMD-bit (Sub-Address 0x13, 0x2B[6:5]) NSIGMD [1:0]-bit [00] [01] [10] ( ) [11] Reserved -59-
[6.15.]Y/C AK8857 2 Y/C Y/C NTSC-4.43, PAL-60, SECAM 1 Y/C YCSEP[1:0]-bit Y/C YCSEP[1:0]-bit YC [00] Y/C [01] 1 Y/C 1 (BPF)Y/C [10] 2 Y/C [11] Reserved (Sub-Address 0x04[1:0]) (NTSC-M,J, PAL-M) : 3Line2 Y/C (PAL-B,D,G,H,I,N,Nc) : 5Line2 Y/C * *NTSC-4.43, PAL-60, SECAM 1 Y/C [6.16.]C AK8857 YC C C358FIL[1:0] 3.58MHz C (Sub-Address 0x13, 0x2B[2:1]) C358FIL[1:0] -bit C [00] Narrow [01] Medium [10] Wide [11] Reserved NTSC-M, J, PAL-M, PAL-Nc -60-
C443FIL[1:0] 4.43MHz C (Sub-Address 0x13, 0x2B[4:3]) C443FIL[1:0] -bit C [00] Narrow [01] Medium [10] Wide [11] Reserved PAL-B,D,G,H,I,N, NTSC-4.43, PAL-60 *SECAM [6.17.]U/ V AK8857 C Low Pass Filter U/ V UVFILSEL-bit U/ V (Sub-Address 0x04[2]) UVFILSEL bit U/V [0] Wide [1] Narrow [6.18.] AK8857 INTPOLOFF-bit (Sub-Address 0x04[4]) INTPOLOFF-bit [0] ON [1] OFF -61-
[6.19.] AK8857 PLL 27MHz 720x487, VGA, WVGA 27MHz 54MHz [6.20.] PAL-B,D,G,H,I,N,Nc,60,M ON NTSC-M,J SECAM DPAL[1:0]-bit (Sub-Address 0x05[1:0]) DPAL[1:0]-bit [00] [01] ON [10] OFF [11] Reserved [6.21.] [6.21.1.]EAV/SAV AK8857 ITU-R BT.601 ITU-RBT.656 EAV/SAV ITU-R BT.601 EAV/SAV (4 ) V F V bit V bit EAV SAV EAV F bit F bit EVEN ODD ODD EVEN EAV SAV EAV SAV -62-
EAV/SAV DTCLK DATA [7:0] FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 FF 00 00 EAV AK8857 EAV SAV SAV EAV SAV EAVSAV-bit EAV/SAV (Sub-Address 0x04[6]) EAVSAV-bit EAV/SAV [0] [1] [6.21.2.] AK8857 < > [ ] [ ] [ ] [ ] SAV Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Y718 Cr359 Y719 FF 128CLK 244CLK (264CLK) 1440CLK 32CLK (24CLK) -63-
[6.22] Setup AK8857 Setup Setup Y=(Y 7.5)/0.925 U=U/0.925, V=V/0.925 Setup AK8857 (Sub-Address 0x05[6]) NTSC-M,J [0] PAL-B,D,G,H,I,N PAL-Nc, 60 SECAM [1] PAL-M NTSC-4.43 Setup-bit [0] [1] STUPATOFF-bit [ Setup ] Setup [0] [1] [0] [1] [0] [1] [0] [1] Setup [6.23.]PGA (Programable Gain Amp) AK8857 PGA ADC 3dB 10dB 0x1F(HEX)=0dB (Sub-Address 0x0B, 0x0C[7:0]) 0.625 G = 20log { 0.006 ( 31 PGA) } 0.625 G PGA (db) PGA PGA (Dec.) 0.5Vpp AIN PGA1[7:0]-bit PGA PGA2[7:0]-bit PGA (CVBS) PGA1 A PGA2 B S(Y/C) PGA1 PGA2 CVBS A B AIN PGA1 PGA2 AGC AGC Enable PGA[7:0]-bit AGC Disable PGA -64-
[6.24.] AK8857 10bit (ITU-R BT.601 ) 8+7LSB 1LSB 0.4LSB BKLVL[3:0]-bit BKLVL[3:0]-bit 601 (Sub-Address 0x06[3:0]) [0001] 1 0.4LSB [0010] 2 0.8LSB [0011] 3 1.2LSB [0100] 4 1.6LSB [0101] 5 2.0LSB [0110] 6 2.4LSB [0111] 7 2.8LSB [0000] [1000] 8 3.2LSB [1001] 7 2.8LSB [1010] 6 2.4LSB [1011] 5 2.0LSB [1100] 4 1.6LSB [1101] 3 1.2LSB [1110] 2 0.8LSB [1111] 1 0.4LSB 2 [6.25.] (286mV/300mV) 16(8-Bit, ITU-R BT.601 ) DPCT[1:0]-bit (Sub-Address 0x06[5:4]) DPCT[1:0]-bit [00] Fast [01] Middle [10] Slow [11] Disable OFF -65-
DPCC[1:0]-bit (Coring Level) (Sub-Address 0x06[7:6]) DPCC[1:0]-bit [00] ±1bit [01] ±2bit [10] ±3bit [11] [6.26.] AK8857 { I_ICKLVL[3:0] << 2} + 24 << 2 2bit CKLVL[3:0]-bit [1000] 23dB (Sub-Address 0x07[3:0]) CLKVL [3:0] NTSC PAL % db % db [0000] 24 3.3 29.7 3.1 30.2 [0001] 28 3.8 28.4 3.6 28.9 [0010] 32 4.3 27.2 4.1 27.7 [0011] 36 4.9 26.2 4.6 26.7 [0100] 40 5.4 25.3 5.2 25.8 [0101] 44 6.0 24.5 5.7 24.9 [0110] 48 6.5 23.7 6.2 24.2 [0111] 52 7.1 23.0 6.7 23.5 [1000] 56 7.6 22.4 7.2 22.8 [1001] 60 8.1 21.8 7.7 22.2 [1010] 64 8.7 21.2 8.3 21.7 [1011] 68 9.2 20.7 8.8 21.1 [1100] 72 9.8 20.2 9.3 20.6 [1101] 76 10.3 19.7 9.8 20.2 [1110] 80 10.9 19.3 10.3 19.7 [1111] 84 11.4 18.9 10.8 19.3 AK8857 Cb/Cr 0x80 PLL COLKILL-bit ON/OFF ON COLKILL-bit [0] Enable [1] Disable (Sub-Address 0x07[7]) -66-
CKSCM[1:0]-bit SECAM (Sub-Address 0x07[5:4]) CKSCM [1:0] SECAM [00] {CKLVL [3:0]} [01] {0, CKLVL [3:1]} 1bit [10] {0,0, CKLVL [3:2]} 2bit [11] Reserved CKILSEL (Sub-Address 0x05[7]) CKILSEL-bit [0] CKLVL[3:0]-bit [1] CKLVL[3:0]-bit PLL * *SECAM PLL CKILSEL ON/OFF -67-
[6.27.] AK8857 [6.27.1.] CONT[7:0]-bit: (0x80) Contrast Control Register (Sub-Address 0x14, 0x2C[7:0]) CONTSEL=[0] YOUT = (CONT / 128) x (YIN 128) + 128 CONTSEL=[1] YOUT = (CONT / 128) x YIN YOUT : YIN : CONT : ( ) 0255 [254]/ [1] ( 601LIMIT [1] 16-235 ) CONTSEL-bit CONTSEL -bit [0] 128 [1] 0 (Sub-Address 0x07[6]) [6.27.2.] BR[7:0]-bit 2 (0x00) ITU-R BT.601 8Bit ( )(Sub-Address 0x15, 0x2D[7:0]) YOUT = YIN+BR YOUT YIN BR ( ) 127+127(1step) 2 [254]/ [1] ( 601LIMIT [1] 16-235 ) -68-
[6.27.3.] (Saturation) SAT[7:0]-bit : (0x80) 0255/128(1/128steps) (Sub-Address 0x16, 0x2E[7:0]) [6.27.4.] (HUE) HUE[7:0]-bit: 2 (0x00) ±45 ( 0.35 steps) (Sub-Address 0x17, 0x2F[7:0]) [6.27.5.] AK8857 SHARP[1:0]-bits SHCORE[1:0]-bits Filter Coring Delay SHARP[1:0]-bit (Sub-Address 0x08[1:0]) SHARP[1:0]-bit [00] [01] Min [10] Middle [11] Max SHCORE[1:0]-bit (Sub-Address 0x08[3:2]) SHCORE[1:0]-bit [00] [01] ±1LSB [10] ±2LSB [11] ±3LSB -69-
VBIIMGCTL-bit VBI ON/OFF (Sub-Address 0x08[7]) VBIIMGCTL bit VBI [0] [1] [6.27.6.] MPEG LUMFIL[1:0]-bit LUMFIL [1:0]-bit [00] [01] Narrow 3dB at 2.94MHz [10] Mid 3dB at 3.30MHz [11] Wide 3dB at 4.00MHz (Sub-Address 0x08[5:4]) 3dB at 6.29MHz [6.27.7.] AK8857 SEPIA-bit SEPIA bit [0] [1] (Sub-Address 0x08[6]) -70-
[6.28.]VBI Information AK8857 VBI Closed Caption Data, Closed Caption Extended Data,VBID(CGMS), WSS Request VBI Information Register(R/W)-[3:0] (Sub-Address 0x18, 0x30[3:0]) AK8857 Status 2 Register(R)-[3:0] (Sub-Address 0x1A, 0x32[3:0]) VBID (CGMS-A) CRCC Closed Caption Line21 525-Line Closed Caption Extended Data Line284 525-Line VBID Line20 / 283 Line20 / 333 525-Line 625-Line WSS Line23 625-Line (Sub-Address 0x1D0x24, 0x350x3C) Closed Caption 1 Register, Closed Caption 2 Register WSS 1 Register, WSS 2 Register Extended Data 1 Register, Extended Data 2 Register VBID 1 Register, VBID 2 Register Start Request VBI Info Register xxrq-bit = 1 ( Closed Caption CCRQ-bit Closed Caption Extended EXTRQ-bit VBID/WSS VBWSRQ-bit Status Register Read Request = 1 Yes No Closed Caption CCDET-bit Closed Caption Extended EXTDET-bit VBID/WSS VBWSDET-bit Closed Caption Closed Caption 1 2 Register Closed Caption Extended Extended Data 1 2 Register VBID/WSS VBID/WSS 1 2 Register -71-
[6.29.] NOSIG-bit NOSIG bit [0] [1] (Sub-Address 0x19, 0x31[0]) VLOCK-bit VLOCK VLOCK-bit [0] [1] (Sub-Address 0x19, 0x31[1]) COLKILON COLKILON bit [0] [1] (Sub-Address 0x19, 0x31[3]) CPLL-bit PLL (Sub-Address 0x19, 0x31[4]) CPLL bit [00] [01] PKWHITE AGC (Sub-Address 0x19, 0x31[6]) PKWHITE bit [0] [1] OVCOL ACC (Sub-Address 0x19, 0x31[7]) OVCOL bit [0] [1] REALFLD-bit AK8857 (Sub-Address 0x1A, 0x32[4]) REALFLD bit [0] Even [1] Odd AGCSTS-bit AGC AGCSTS bit [0] AGC [1] AGC (Sub-Address 0x1A, 0x32[5]) -72-
[6.30.] Video Status-Register (Sub-Address 0x1C, 0x34) Bit bit 0 bit 1 bit 2 bit 3 bit 4 Register Name ST_VSF0 ST_VSF1 ST_VCEN0 ST_VCEN1 ST_VLF Status of Video Sub-Carrier Frequency Status of Video Color Encode Status of Video Line Frequency bit 5 ST_BW Status of B/W Signal R bit 6 UNDEF Un_define bit R bit 7 FIXED Video Standard fixed bit R/W R R R R Definition [ ST_VSF1 : ST_VSF0 ] ( MHz ) [00] : 3.57954545 (NTSC-M,J) [01] : 3.57561149 (PAL-M) [10] : 3.58205625 (PAL-Nc) [11] : 4.43361875 (PAL-B,D,G,H,I,N,60, NTSC-4.43) [ST_VCEN1 : ST_VCEN0] [00] : NTSC [01] : PAL [10] : SECAM [11] : Reserved [0]: 525 (NTSC-M,J, 4.43, PAL-M,60) [1]: 625 (PAL-B,D,G,H,I,N,Nc, SECAM) * [0] : [1] : [0]: [1]: [0]: [1]: * ON(COLKILL-bit = [1]) ST_BW-bit [1] B/W-bit 525/625 ST_VLF -73-
[7.] AK8857 I2C [7.1.] I2C SLAVE Address I2C SELA [1000100] [1000101] Slave Address SELA MSB LSB [Low] 1 0 0 0 1 0 0 R/W [High] 1 0 0 0 1 0 1 R/W [7.2.] I2C [7.2.1.] Write 1 AK8857 2 3 Write 1 Write Write Sequential Write operation (a) 1 Write S Slave Address w A Sub Address A Data A Stp 8-bit 1- bit 8-bit 1- bit 8-bit 1- bit (b) (m-bytes) Write (Sequential Write Operation) S Slave Address w A Sub Address(n) A Data(n) A Data A (n+1) 1-1- 1-1- 8-bit 8-bit 8-bit 8-bit bit bit bit bit Data (n+m) 8-bit A 1- bit stp [7.2.2.] Read 1 AK8857 2 S Slave Address w A Sub Address(n) A rs Slave Address R A Data1 A Data2 A Data3 A 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 Data n!a stp 8-bit 1 S : Start Condition rs : repeated Start Condition A : Acknowledge (SDA Low )!A : Not Acknowledge (SDA High) stp : Stop Condition R/W 1 : Read 0 : Write : : AK8857-74-
[8.] Sub Address Default R/W 0x00 Channel Select 0x00 R/W 0x01 AFE Control 0x01 R/W 0x02 Output Control 0x00 R/W 0x03 Start and Delay Control 0x00 R/W 0x04 Control 1 0x00 R/W 0x05 Control 2 0x00 R/W 0x06 Pedestal Level Control 0x00 R/W 0x07 Color Killer Control 0x08 R/W 0x08 Image Control 0x00 R/W 0x09 High Slice Data Set 0xEB R/W VBI High 0x0A Low Slice Data Set 0x10 R/W VBI Low 0x0B PGA Control 1 0x3E R/W PGA1 0x0C PGA Control 2 0x3E R/W PGA2 0x0D Output Data Format A 0x00 R/W A 0x0E Video Standard A 0x00 R/W A 0x0F NDMODE A 0x00 R/W A 0x10 Output Pin Control 0 A 0x00 R/W A 0x11 Output Pin Control 1 A 0x00 R/W A 0x12 AGC & ACC A Control 0x00 R/W A AGC ACC 0x13 Control 0 A 0x00 R/W A 0x14 Contrast Control A 0x80 R/W A 0x15 Brightness Control A 0x00 R/W A 0x16 Saturation Control A 0x80 R/W A 0x17 HUE Control A 0x00 R/W A HUE( ) 0x18 Request VBI Infomation A 0x00 R/W A VBI 0x19 Status 1 A R A 0x1A Status 2 A R A 0x1B Reserved R A Reserved 0x1C Video Status A R A 0x1D Closed Caption 1 A R A Closed Caption 0x1E Closed Caption 2 A R A Closed Caption 0x1F WSS 1 A R A WSS 0x20 WSS 2 A R A WSS 0x21 Extended Data 1 A R A CC-Extended 0x22 Extended Data 2 A R A CC-Extended -75-
Sub Address Default R/W 0x23 VBID 1 A R A VBID 0x24 VBID 2 A R A VBID 0x25 Output Data Format A 0x00 R/W B 0x26 Video Standard B 0x00 R/W B 0x27 NDMODE B 0x00 R/W B 0x28 Output Pin Control 0 B 0x00 R/W B 0x29 Output Pin Control 1 B 0x00 R/W B 0x2A AGC & ACC B Control 0x00 R/W B AGC ACC 0x2B Control 0 B 0x00 R/W B 0x2C Contrast Control B 0x80 R/W B 0x2D Brightness Control B 0x00 R/W B 0x2E Saturation Control B 0x80 R/W B 0x2F HUE Control B 0x00 R/W B HUE( ) 0x30 Request VBI Infomation B 0x00 R/W B VBI 0x31 Status 1 B R B 0x32 Status 2 B R B 0x33 Reserved R B Reserved 0x34 Video Status B R B 0x35 Closed Caption 1 B R B Closed Caption 0x36 Closed Caption 2 B R B Closed Caption 0x37 WSS 1 B R B WSS 0x38 WSS 2 B R B WSS 0x39 Extended Data 1 B R B CC-Extended 0x3A Extended Data 2 B R B CC-Extended 0x3B VBID 1 B R B VBID 0x3C VBID 2 B R B VBID 0x3D Device and Revision ID 0x39 R Device ID Revision Default Sub-address 0x00 REGSEL A B R/W [ Channel Select], [PGA Control 1], [PGA Control 2], [Device and Revision ID] REGSEL A A B B -76-
[9.] [9.1.] Channel Select Register (R/W) [Sub Address 0x00] Sub Address 0x00 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P1DRV1 P1DRV0 REGSEL AINSEL4 AINSEL3 AINSEL2 AINSEL1 AINSEL0 Default Value 0 0 0 0 0 0 0 0 Channel Select Register Definition Register bit R / W Definition Name bit 0 bit 4 AINSEL0 AINSEL4 Analog Select R / W A B [AINSEL4: AINSEL0] [00000]: [A]: AIN1(CVBS), [B]: AIN4(CVBS) [00001]: [A]: AIN1(CVBS), [B]: AIN3(CVBS) [00010]: [A]: AIN1(CVBS), [B]: AIN2(CVBS) [00011]: [A]: AIN1(CVBS), [B]: AIN1(CVBS) (*2) [00100]: [A]: AIN1(CVBS), [B]: (*1) [00101]: [A]: AIN2(CVBS), [B]: AIN4(CVBS) [00110]: [A]: AIN2(CVBS), [B]: AIN3(CVBS) [00111]: [A]: AIN2(CVBS), [B]: AIN2(CVBS) (*2) [01000]: [A]: AIN2(CVBS), [B]: AIN1(CVBS) [01001]: [A]: AIN2(CVBS), [B]: (*1) [01010]: [A]: AIN3(CVBS), [B]: AIN4(CVBS) [01011]: [A]: AIN3(CVBS), [B]: AIN3(CVBS) (*2) [01100]: [A]: AIN3(CVBS), [B]: AIN2(CVBS) [01101]: [A]: AIN3(CVBS), [B]: AIN1(CVBS) [01110]: [A]: AIN3(CVBS), [B]: (*1) [01111]: [A]: AIN4(CVBS), [B]: AIN4(CVBS) (*2) [10000]: [A]: AIN4(CVBS), [B]: AIN3(CVBS) [10001]: [A]: AIN4(CVBS), [B]: AIN2(CVBS) [10010]: [A]: AIN4(CVBS), [B]: AIN1(CVBS) [10011]: [A]: AIN4(CVBS), [B]: (*1) [10100]: [A]:, [B]: AIN4(CVBS) (*1) [10101]: [A]:, [B]: AIN3(CVBS) (*1) [10110]: [A]:, [B]: AIN2(CVBS) (*1) [10111]: [A]:, [B]: AIN1(CVBS) (*1) [11000]: [A]: AIN1(Y) / AIN3(C), [B]: (*1, *2) [11001]: [A]: AIN1(Y) / AIN3(C), [B]: AIN1(Y) / AIN3(C) (*1, *2) [11010]: [A]: AIN2(Y) / AIN4(C), [B]: (*1, *2) [11011]: [A]: AIN2(Y) / AIN4(C), [B]: AIN2(Y) / AIN4(C) (*1, *2) [11100]: [A]:, [B]: AIN1(Y) / AIN3(C) (*1, *2) [11101]: [A]:, [B]: AIN2(Y) / AIN4(C) (*1, *2) [11110],[11111]: Reserved -77-
bit 5 REGSEL Register Select R / W (*2) [0]: A Write/ Read [1]: B Write/ Read bit 6 bit 7 P1DRV0 P1DRV1 PD1 Drive R / W P1 PD1 (*3) [P1DRV1: P1DRV0] [00]: PD1 = 3.0 3.6V [01]: PD1 = 2.3 2.7V [10]: Reserved [11]: PD1 = 1.7 2.0V (*1) (*2) A B Sub-address0x01[AFE ControlRegister] REGSEL=[0] REGSEL=[1] S(Y/C) REGSEL=[0] REGSEL=[1] (*3) P1, DATA_A[7:0], _ACT_A, _ACT_A, _A, _A, DATA_B[7:0], _ACT_B, _ACT_B, _B, _B, DTCLK -78-
[9.2.] AFE Control Register (R/W) [Sub Address 0x01] ( ) 0x00 REGSEL R / W Sub Address 0x01 Default Value: 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CLPWIDTH1 CLPWIDTH0 CLPSTAT1 CLPSTAT0 UDG1 UDG0 CLPG1 CLPG0 Default Value 0 0 0 0 0 0 0 1 AFE Control Register Definition bit Register Name R / W Definition bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 CLPG 0 CLPG1 UDG 0 UDG 1 CLPSTAT0 CLPSTAT1 CLPWIDTH0 CLPWIDTH1 Clamp Gain Up Down Gain Clamp Start Clamp Pulse Width R / W R / W R / W R / W [00]: Min. [01]: Middle 1 [ = (Min. x 3 ) ] (Default) [10]: Middle 2 [ = (Min. x 5 ) ] [11]: Max. [ = (Min. x 7 ) ] [00]: Min. (Default) [01]: Middle 1 [ = (Min. x 2 ) ] [10]: Middle 2 [ = (Min. x 3 ) ] [11]: Max. [ = (Min. x 4 ) ] [ CLPSTAT1 : CLPSTAT0 ] [00]: [01]: (1/128)H [10]: (2/128)H [11]: (1/128H) [ CLPWIDTH1 : CLPWIDTH0 ] [00]: 296nsec [01]: 593nsec [10]: 1.1usec [11]: 2.2usec -79-
[9.3.] Output Control Register (R/W) [Sub Address 0x02] ( ) 0x00 REGSEL R / W Sub Address 0x02 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 VBIDEC1 VBIDEC0 SLLVL TRSVSEL 601LIMIT VBIL2 VBIL1 VBIL0 Default Value 0 0 0 0 0 0 0 0 Output Control Register Definition bit Register Name R/W Definition bit 0 bit 2 VBIL0 VBIL2 Vertical Blanking Length R/W bit 3 601LIMIT 601 Output Limit R/W bit 4 TRSVSEL Time Reference Signal V Select R/W * [ VBIL2 : VBIL0 ] [000]: [001]: 1Line (2Line*) [010]: 2Line (4Line*) [011]: 3Line (6Line*) [100]: 4Line (8Line*) [101]: 5Line (10Line*) [110]: 6Line (12Line*) [111]: 7Line (14Line*) Min - Max [0]: 1-254 (Y/Cb/Cr) [1]: 16-235 (Y) / 16-240 (Cb/Cr) 1 16 16 235 / 240 (Y / Cb,Cr) 240 ITU-R BT.656 Timing reference signals V-bit 525LINE [0]: V=1 (Line1 Line9 / Line264 Line272) V=0(Line10 Line263 / Line273 Line525) [1]: V=1 (Line1 Line19 / Line264 Line282) V=0 (Line20 Line263 / Line283 Line525) 625LINE bit 5 SLLVL Slice Level R/W [0]: 25IRE [1]: 50IRE bit 6 bit 7 VBIDEC0 VBIDEC1 VBI Decode R/W Vertical Blanking Length [ VBIDEC1 : VBIDEC0 ] [00]: [01]: [10]: [11]: Reserved *ITU-R BT.601, VGA, WVGA -80-
[9.4.] Start and Delay Control Register (R/W) [Sub Address 0x03] ( ) 0x00 REGSEL R / W Sub Address 0x03 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 VLOCKSEL ACTSTA2 ACTSTA1 ACTSTA0 Reserved YCDELAY2 YCDELAY1 YCDELAY0 Default Value 0 0 0 0 0 0 0 0 Start and Delay Control Register Definition bit Register Name R/W Definition bit 0 bit 2 YCDELAY0 YCDELAY2 Y/C Delay Control R/W bit 3 Reserved Reserved R/W Reserved bit 4 bit 6 ACTSTA0 ACTSTA2 Active Video Start Control R/W bit 7 VLOCKSEL Vlock Select R/W Y / C [ YCDELAY2: YCDELAY0 ] [001]: Y C 1 [010]: Y C 2 [011]: Y C 3 [000]: Y/C [101]: Y C 3 [110]: Y C 2 [111]: Y C 1 [100]: Reserved [ ACTSTA2 : ACTSTA0 ] [001] : 1 [010] : 2 [011] : 3 [000] : [101] : 3 [110] : 2 [111] : 1 [100] : Reserved [0]: PLL VLOCK [1]: VLOCK* * VLOCK (Sub-Address0x0E[7]=1 Sub-Address0x26[7]=1) -81-
[9.5.] Control 1 Register (R/W) [Sub Address 0x04] ( ) 0x00 REGSEL R / W Sub Address 0x04 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved EAVSAV CLKINV INTPOLOFF Reserved UVFILSEL YCSEP1 YCSEP0 Default Value 0 0 0 0 0 0 0 0 Control 1 Register Definition bit Register Name R/W Definition bit 0 bit 1 YCSEP0 YCSEP1 YC Separation Control R/W YC [ YCSEP1 : YCSEP0 ] [00]: YC [01]: 1 YC [10]: 2 YC [11]: Reserved bit 2 UVFILSEL UV Filter Select R/W UV [0]: Wide [1]: Narrow bit 3 Reserved Reserved R/W Reserved bit 4 INTPOLOFF Interpolator Mode Select R/W bit 5 CLKINV CLK Invert Set R/W bit 6 EAVSAV EAV/ SAV SELECT R/W bit 7 Reserved Reserved R/W Reserved [0]: ON [1]: OFF DTCLK [0]: [1]: EAV/SAV [0]: [1]: -82-
[9.6.] Control 2 Register (R/W) [Sub Address 0x05] ( ) 0x00 REGSEL R / W Sub Address 0x05 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CKILSEL STUPATOFF Reserved Reserved Reserved Reserved DPAL1 DPAL0 Default Value 0 0 0 0 0 0 0 0 Control 2 Register Definition bit Register Name R/W Definition bit 0 bit 1 bit 2 bit 5 DPAL0 DPAL1 Deluxe PAL R/W Reserved Reserved R/W Reserved bit 6 STUPATOFF Setup Auto Control Off R/W bit 7 CKILSEL Color killer Select R/W (PAL ) [ DPAL1 : DPAL0 ] [00]: ON [01]: ON [10]: OFF [11]: Reserved Setup On/Off [0]: Setup On [1]: Setup Off [0]: CKLVL[3:0]-bit [1]: CKLVL[3:0]-bit PLL -83-
[9.7.] Pedestal Level Control Register (R/W) [Sub Address 0x06] ( ) 0x00 REGSEL R / W Sub Address 0x06 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DPCC1 DPCC0 DPCT1 DPCT0 BKLVL3 BKLVL2 BKLVL1 BKLVL0 Default Value 0 0 0 0 0 0 0 0 Pedestal Level Control Register Definition bit Register Name R/W Definition bit 0 bit 3 bit 4 bit 5 bit 6 bit 7 BKLVL0 BKLVL3 DPCT0 DPCT1 DPCC0 DPCC1 Black Level Digital Pedestal Clamp Control Digital Pedestal Clamp Coring Control R/W R/W R/W [ BKLVL3 : BKLVL0 ] [0001]: 1 [0010]: 2 [0011]: 3 [0100]: 4 [0101]: 5 [0110]: 6 [0111]: 7 [0000]: [1000]: 8 [1001]: 7 [1010]: 6 [1011]: 5 [1100]: 4 [1101]: 3 [1110]: 2 [1111]: 1 [ DPCT1 : DPCT0 ] [00]: Fast [01]: Middle [10]: Slow [11]: Disable [ DPCC1 : DPCC0 ] [00]: ±1bit [01]: ±2bit [10]: ±3bit [11]: -84-
[9.8.] Color Killer Control Register (R/W) [Sub Address 0x07] ( ) 0x00 REGSEL R / W Sub Address 0x07 Default Value: 0x08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 COLKILL CONTSEL CKSCM1 CKSCM0 CKLVL3 CKLVL2 CKLVL1 CKLVL0 Default Value 0 0 0 0 1 0 0 0 Color Killer Control Register Definition bit Register Name R/W Definition bit 0 bit 3 bit 4 bit 5 CKLVL0 CKLVL3 CKSCM0 CKSCM1 Color Killer Level Control R/W 23dB Color Killer Level for SECAM R/W bit 6 CONTSEL Contrast Select R/W bit 7 COLKILL Color killer Set R/W SECAM Contrast selecter [0]: 50 [1]: 0 ON / OFF [0]: Enable [1]: Disable -85-
[9.9.] Image Control Register (R/W) [Sub Address 0x08] ( ) VBI 0x00 REGSEL R / W Sub Address 0x08 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 VBIIMGCTL SEPIA LUMFIL1 LUMFIL0 SHCORE1 SHCORE0 SHARP1 SHARP0 Default Value 0 0 0 0 0 0 0 0 Image Control Register Definition bit Register Name R/W Definition bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 SHARP0 SHARP1 SHCORE0 SHCORE1 LUMFIL0 LUMFIL1 Sharpness Control Sharpness Coring Luminance Filter R/W R/W R/W bit 6 SEPIA Sepia Output R/W bit 7 VBIIMGCTL VBI Image Control R/W [ SHARP1 : SHARP0 ] [00]: [01]: Min [10]: Middle [11]: Max [ SHARP1 : SHARP0 ] [00] [ SHCORE1 : SHCORE0 ] [00]: [01]: ±1LSB [10]: ±2LSB [11]: ±3LSB [ LUMFIL1 : LUMFIL0 ] [00]: [01]: Narrow [10]: Mid [11]: Wide * [0]: [1]: VBI On/Off [0]: VBI [1]: VBI *SEPIA Sub-address 0x10 DOA Sub-address 0x28 DOB -86-
[9.10.] High Slice Data Set Register (R/W) [Sub Address 0x09] ( ) VBI High 0x00 REGSEL R / W 100% (235) Sub Address 0x09 Default Value: 0xEB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 H7 H6 H5 H4 H3 H2 H1 H0 Default Value 1 1 1 0 1 0 1 1 High Slice Data Set Register Definition bit Register Name R/W Definition bit 0 bit 7 H0 H7 High Data 07 Set R/W VBI High 0x00 0xFF 601 [9.11.] Low Slice Data Set Register (R/W) [Sub Address 0x0A] ( ) VBI Low 0x00 REGSEL R / W (16) Sub Address 0x0A Default Value: 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 L7 L 6 L 5 L 4 L 3 L 2 L 1 L 0 Default Value 0 0 0 1 0 0 0 0 Low Slice Data Set Register Definition bit Register Name R/W Definition bit 0 bit 7 L0 L7 Low Data 07 Set R/W VBI Low 0x00 0xFF 601-87-
[9.12.] PGA Control 1 Register (R/W) [Sub Address 0x0B] PGA 1 (CVBS) A S(Y/C) Y Sub Address 0x0B Default Value: 0x1F bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PGA1_7 PGA1_6 PGA1_5 PGA1_4 PGA1_3 PGA1_2 PGA1_1 PGA1_0 Default Value 0 0 0 1 1 1 1 1 PGA Control 1 Register Definition bit Register Name R/W Definition bit 0 bit 7 PGA1_0 PGA1_7 PGA1 Gain Set R/W PGA1 CVBS A B PGA1 PGA2 CVBS 0x00 [9.13.] PGA Control 2 Register (R/W) [Sub Address 0x0C] PGA2 (CVBS) B S(Y/C) C Sub Address 0x0C Default Value: 0x1F bit 7 Bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PGA2_7 PGA2_6 PGA2_5 PGA2_4 PGA2_3 PGA2_2 PGA2_1 PGA2_0 Default Value 0 0 0 1 1 1 1 1 PGA Control 2 Register Definition bit Register Name R/W Definition bit 0 bit 7 PGA2_0 PGA2_7 PGA2 Gain Set R/W PGA2 CVBS A B PGA1 PGA2 CVBS 0x00-88-