PGA116 PGA112 PGA113 PGA117 PGA112, PGA113 PGA116, PGA117 www.tij.co.jp µµ µµ ± µ +5V +3V AV DD 1 C BYPASS.1µF DV DD C BYPASS.1µF C BYPASS.1µF V CAL/CH CH1 3 2 1kΩ MUX CAL1 PGA112 PGA113 R F 1 Output Stage 5 V OUT MSP43 Microcontroller ADC 8kΩ.9V CAL.1V CAL CAL2 CAL3 CAL4 V REF R I 7 SCLK 1kΩ CAL2/3 SPI Interface 8 9 DIO CS 6 GND V REF 4
± 2
Ω V OS ± ± 5 ± < < ± ± ± 1.2 ± ± µ µ µ µ µ µ µ µ Ω Ω Ω 3
Ω ± ± µ µ µ µ µ µ µ 4
Ω θ MSOP-1 µ µ µ µ µ V OUT µ µ µ µ µ µ Ω µ µ µ µ µ CHx (Input) Mux Switch R SW R AMP C CH C AMP V OUT Break-Before-Make R F R I V REF 5
Ω µ 6
t CSH CS t CSSC t LO t SCCS t CS1 t CS t HI SCLK 1/f SCLK t SU t HD DIN t DO t SOZ DOUT Hi-Z Hi-Z t CSH CS t CSSC thi tlo t SCCS t CS1 t CS SCLK t SU t HD 1/f SCLK DIN t DO t SOZ DOUT Hi-Z Hi-Z 7
AV DD 1 1 DV DD CH1 V CAL /CH 2 3 PGA112 PGA113 9 8 CS DIO V REF 4 7 SCLK V OUT 5 6 GND Ω µ µ 8
AV DD 1 2 CH6 CH5 2 19 DV DD CH4 3 18 CS CH3 4 17 DOUT CH2 5 PGA116 PGA117 16 DIN CH1 6 15 SCLK V CAL /CH 7 14 GND V REF 8 13 ENABLE V OUT 9 12 CH9 CH7 1 11 CH8 Ω µ µ µ 9
+5V +3V AV DD 1 C BYPASS.1µF DV DD C BYPASS.1µF C BYPASS.1µF V CAL /CH CH1 3 2 1kΩ 8kΩ.9V CAL.1V CAL MUX CAL1 CAL2 CAL3 CAL4 V REF PGA112 PGA113 R F R I 1 Output Stage 5 7 V OUT SCLK MSP43 Microcontroller ADC 1kΩ CAL2/3 SPI Interface 8 9 DIO CS 6 GND V REF 4 +5V AV DD 1 C BYPASS.1µF V CAL /CH CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 7 6 5 4 3 2 2 1 11 12 1kΩ 8kΩ MUX CAL1.9V CAL CAL2.1V CAL CAL3 CAL4 1kΩ V REF CAL2/3 PGA116 PGA117 R F R I Output Stage SPI Interface 19 9 15 16 18 17 DV DD V OUT SCLK DIN CS DOUT C BYPASS.1µF ADC +3V MSP43 Microcontroller C BYPASS.1µF 14 GND V REF 8 13 ENABLE 1
Ω V CM = 2.5V V CM = 4.5V 9 1 Population Population 8 7 6 5 4 3 2 1 Offset Voltage (µv) 1 2 3 4 5 6 7 8 9 1 325. 292.5 26. 227.5 195. 162.5 13. 97.5 65. 32.5 Offset Voltage (µv) 32.5 65. 97.5 13. 162.5 195. 227.5 26. 292.5 325. V CM = 2.5V V CM = 4.5V.9.81.72.63.54.45.36.27.18.9.9.18.27.36.45.54.63.72.81.9 1.3 1.17 1.4.91.78.65.52.39.26.13.13.26.39.52.65.78.91 1.4 1.17 1.3 Population Population Offset Voltage Drift (µv/) Offset Voltage Drift (µv/) V CM = 2.5V V CM = 4.5V 1.2 1.8.96.84.72.6.48.36.24.12.12.24.36.48.6.72.84.96 1.8 1.2 1.8 1.62 1.44 1.26 1.8.9.72.54.36.18.18.36.54.72.9 1.8 1.26 1.44 1.62 1.8 Population Population Offset Voltage Drift (µv/) Offset Voltage Drift (µv/) 11
Ω Input Offset Voltage (µv) 1 8 6 4 2 2 4 6 8 1 1 2 3 4 5 Input Voltage (V) DC Output Nonlinearity Error (%FSR).1.8 AV DD = DV DD = +5V G = 2.6.4.2.2 6.4.6 28.8.1.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. V OUT (V).1.9.8.7.6.5.4.3.2.1.1.2.3.4.5.6.7.8.9.1.1.9.8.7.6.5.4.3.2.1.1.2.3.4.5.6.7.8.9.1 Population Population Gain Error (%) Gain Error (%).1.9.8.7.6.5.4.3.2.1.1.2.3.4.5.6.7.8.9.1.5.1.15.2.25.3.35.4.45.5.55.6.65.7.75.8.85.9.95 1. Population Population Gain Error (%) Gain Error (%) 12
Ω 1 < G 32 G 5 Population Population Gain Error Drift (ppm/) Gain Error Drift (ppm/) Population Population Gain Error (%) Gain Error (%) 2. 1.8 1.6 1.4 1.2 1..8.6.4.2.2.4.6.8 1. 1.2 1.4 1.6 1.8 2. 2. 1.8 1.6 1.4 1.2 1..8.6.4.2.2.4.6.8 1. 1.2 1.4 1.6 1.8 2. > 2. Population Population.1.9.8.7.6.5.4.3.2.1.1.2.3.4.5.6.7.8.9.1.1.9.8.7.6.5.4.3.2.1.1.2.3.4.5.6.7.8.9.1.25.5.75 1. 1.25 1.5 1.75 2. 2.25 2.5 2.75 3. 3.25 3.5 3.75 4. 4.25 4.5 4.75 5..5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 6. 6.5 7. 7.5 8. 8.5 9. 9.5 1. Gain Error Drift (ppm/) Gain Error Drift (ppm/) 13
Ω V S = 2.2V V S = 5V 25nV/div 1nV/div 2.5s/div 2.5s/div 1 1k 1 28 G = 64 G = 32 6 Voltage Noise (nv/ Hz) Current Noise, V S = 5V 5 Voltage Noise, V S = 2.2V 2 Voltage Noise, V S = 5V 5 2 1 1 1 1 1 1k 1k 1k Frequency (Hz) Current Noise (fa/ Hz) THD+N (%).1.1.1 G = 2 G = 4 G = 8.1 1 1 1k 1k 1k Frequency (Hz) 1 1.1 28 G = 64 G = 32 6.1 G = 2 G = 5 G = 2 THD+N (%).1 THD+N (%).1 G = 8.1 G = 2 G = 4.1 1 1 1k 1k 1k Frequency (Hz).1 G = 2 G = 5.1 1 1 1k 1k 1k Frequency (Hz) 14
Ω 1.8 THD+N (%) G = 2 G = 5 G = 2.1.1.1 G = 2 G = 5.1 1 1 1k 1k 1k Frequency (Hz) I Q (ma).7.6 Digital.5.4.3 Analog.2 V S = 5.5V.1 V S = 2.2V f SCLK = 1MHz 5 25 25 5 75 1 1k 125 Temperature () I QA + I QD (ma) 1.2 1..8.6.4.2 SCLK = 5MHz SCLK = 1MHz SCLK = 5kHz SCLK = 2MHz Shutdown I Q (µa) 4. 3.5 3. 2.5 2. 1.5 1..5 Digital Analog 2. 2.5 3. 3.5 4. 4.5 5. 5.5 Supply Voltage (V) 5 25 25 5 75 1 125 Temperature () Output Voltage (V) 2.2 2. 1.8 1.6 1.4 1.2 1..8.6.4.2 +125 C +25 C 4 C 2 4 6 8 1 12 14 16 18 2 22 24 Output Current (ma) 5.5 V S = 2.2V V 5. S = 5.5V 4.5 4. 3.5 +125 3. +25 2.5 2. 4 1.5 1..5 Output Voltage (V) 1 2 3 4 5 6 7 8 9 1 Output Current (ma) 15
Ω 2.5 AV DD = DV DD = 2.2V G = 4 2.5 AV DD = DV DD = 2.2V Output Voltage (V) 2. G = 8 1.5 G = 2 1..5 1k 1k 1k 1M 1M Output Voltage (V) 2. 1.5 6 G = 64 1. G = 32.5 28 1k 1k 1k 1M 1M Frequency (Hz) Frequency (Hz) Output Voltage (V) 6 5 4 3 2 G = 2 G = 8 G = 4 Output Voltage (V) 6 5 4 3 2 6 G = 32 G = 64 1 AV DD = DV DD = 5.5V 1 1k 1k 1k 1M 1M 1 AV DD = DV DD = 5.5V 28 1 1k 1k 1k 1M 1M Frequency (Hz) Frequency (Hz) 2.5 2.5 Output Voltage (V) 2. 1.5 1. G = 2 Output Voltage (V) 2. 1.5 1. G = 2 G = 2 G = 5.5 G = 5.5 AV DD = DV DD = 2.2V 1k 1k 1k 1M 1M Frequency (Hz) AV DD = DVDD 1k 1k 1k 1M 1M Frequency (Hz) 16
Ω 6 6 5 5 G = 5 Output Voltage (V) 4 G = 5 3 2 1 AV DD = DV DD = 5.5V G = 2 1 1k 1k 1k 1M 1M Output Voltage (V) 4 3 2 G = 2 1 G = 2 AV DD = DV DD = 5.5V 1 1k 1k 1k 1M 1M Frequency (Hz) Frequency (Hz) Overshoot (%) 5 4 3 2 G 2 Settling Time (µs) 12 1 8 6 4 C L = 1pF/R L = 1kΩ V OUT = 4V PP.1%.1% 1 2 1 2 3 4 5 6 7 8 Load Capacitance (pf) 5 1 15 2 Gain Input On-Channel Current (na) 5 4 3 2 1 12 CH1 5 25 25 5 75 1 125 5 25 CH CH CH1 25 5 75 1 125 Temperature () Temperature () Input Off-Channel Leakage Current (na) 1 8 6 4 2 17
Ω PSRR (db) 11 1 9 8 G 2 G = 5 7 G = 2 6 5 4 3 G = 2 2 1.1 1 1 1 1k 1k 1k 1M 1M Frequency (Hz) Crosstalk (db) 14 13 12 11 1 9 8 7 6 1 1 1k 1k 1k 1M 1M Frequency (Hz) 1mV G = 2 1mV G = 5 V Output V Output, 2 V IN /G V IN /G V Input V Input 2.5µs/div 2.5µs/div G = 2 G = 5 2V/div Output 2V/div Output, 2 Input Input 2.5µs/div 2.5µs/div 18
Ω V IN Output (1V/div) 5V V 1V/div V OUT V Supply (5V/div) V V S = 5V R L = 1kΩ C L = 1pF 2.5µs/div 1ms/div Active In Shutdown In Shutdown Active 2V/div Output Output CS CS 1µs/div 19
CS SCLK SPI Mode, (CPOL =, CPHA = ) 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 DIN DOUT CS SCLK SPI Mode 1, 1 (CPOL = 1, CPHA = 1) 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 DIN DOUT (1) (2) µ PGA116 PGA117 1µ A DOUT DOUT DIN DIO PGA112 PGA113 DIN 1µA 2
DIO Pin DIO Pin DIO Pin DIO Pin CS SCLK DIN DOUT CS SCLK DIN DOUT CS SCLK DIN DOUT CS SCLK DIN DOUT SPI Write, Mode =, 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Hi-Z SPI Write, Mode = 1, 1 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Hi-Z SPI Read, Mode =, 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 1 1 1 1 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Hi-Z SPI Read, Mode = 1, 1 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 1 1 1 1 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Hi-Z 17 18 19 2 21 22 23 24 25 26 27 28 29 3 31 32 D15 D14 D13 D12 D11 D1 D9 D8 G3 G2 G1 G CH3 CH2 CH1 CH D7 D6 D5 D4 D3 D2 D1 D 17 18 19 2 21 22 23 24 25 26 27 28 29 3 31 32 D15 D14 D13 D12 D11 D1 D9 D8 G3 G2 G1 G CH3 CH2 CH1 CH D7 D6 D5 D4 D3 D2 D1 D Hi-Z Hi-Z 21
22
Input Offset Voltage (µv) 8 7 6 5 4 3 2 AV DD V IN+ GND Reference Current V IN 1 AV DD = 5V 1 2 3 4 5 6 Input Voltage (V) 23
V OUT CH PGA112 CH1 MUX PGA113 R I V IN VIN1 V REF R F V S /2 + 5 4 AV DD = 5V Input Offset Voltage (µv) 3 2 1 1 2 3 1 2 3 4 5 6 Input Voltage (V) Ω Ω Ω Ω CH1 PGA112 PGA113 R I V OUT V IN V REF R F 24
µπ µ µ µπ π Ω Ω Ω µ µ µ µ µ µ µ µ Ω 25
+3V +3V C BYPASS.1µF C BYPASS.1µF C BYPASS.1µF AV DD DV DD V CAL /CH CH1 1kΩ 8kΩ MUX CAL1.9V CAL CAL2.1V CAL CAL3 CAL4 1kΩ V REF CAL2/3 PGA112 PGA113 R F R I Output Stage SPI Interface REF3225 V OUT SCLK DIO CS 2.5V ADC Ref ADC MSP43 Microcontroller GND V REF 26
+3V +3V AV DD C BYPASS.1µF DV DD C BYPASS.1µF C BYPASS.1µF V CAL /CH CH1 1kΩ 8kΩ MUX CAL1.9V CAL CAL2.1V CAL CAL3 CAL4 1kΩ V REF CAL2/3 PGA112 PGA113 R F R I Output Stage SPI Interface V OUT SCLK DIO CS ADC Ref ADC MSP43 Microcontroller GND V REF R F 1kΩ C F 2.7nF +3V +3V C BYPASS.1µF R X 1kΩ OPA364 (1.5V) R Y 1kΩ.1 µf C L2.1µF 27
V FS_ACTUAL FFFh Gain Error FFFh (4.99878V) (4.5114751443V) V REF = +5V Offset Error = +4LSB Gain Error = +6LSB V FS_IDEAL Digital Output Transfer Function with Offset Error + Gain Error Ideal Transfer Function Transfer Function with Gain Error Only Digital Output (V AD_MEAS ) Transfer Function with Offset Error + Gain Error Ideal Transfer Function (.556191443V) V Z_ACTUAL h (V) h V.5V (.1 V REF_ADC ) V IN 4.5V (.9 V REF_ADC ) 4.99878V (V REF_ADC 1LSB) Offset Error V V Z_IDEAL Analog Input V REF_ADC 1LSB 28
29
± ± ± ± +1mV V IN +2.6V V CH +2.5V 1mV C A +2.4V V IN 2mV PP R A CH CH1 MUX PGA112 PGA113 AV DD V S (+5V) DV DD +4.5V +2.5V +.5V V OUT R I G = 2 V OUT V REF V OUT1 V REF_ADC R F +4.9625V R A R X V S /2 (+2.5V) + +37.5mV V IN1 R B 3
Ω Ω Ω 31
± Ω V REF_ADC (2.5V) V IN1 (+5V, 5V) + + R B 1kΩ R X 4.81kΩ R A 9.2kΩ CH1 Input (2.447817V,.47493V) Ω Ω Ω Ω Ω Ω Ω 32
Ω Ω +5V +3V AV DD 1 C BYPASS.1µF DV DD C BYPASS.1µ F C BYPASS.1µF V CAL /CH CH1 3 2 1kΩ 8kΩ.9V CAL.1V CAL MUX CAL1 CAL2 CAL3 CAL4 V REF PGA112 PGA113 (MSOP-1) R F R I 1 Output Stage 5 7 V OUT SCLK R FILT 1Ω C FILT (1nF) C SH 4pF CDAC SAR ADC 1kΩ CAL2/3 SPI Interface 8 9 DIO CS 6 GND V REF 4 12-Bit Settling 5kHz 16-Bit Settling 3kHz 33
µ AV DD +5V DV DD +3V V CAL /CH CH1 3 2 1kΩ 8kΩ PGA112 PGA113 (MSOP-1) 1kΩ CAL1 MUX.9V CAL CAL2.1V CAL CAL3 CAL4 1 V REF CAL2/3 R F R I 1 Output Stage SPI Interface 5 7 8 9 V OUT SCLK DIO CS MSP43 Microcontroller ADC 6 GND V REF 4 34
Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) PGA112AIDGSR ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA112AIDGSRG4 ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA112AIDGST ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA112AIDGSTG4 ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA113AIDGSR ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA113AIDGSRG4 ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA113AIDGST ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA113AIDGSTG4 ACTIVE MSOP DGS 1 25 Green (RoHS & CU NIPDAU Level-2-26C-1 YEAR no Sb/Br) PGA116AIPW PREVIEW TSSOP PW 2 7 TBD Call TI Call TI PGA116AIPWR PREVIEW TSSOP PW 2 2 TBD Call TI Call TI PGA117AIPW PREVIEW TSSOP PW 2 7 TBD Call TI Call TI PGA117AIPWR PREVIEW TSSOP PW 2 2 TBD Call TI Call TI 35
REEL DIMENSIONS TAPE DIMENSIONS K P1 Reel Diameter Cavity A B W A B K W P1 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A(mm) B (mm) K (mm) P1 (mm) W (mm) Pin1 Quadrant PGA112AIDGSR MSOP DGS 1 25 33. 12.4 5.3 3.3 1.3 8. 12. Q1 PGA112AIDGST MSOP DGS 1 25 18. 12.4 5.3 3.3 1.3 8. 12. Q1 PGA113AIDGSR MSOP DGS 1 25 33. 12.4 5.3 3.3 1.3 8. 12. Q1 PGA113AIDGST MSOP DGS 1 25 18. 12.4 5.3 3.3 1.3 8. 12. Q1 36
*All dimensions are nominal Device PackageType Package Drawing Pins SPQ Length(mm) Width (mm) Height (mm) PGA112AIDGSR MSOP DGS 1 25 37. 355. 55. PGA112AIDGST MSOP DGS 1 25 37. 355. 55. PGA113AIDGSR MSOP DGS 1 25 37. 355. 55. PGA113AIDGST MSOP DGS 1 25 195. 2. 45. 37
PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE,3,65,1 M,19 14 8 4,5 4,3 6,6 6,2,15 NOM Gage Plane 1 A 7 ±8,25,75,5 1,2 MAX,15,5 Seating Plane,1 DIM PINS ** 8 14 16 2 24 28 A MAX 3,1 5,1 5,1 6,6 7,9 9,8 A MIN 2,9 4,9 4,9 6,4 7,7 9,6 4464/F 1/97 NOTES: A. B. C. D. 38
DGS (S-PDSO-G1) PLASTIC SMALL-OUTLINE PACKAGE 473272/C 2/4 NOTES: A. B. C. D. (SBOS424) 39
IMPORTANT NOTICE 21.11