NCV33163JP A昇圧/降圧/反転スイッチング・レギュレータ

Transcription

1 DCDC PDIP16 P SUFFIX CASE 648C SO16WB DW SUFFIX CASE 751G MARKING DIAGRAMS P AWLYYWWG DW AWLYYWWG 2.0 A 2.5 V60 V OC 2% MSL1 NCV A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = PbFree Package PIN CONNECTIONS ORDERING INFORMATION Device Package Shipping P PDIP16 25 Units / Rail PG DWR2 SO16WB 1000 Tape & Reel DWR2G PDIP16 (PbFree) SO16WB (PbFree) 25 Units / Rail 1000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Semiconductor Components Industries, LLC, 2014 August, 2014 Rev. 4 1 Publication Order Number: JP/D

2 This device contains 114 active transistors. Figure 1. Representative Block Diagram MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Power Supply Voltage V CC 60 V Switch Collector Voltage Range V C(switch) 1.0 to 60 V Switch Emitter Voltage Range V E(switch) 2.0 to V C(switch) V Switch Collector to Emitter Voltage V CE(switch) 60 V Switch Current (Note 2) I SW 2.5 A Driver Collector Voltage V C(driver) 1.0 to 60 V Driver Collector Current I C(driver) 150 ma Bootstrap Input Current Range (Note 2) I BS 100 to 100 ma Current Sense Input Voltage Range V Ipk (Sense) (V CC 7.0) to (V CC 1.0) V Feedback and Timing Capacitor Input Voltage Range V in 1.0 to 7.0 V Low Voltage Indicator Output Voltage Range V C(LVI) 1.0 to 60 V Low Voltage Indicator Output Sink Current I C(LVI) 10 ma Thermal Characteristics P Suffix, DualInLine Case 648C Thermal Resistance, JunctiontoAir Thermal Resistance, JunctiontoCase (Pins 4, 5, 12, 13) DW Suffix, Surface Mount Case 751G Thermal Resistance, JunctiontoAir Thermal Resistance, JunctiontoCase (Pins 4, 5, 12, 13) R JA R JC R JA R JC C/W Operating Junction Temperature T J 150 C Operating Ambient Temperature T A 40 to 115 C Storage Temperature Range T stg 65 to 150 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. () 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1500 V per MILSTD883, Method Machine Model Method 150 V. 2. Maximum package power dissipation limits must be observed. 2

3 ELECTRICAL CHARACTERISTICS (V CC = 15 V, Pin 16 = V CC, C T = 620 pf, for typical values T A = 25 C, for min/max values T A = 40 C to 115 C.) Characteristic Symbol Min Typ Max Unit OSCILLATOR Frequency T A = 25 C Total Variation over V CC = 2.5 V to 60 V, and Temperature f OSC Charge Current I chg 225 A Discharge Current I dischg 25 A Charge to Discharge Current Ratio I chg /I dischg Sawtooth Peak Voltage V OSC(P) 1.25 V Sawtooth Valley Voltage V OSC(V) 0.55 V FEEDBACK COMPARATOR 1 Threshold Voltage T A = 25 C Line Regulation (V CC = 2.5 V to 60 V, T A = 25 C) Total Variation over Line, and Temperature V th(fb1) Input Bias Current (V FB1 = 5.05 V) I IB(FB1) A FEEDBACK COMPARATOR 2 Threshold Voltage T A = 25 C Line Regulation (V CC = 2.5 V to 60 V, T A = 25 C) Total Variation over Line, and Temperature V th(fb2) Input Bias Current (V FB2 = 1.25 V) I IB(FB2) A khz V %/V V V %/V V CURRENT LIMIT COMPARATOR Threshold Voltage T A = 25 C Total Variation over V CC = 2.5 V to 60 V, and Temperature V th(ipk Sense) mv Input Bias Current (V Ipk (Sense) = 15 V) I IB(sense) A DRIVER AND OUTPUT SWITCH (Note 3) Sink Saturation Voltage (I SW = 2.5 A, Pins 14, 15 grounded) NonDarlington Connection (R Pin 9 = 110 to V CC, I SW /I DRV 20) Darlington Connection (Pins 9, 10, 11 connected) V CE(sat) V Collector OffState Leakage Current (V CE = 60 V) I C(off) A Bootstrap Input Current Source (V BS = V CC 5.0 V) I source(drv) ma Bootstrap Input Zener Clamp Voltage (I Z = 25 ma) V Z V CC 6.0 V CC 7.0 V CC 9.0 V LOW VOLTAGE INDICATOR Input Threshold (V FB2 Increasing) V th V Input Hysteresis (V FB2 Decreasing) V H 15 mv Output Sink Saturation Voltage (I sink = 2.0 ma) V OL(LVI) V Output OffState Leakage Current (V OH = 15 V) I OH A TOTAL DEVICE Standby Supply Current (V CC = 2.5 V to 60 V, Pin 8 = V CC, Pins 6, 14, 15 = GND, remaining pins open) I CC ma Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. () 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3

4 μ Δ Figure 2. Output Switch OnOff Time versus Oscillator Timing Capacitor Figure 3. Oscillator Frequency Change versus Temperature μ Figure 4. Feedback Comparator 1 Input Bias Current versus Temperature Figure 5. Feedback Comparator 2 Threshold Voltage versus Temperature Figure 6. Bootstrap Input Current Source versus Temperature Figure 7. Bootstrap Input Zener Clamp Voltage versus Temperature 4

5 Figure 8. Output Switch Source Saturation versus Emitter Current Figure 9. Output Switch Sink Saturation versus Collector Current Figure 10. Output Switch Negative Emitter Voltage versus Temperature Figure 11. Low Voltage Indicator Output Sink Saturation Voltage versus Sink Current Figure 12. Current Limit Comparator Threshold Voltage versus Temperature μ Figure 13. Current Limit Comparator Input Bias Current versus Temperature 5

6 Figure 14. Standby Supply Current versus Supply Voltage Figure 15. Standby Supply Current versus Temperature Figure 16. Minimum Operating Supply Voltage versus Temperature θ ÎÎÎÎÎ ÎÎÎ ÎÎ Figure 17. P Suffix (DIP16) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length θ ÎÎÎ ÎÎÎ ÎÎ ÎÎ Figure 18. DW Suffix (SOP16L) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length 6

7 Figure 19. Representative Block Diagram Figure 20. Typical Operating Waveforms 7

8 DCDC Figure 19 MC34163 Figure 20 1 C T C T 91 6C T NOR AND 225A25 A 1.25 V0.55 V90% C T R DT R DT Figure 2 t on /t on 0.2 nfc T NPN C T 1.25 V 22 ±0.4 A 5.0 V V 1.0% 50 mv 2 LVI V 90%LVI15 mv 6.0 ma Figure 11 R LVI C DLY t DLY V th(mpu) Figure 21 t DLY = R LVI C DLY In 1 1 V th(mpu) V out 8

9 V CC Q 2 R SC V CC 250 mv 1 R SC RSC 0.25 V Ipk (Switch) Figure A 200 nsr SC IC 170 C 2.5 A60 V R SC RSC(min) 0.25 V A Figure 2125 Figure V 10 A 1N mav CC V CC 7.0 V 100 ma ESR CB(min) I t V 4.0 ma t on 4.0 V t on 2.5 V60 V 3.0 V V CC Figure V 16 Figure

10 Test Condition Results Line Regulation V in = 8.0 V to 24 V, I O = 3.0 A 6.0 mv = ± 0.06% Load Regulation V in = 12 V, I O = 0.6 A to 3.0 A 2.0 mv = ± 0.02% Output Ripple V in = 12 V, I O = 3.0 A 36 mvpp Short Circuit Current V in = 12 V, R L = A Efficiency, Without Bootstrap V in = 12 V, I O = 3.0 A 76.7% Efficiency, With Bootstrap V in = 12 V, I O = 3.0 A 81.2% Figure 21. StepDown Converter Figure 22A. External NPN Switch Figure 22B. External PNP Saturated Switch Figure 22. External Current Boost Connections for I pk (Switch) Greater Than 2.5 A 10

11 Test Condition Results Line Regulation V in = 9.0 V to 16 V, I O = 0.6 A 30 mv = ± 0.05% Load Regulation V in = 12 V, I O = 0.1 A to 0.6 A 50 mv = ± 0.09% Output Ripple V in = 12 V, I O = 0.6 A 140 mvpp Efficiency V in = 12 V, I O = 0.6 A 88.1% Figure 23. StepUp Converter Figure 24A. External NPN Switch Figure 24B. External PNP Saturated Switch Figure 24. External Current Boost Connections for I pk (Switch) Greater Than 2.5 A 11

12 Test Condition Results Line Regulation V in = 9.0 V to 16 V, I O = 1.0 A 5.0 mv = ± 0.02% Load Regulation V in = 12 V, I O = 0.6 A to 1.0 A 2.0 mv = ± 0.01% Output Ripple V in = 12 V, I O = 1.0 A 130 mvpp Short Circuit Current V in = 12 V, R L = A Efficiency, Without Bootstrap V in = 12 V, I O = 1.0 A 73.1% Efficiency, With Bootstrap V in = 12 V, I O = 1.0 A 77.5% Figure 25. VoltageInverting Converter Figure 26A. External NPN Switch Figure 26B. External PNP Saturated Switch Figure 26. External Current Boost Connections for I pk (Switch) Greater Than 2.5 A 12

13 Calculation StepDown StepUp VoltageInverting ton (Notes toff 1, 2, 3) V out V F V in V sat V out V out V V F in V V in sat V out V F V V in sat ton t on ƒ t on 1 t on ƒ t on 1 t on ƒ t on 1 CT ƒ ƒ ƒ IL(avg) Iout I out t on 1 I out t on 1 Ipk (Switch) RSC IL(avg) I L Ipk (Switch) IL(avg) I L Ipk (Switch) IL(avg) I L Ipk (Switch) L V in V sat V out I L t on V in V sat I L I L t on V in V sat t on V ripple(pp) IL 1 8 CO 2 (ESR)2 ƒ Vout t on I out C O t on I out C O V ref R 2 R 1 1 V ref R 2 R 1 1 V ref R 2 R 1 1 The following Converter Characteristics must be chosen: V in V out I out I L V ripple(pp) Nominal operating input voltage. Desired output voltage. Desired output current. Desired peaktopeak inductor ripple current. For maximum output current it is suggested that I L be chosen to be less than 10% of the average inductor current I L(avg). This will help prevent I pk (Switch) from reaching the current limit threshold set by R SC. If the design goal is to use a minimum inductance value, let I L = 2(I L(avg) ). This will proportionally reduce converter output current capability. Maximum output switch frequency. Desired peaktopeak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor C O should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. NOTES: 1. V sat Saturation voltage of the output switch, refer to Figures 8 and 9. NOTES: 2. V F Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V. NOTES: 3. The calculated t on / must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum NOTES: 3. operating input voltage. Figure 27. Design Equations 13

14 PACKAGE DIMENSIONS SOIC16 WB CASE 751G03 ISSUE D 8X H D 16 9 A E h X 45 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 16X B 8 A B MILLIMETERS DIM MIN MAX A A B C D E e 1.27 BSC H h L q 0 7 L 14X e A1 T SEATING PLANE C SOLDERING FOOTPRINT* 16X X PITCH DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 14

15 PACKAGE DIMENSIONS PDIP16 CASE 648C04 ISSUE D A A F B N B C L M K J 16X E G 16X D T ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. () ON SemiconductorONSemiconductor Components Industries, LLC (SCILLC) SCILLC ()SCILLC SCILLC SCILLCSCILLC SCILLC SCILLCSCILLC SCILLC SCILLC PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative JP/D