3 ? 1 DVI/HDMI ????

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1 341 < Ω DVD Player PC or Game Machine STB 341 Digital TV

2 A14 B14 A13 B13 A1 B1 A11 B11 VCC (3.3 V) RINT Rx w/ RINT Rx w/ RINT Rx w/ RINT Rx w/ PRE (3.3 V) VSADJ A4 B4 A3 B3 A B Rxw/ Rxw/ Rx w/ 3-to-1 MUX Drive Drive Y4 Z4 Y3 Z3 A1 B1 Rx w/ Drive Y Z A34 B34 A33 B33 A3 B3 (3.3 V) Rx w/ Rx w/ VCC Rx w/ Drive Y1 Z1 OE S1 S S3 A31 B31 HPD1 Rx w/ HPD Control Logic HPD_SINK HPD3 SCL1 SDA1 SCL_SINK SDA_SINK SCL SDA SCL3 SDA3

3 (TOPVIEW) NC A34 B34 A33 B33 A3 B3 A31 B31 SCL3 SDA3 HPD3 OE NC HPD_SINK HPD SDA_SINK SDA SCL_SINK SCL Z1 B1 Y1 A1 Z B Y A Z3 B3 Y3 A3 VCC B4 A4 Z4 Y4 S3 S HPD1 S1 SDA1 SCL1 B11 A11 VCC B1 A1 B13 A13 VCC B14 A14 VCC VSADJ PRE NC VCC VCC VCC NC 3

NC VCC VCC VCC 60 59 58 57 56 55 54 53 5 51 50 49 48 47 46 45 44 43 4 41 61 40 6 39 63 38 64 37 65 36 66 35 67 34

4 TERMINAL NAME NO. I/O DESCRIPTION A11, A1, A13, A14 6, 9, 1, 15 I Port 1 positive inputs A1, A, A3, A4 68, 71, 74, 77 I Port positive inputs A31, A3, A33, A34 49, 5, 55, 58 I Port 3 positive inputs B11, B1, B13, B14 5, 8, 11, 14 I Port 1 negative inputs B1, B, B3, B4 67, 70, 73, 76 I Port negative inputs B31, B3, B33, B34 48, 51, 54, 57 I Port 3 negative inputs 4, 10, 16 4, 30, 36, 37, 47, 53, Ground 59, 65, 66, 7, 78 HPD1 80 O Port 1 hot plug detector output HPD 6 O Port hot plug detector output HPD3 44 O Port 3 hot plug detector output Sink side hot plug detector input HPD_SINK 40 I High: 5-V power signal asserted from source to sink and EDID is ready Low: No 5-V power signal asserted from source to sink, or EDID is not ready NC 1, 0, 41,60 No connect OE 4 I Output enable, active low Output de-emphasis adjustment PRE 19 I High: 3 db Low: 0 db SCL1 3 I/O Port 1 DDC bus clock line SCL 64 I/O Port DDC bus clock line SCL3 46 I/O Port 3 DDC bus clock line SCL_SINK 38 I/O Sink side DDC bus clock line SDA1 I/O Port 1 DDC bus data line SDA 63 I/O Port DDC bus data line SDA3 45 I/O Port 3 DDC bus data line SDA_SINK 39 I/O Sink side DDC bus data line S1, S, S3 1,, 3 I Source selector input 7, 13, 17 7, 33, 43, 50, 56 61, 69, Power supply 75, 79 VSADJ 18 I compliant voltage swing control Y1, Y, Y3, Y4 34, 31, 8, 5 O positive outputs Z1, Z, Z3, Z4 35, 3, 9, 6 O negative outputs CONTROL PINS I/O SELECTED HOT PLUG DETECT STATUS S1 S S3 Y/Z SCL_SINK SDA_SINK HPD1 HPD HPD3 H x x A1/B1 SCL1 SDA1 HPD_SINK L L L H x A/B SCL SDA L HPD_SINK L L L H A3/B3 SCL3 SDA3 L L HPD_SINK L L L None (Z) None (Z) L L L 1. (1) (1) H: Logic high; L: Logic low; X: Don't care; Z: High impedance 4

5, 8, 11, 14 I Port 1 negative inputs B1, B, B3, B4 67, 70, 73, 76 I Port negative inputs B31, B3, B33, B34 48, 51, 54, 57 I Port 3 negative inputs 4, 10, 16 4, 30, 36, 37, 47, 53, Ground 59, 65, 66,

5 Input Stage Output Stage 50Ω Vcc 50Ω 5 Ω 5 Ω Y Z A B 10 ma Control Input Stage HPD output stage Vcc Vcc OE HPD_SINK PRE S1, S, S3 400Ω HPD1 HPD HPD3 DDC pass gate Vcc SCL/SCA Source SCL/SCA Sink 8V 8V (1) PART NUMBER PART MARKING PACKAGE 341PFC PIN TQFP 341PFCR PIN TQFP Tape/Reel 5

HPD3 DDC pass gate Vcc SCL/SCA Source SCL/SCA Sink 8V 8V (1) PART NUMBER

6 over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, V () CC 0.5 V to 4 V Anm (3), Bnm 1.7 V to 4 V Voltage range Ym, Zm, VSADJ, PRE, Sn, OE, HPDn 0.5V to 4 V SCLn, SCL_SINK, SDAn, SDA_SINK, HPD_SINK 0.5 V to 6 V Human body model (4) (all pins) ±3 kv Electrostatic discharge Charged-device model (5) (all pins) ±1500 V Machine model (6) (all pins) ± 00 V Continuous power dissipation See Dissipation Rating Table DERATING FACTOR (1) T A =70 C PACKAGE T A 5 C ABOVE T A =5 C POWER RATING 80-TQFP 134 mw 13.4 mw/ C 738 mw MIN NOM MAX UNIT Supply voltage V T A Operating free-air temperature 0 70 C DIFFERENTIAL PINS (A/B) V ID Receiver peak-to-peak differential input voltage mvp-p V IC Input common mode voltage 0.04 V R VSADJ Resistor for compliant voltage swing range kω A output termination voltage, see Figure V Termination resistance, see Figure Ω Signaling rate Gbps CONTROL PINS (PRE; S, OE) V IH LVTTL High-level input voltage V V IL LVTTL Low-level input voltage 0.8 V DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) V I(DDC) Input voltage 5.3 V STATUS PINS (HPD_SINK) V IH LVTTL High-level input voltage 5.3 V V IL LVTTL Low-level input voltage 0.8 V 6

5 V to 6 V Human body model (4) (all pins) ±3 kv Electrostatic discharge Charged-device model (5) (all pins) ±1500 V Machine model (6) (all pins) ± 00 V Continuous power dissipation See Dissipation

7 over recommended operating conditions (unless otherwise noted) PARAMETEEST CONDITIONS MIN TYP (1) MAX UNIT V IH =,V IL = 0.4 V, R VSADJ = 4.64 kω, I CC Supply current =50Ω, A = 3.3 V Am/Bm = 1.65 Gbps HDMI data pattern, m =, 3, ma P D Power dissipation A1/B1 = 165 MHz clock V IH =,V IL = 0.4 V, R VSADJ = 4.64 kω, =50Ω, A = 3.3 V Am/Bm = 1.65 Gbps HDMI data pattern, m =, 3, mw A1/B1 = 165 MHz clock DIFFERENTIAL PINS (A/B; Y/Z) V OH Single-ended high-level output voltage A 10 A +10 mv V OL Single-ended low-level output voltage A 600 A 400 mv V swing Single-ended output swing voltage mv See Figure, A = 3.3 V, V OD(O) Overshoot of output differential voltage RT =50Ω, PRE=0V 6% 15% V swing V OD(U) Undershoot of output differential voltage 1% 5% V swing V OC(SS) Change in steady-state common-mode output voltage between logic states mv I (O)OFF Single-ended standby output current 0V 1.5 V, A = 3.3 V, =50Ω µa I (OS) Short circuit output current See Figure 3 1 ma V ODE(SS) Steady state output differential voltage with See Figure 4, PRE=, de-emphasis Am/Bm = 50 Mbps HDMI data pattern, m =, 3, mvp-p V ODE(pp) Peak-to-peak output differential voltage A1/B1 = 5 MHz clock mvp-p V I(open) Single-ended input voltage under high impedance input or open input I I =10µA mv Input termination resistance V IN =.9 V Ω DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) I lkg Input leakage current V I = 0.1 to 0.9 to isolated DDC ports 0.1 µa C IO Input/output capacitance V I =0V 7.5 pf R ON Switch resistance I O =3mA, V O = 0.4 V 5 50 Ω V PASS Switch output voltage V I = 3.3 V, I O = 100 µa 1.5 ().0.5 (3) V STATUS PINS (HPD) V OH(TTL) TTL High-level output voltage I OH = 8mA.4 V V OL(TTL) TTL Low-level output voltage I OL =8mA 0.4 V CONTROL PINS (PRE, S, OE) I IH High-level digital input current V IH =Vor 0.1 µa I IL Low-level digital input current V IL = or 0.8 V 0.1 µa STATUS PINS (HPD_SINK) I IH High-level digital input current V IH = 5.3 V V IH =Vor 0.1 µa I IL Low-level digital input current V IL = or 0.8 V 0.1 µa 7

65 Gbps HDMI data pattern, m =, 3, 4 394 657 mw A1/B1 = 165 MHz clock DIFFERENTIAL PINS (A/B; Y/Z) V OH Single-ended high-level output voltage A 10 A +10 mv V OL Single-ended low-level output voltage

8 over recommended operating conditions (unless otherwise noted) PARAMETEEST CONDITIONS MIN TYP (1) MAX UNIT DIFFERENTIAL PINS (Y/Z) t PLH Propagation delay time, low-to-high-level output ps t PHL Propagation delay time, high-to-low-level output ps t r Differential output signal rise time (0% - 80%) ps t f Differential output signal fall time (0% - 80%) See Figure, A = 3.3 V, ps t sk(p) Pulse skew ( t PHL t PLH ) =50Ω, PRE = 0 V 7 50 ps t sk(d) Intra-pair differential skew, see Figure ps t sk(o) Inter-pair channel-to-channel output skew () 100 ps t sk(pp) Part-to-part skew (3) 00 ps t jit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter See Figure 8, PRE = 0 V ps t jit(pp) Peak-to-peak output jitter from Y/Z(:4) residual jitter Am/Bm = 1.65 Gbps HDMI data pattern, m=,3,4 A1/B1 = 165 MHz clock ps t PRE De-emphasis duration See Figure 4, PRE = Am/Bm = 50 Mbps HDMI data pattern, m=,3,4 40 (4) ps A1/B1 = 5 MHz clock t SX Select to switch output 6 10 ns t en Enable time See Figure ns t dis Disable time 6 10 ns DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) t pd(ddc) Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn See Figure 7, C L =10pF ns CONTROL AND STATUS PINS (S, HPD_SINK, HPD) t pd(hpd) Propagation delay (from HPD_SINK to the active port of HPD) 6.0 ns See Figure 7, C L =10pF t sx(hpd) Switch time (from port select to the latest valid status of HPD) ns 8

3 V, 75 40 ps t sk(p) Pulse skew ( t PHL t PLH ) =50Ω, PRE = 0 V 7 50 ps t sk(d) Intra-pair differential skew, see Figure 5 3 50 ps t sk(o) Inter-pair channel-to-channel output skew () 100 ps t

9 AVcc Driver Z O = Z O = Receiver 1. Vcc V A V ID A Receiver Driver Y C L 0.5 pf V Y AVcc B Z V B V = V ID A V B V swing = V Y V Z V Z V A Vcc V B V ID Vcc 0.4 V 0.4 V V ID(pp) V ID 0 V 0.4 V t PHL t PLH 80% V OD(O) 100% V OD(pp) 0V Differential t f 0% t r 0% V OC V OD(U) V OC(SS). 9

10 50 Ω Driver 50 Ω I OS + _ 0 V or 3.6 V 3. 1 bit 1 to N bit VOD(pp) V ODE(SS) 80% 0% t PRE 4. V Y V OH 50% V Z t sk(d) V OL 5. 10

11 Input 1 Kept High Input /Input 3 Kept Low A B A B 3.3 V S1 Clocking S or S3 Kept High 0 V Output Y Z t sx 75 mv 75 mv Hi-Z 75 mv 75 mv t sx 3.3 V OE t dis t en 0 V 6. HPD_SINK HPD1 0.4 V t pd(hpd) t pd(hpd) t sx(hpd).4 V HPD HPD3 0 V S1 S S3 0 V SDA_SINK t pd(ddc) t pd(ddc) SDA1 SDA SDA

mv 75 mv t sx 3.3 V OE t dis t en 0 V 6. HPD_SINK HPD1 0.

12 AVcc Data + Data - Video Patterm Generator Coax Coax SMA SMA 5m 8AWG HDMI Cable RX + M U X 341 OUT 0dB <" 50Ω Transmission Line <" 50 Ω Transmission Line SMA SMA Coax Coax AVcc Jitter Test Instrument 1000 mvpp Differential Clk+ Clk- Coax Coax SMA SMA RX + M U X OUT 0dB <" 50 Ω Transmission Line <" 50 Ω Transmission Line SMA SMA Coax Coax Jitter Test Instrument TP1 TP TP3 A. B input equalization gain vs. 5m DVI/HDMI cable response 0 Inversed 341 Gain AWG 5m HDMI Cable Gain - db AWG 5m DVI Cable f Frequency MHz 9. 1

<" 50 Ω Transmission Line SMA SMA Coax Coax Jitter Test Instrument TP1 TP TP3 A. B. 8. 341 input equalization gain vs.

13 SUPPLY CURRENT vs FRUENCY SUPPLY CURRENT vs FREE-AIEMPERATURE ICC - Supply Current - ma =A = 3.3 V, T A = 5 C, TP1 V ID(PP) = 800 mv p-p, R VSADJ = 4.64 KΩ PRE = OE = Low Input (:4) HDMI Data Pattern, 50 Mbps Gbps Input (1) Clock, 5 MHz MHz ICC - Supply Current - ma =A = 3.3 V, TP1 V ID(PP) = 800 mv, R VSADJ = 4.64 KΩ Input (:4) 1.65 Gbps HDMI Data Pattern Input (1) 165 Mhz Clock f - Frequency - MHz 10 T - Free-Air Temperature - C A 11 RESIDUAL DETERMINISTIC JITTER vs DATA RATE RESIDUAL PEAK-TO-PEAK JITTER vs CLOCK FRUENCY Residual Deterministic Jitter - % Unit Interval =A = 3.3 V, T A = 5 C, TP1 V ID(PP) = 800 mv, R VSADJ = 4.64 KΩ PRE = OE = Low, Source jitter = 180 ps 1 m HDMI Cable 5 m HDMI Cable 3 m HDMI Cable Residual Peak-Peak Jitter - % Unit Interval 3 1 =A = 3.3 V, T A = 5 C, TP1 V ID(PP) = 800 mv p-p, R VSADJ = 4.64 KΩ PRE = OE = Low, Source jitter = 150 ps 1 m HDMI Cable 5 m HDMI Cable 3 m HDMI Cable Data Rate - Mbps Clock Frequency - MHz 13 13

14 RESIDUAL DETERMINISTIC JITTER vs DIFFERENTIAL INPUT VOLTAGE RESIDUAL PEAK-TO-PEAK JITTER vs DIFFERENTIAL INPUT VOLTAGE Residual Deterministic Jitter - % Unit Interval Mbps 74.5 Mbps 70 Mbps =A = 3.3 V, T A = 5 C, R VSADJ = 4.64 KΩ, PRE = OE = Low Residual Peak-Peak Jitter - % Unit Interval MHz 74.5 MHz 7 MHz =A = 3.3 V, T A = 5 C, R VSADJ = 4.64 KΩ, PRE = OE = Low Peak-to-Peak Differential Input Voltage - mvp-p Peak-to-Peak Differential Input Voltage - mvp-p RESIDUAL DETERMINISTIC JITTER vs FR4 PCB TRACE (at 3dB Pre-Emphasis) RESIDUAL PEAK-TO-PEAK JITTER vs FR4 PCB TRACE (at 3dB Pre-Emphasis) Residual Deterministic Jitter - % Unit Interval =A = 3.3 V, T A = 5 C, TP1 V ID(PP) = 800 mv, R VSADJ = 4.64 KΩ PRE = High, OE = Low, 5-m 8 AWG HDMI Cable 1485 Mbps 74.5 Mbps 70 Mbps FR4 PCB Trace - Inch Residual Peak-Peak Jitter - % Unit Interval =A = 3.3 V, T A = 5 C, TP1 V ID(PP) = 800 mv, R VSADJ = 4.64 KΩ PRE = High, OE = Low, 5-m 8 AWG HDMI Cable MHz 74.5 MHz 7 MHz FR4 PCB Trace - Inch

5 MHz 74.5 MHz 7 MHz =A = 3.3 V, T A = 5 C, R VSADJ = 4.

15 TP1 TP TP3 341 Test Board Video Format Generator 8 AWG HDMI Cable

17 µ Ω Ω Ω µ 341 A Receiver Driver Y A B Z 31. A 341 Z O = Driver Z O = Receiver 3. 17

18 Ω Ω Ω

19 V(t) = V DD (1 e t/rc ) (1) t r(30-70) =t IH t IL = RC () Ω Ω = Ω = Ω = // = Ω = // // // // // µ Source Switch Box Sink V DDsource V DDsink R upsource 341 R upsink SDAn SDA_Sink C source C cable1 C I C O C cable C sink

20 Source Sink V DDsource V DDsink R upsource R upsink 341 DVI/HDMI RX SDAn SDA_Sink C source C cable Csink 38. DDC THRESHOLD VOLTAGE, V IH = 0.7 V DD,V IL = 0.3 V DD TOTAL CABLE LENGTH (m) SUGGESTED PULL-UP RESISTANCE (kω) CABLE TYPE SWITCH BOX Lcable1 + Lcable DIGITAL DISPLAY Lcable R upsource = 1.5 kω 8-AWG DVI R upsink =47kΩ 8-AWG HDMI DDC THRESHOLD VOLTAGE, V IH = 1.9 V, V IL = 0.7 V TOTAL CABLE LENGTH (m) SUGGESTED PULL-UP RESISTANCE (kω) CABLE TYPE SWITCH BOX Lcable1 + Lcable DIGITAL DISPLAY Lcable R upsource = 1.5 kω 8-AWG DVI R upsink =47kΩ 8-AWG HDMI

3 V DD TOTAL CABLE LENGTH (m) SUGGESTED PULL-UP RESISTANCE (kω) CABLE TYPE SWITCH BOX Lcable1 + Lcable DIGITAL DISPLAY Lcable R upsource = 1.

21 PACKAGING INFOMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty 341PFC ACTIVE TQFP PFC Green (RoHS & no Sb/Br) 341PFCG4 ACTIVE TQFP PFC Green (RoHS & no Sb/Br) 341PFCR ACTIVE TQFP PFC Green (RoHS & no Sb/Br) 341PFCRG4 ACTIVE TQFP PFC Green (RoHS & no Sb/Br) Eco Plan () Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Level-4-60C-7 HR Level-4-60C-7 HR Level-4-60C-7 HR Level-4-60C-7 HR 1

22 0,7 0,50 0,08 M 0, ,13 NOM 1 0 9,50 TYP 1,0 SQ 11,80 14,0 13,80 SQ 0,05 MIN 0,5 Gage Plane 0 7 1,05 0,95 0,75 0,45 Seating Plane 1,0 MAX 0, / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-06 (SLLS660B_August 005)

23 IMPORTANT NOTICE

電源監視回路

電源監視回路 TPS3820-xx,TPS3823-xx TPS3824-xx,TPS3825-xx TPS3828-xx www.tij.co.jp µ TYPICAL APPLICATION TPS3820, TPS3823, TPS3828: DBV PACKAGE (TOP VIEW) GND MR 1 2 3 5 4 VDD WDI TPS3824: DBV PACKAGE (TOP VIEW) 1 5