main01a.dvi

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1 Tutorial1A Tutorial1A TA A 2 H8/36064 Vstone (VS-WRC003 TA RAM ROM 1B ROM ( 2011/index.html 2. H8 High-performance Embedded Workshop (HEW HTerm ROM Flash Development Toolkit(FDT HEW,HTerm,FDT, 2.1 VS-WRC003 table1 VS-WRC003 I/O VS-WRC004 IO(CN10/EXT VS-WRC004 VS-WRC003 chaser/download.html 1A 1/22

2 DC 2 Table 1: RC 0 ( 2 ( 4 1 LED 1 (1 LED 3. LED1 LED1 I/O iodefine.h 3.1 VS-WRC003 LCD( zip MONITOR.MOT FDT ROM PC [ ] COM3 FDT Basic Full Name H8/36064F COM3( [MHz] FDT Simple Interface User/Data Area MONITOR.MOT 3.2 HTerm Hterm COM1 Hterm COM3( PC ( HTerm HTerm G Enter F5 H8/36064 Series Normal Mode Monitor Ver. 2.0B Copyright (C 2003 Renesas Technology Corp. HTerm Hterm Hterm 1A 2/22

3 3.3 HEW HTerm HEW HTerm RAM LED zip sample problem sample.hws 2 TA 7 PC LED1 VS-wrc003 LED1 Fig.1 (P64 Fig. 1: LED H8/36064 ctrl+f P64 pdf P (PCR6 6(PDR6 P64 4 LED1 PCR6 PCR6 Fig.2 PDR6 H (1 L (0 PDR6 Fig.3 PDR6 LED P64 Fig.1 LED L Fig. 2: PCR6 1A 3/22

4 Fig. 3: PDR I/O iodefine.h H8/ I/O I/O sample.hws iodefine.h (struct I/O #define IO (union Bit CSEL:2; 2 2 1A 4/22

5 I/O. [ ].[ ]= 0x?? 0x 16? 0 F 4 PCR IO.PCR1=0x21 IENR2 [ (= ].BIT.[ ]=? [ ].[ ].BIT.[ ]=?? n 0 (2 n RTINTE ABRK.CR.BIT.RTINTE=1 ACMP 3 1 ABRK.CR.BIT.ACMP=7 [ ].[ ].BYTE= 0x?? H8/36064 iodefine.h iodefine.h LED sample.c main LED1 1a-1 LED1 1. iodefine.h LED1 PCR6 2. PDR6 3. sample.c 1a-1 ( sample.c 1a-1? LED1( sample.c Debug Release Dubug Hterm Release ROM HEW Debug Debug 0 Errors sample.abs Debug 3.4 RAM HEW ROM RAM Fig.7 RAM H F780 H FF7F H 16 H F890 HEW H8S, H8/300 Standard Toolchain... Fig.4 1A 5/22

6 Fig. 4: H8S, H8/300 Standard Toolchain Fig.5 PC 7 Fig.6 Fig. 5: Section Fig. 6: Section HTerm F9 sample.abs RAM G Enter F5 LED1( Hterm 1A 6/22

7 Fig. 7: H8/ (H/L (0/1 1 (, 1 ( 1 1A 7/22

8 5. ( ( set imask ccr(1; set imask ccr(0; 5.1 B1, V, Z0, Z1 B1 5[ms] LED A 8/22

9 5.1.1 B1 TCB1( B1 ( 1 TMB1 TMB10 TMB = 256 B1 TMB1,TLB1,IENR2,IRR2 4 B1 IENR2( IRR2( / Fig.8 Fig.9 Fig. 8: IENR2 IENTB1 0 IRRTB1 0 1 TCB1 256 IRRTB1 1 TMB1( TLB1( TLB TMB1 Fig.10 TMB1 TMB17(RLD TCB1 TLB1 TCB1 TLB1 TCB1 0 1A 9/22

10 Fig. 9: IRR2 Fig. 10: TMB1 TMB10 TMB12(CKS TCB A 10/22

11 B1 sample.c void main(void{ // set_imask_ccr(1; // TB1 : 5 [ms] TB1.TMB1.BIT.RLD = 1; TB1.TMB1.BIT.CKS = 2; TB1.TLB1=?; IENR2.BIT.IENTB1=?; // IRR2.BIT.IRRTB1=?; // // set_imask_ccr(0; } //TCB1 //TCB1 256 //IRR2.BIT.IRRTB1= 1; intprg.c // interrupt(vect=29 void INT_TimerB1(void { IRR2.BIT.IRRTB1=?; // } 5[ms] TB1.TMB1.BIT.RLD = 1; TLB1 5[ms] T[s] f[hz] TLB1 T= 1 f (28 TLB1 ( TCB1 TCB1 TLB1 T 5[ms] f TB1.TMB1.BIT.CKS= 2; 010 φ/512 φ φ= [mhz] T = ( f = (3 512 (1 (3 TLB1 TB1.TLB1=?;? 1A 11/22

12 5.1.2 H8S,H8/300 HEW intprg.c 2 intprg.c B1 interrupt // vector 29 Timer B1 interrupt(vect=29 void INT TimerB1(void resetprg.c #pragma interrupt (INT TimerB1 void INT TimerB1(void; resetprg.c intprg.c 1a-3,4 INT WKP intprg.c interrupt(vect=18 void INT WKP(void #pragma interrupt intprg.c sample.c extern (21 26 extern intprg.c INT TimerB1(void IRR2.BIT.IRRTB1=0; 1a-2 LED1 1. 1a-2 sample.c intprg.c (3 2. 1a-1 ( 3.? 0.5 LED1 LED1flag 0,1 main LED1flag IO.PDR5.BIT.B5 reset reset=1 break 2 15 # pragma section IntPRG sample.c # pragma section IntPRG 1A 12/22

13 5.2 L H NMI,IRQ,WKP NMI NMI MONITOR.MOT Hterm IRQ WKP IRQ H8/ WKP WKP WKP0 WKP5 6 WKP INT WKP 3 WKP0 WKP0 IEGR2,IENR1,IWPR,PMR5 IEGR2( Fig.11 on H L off 0 WPEG0 0 on IENR1( Fig.12 WKP 5 IENWP 1 IWPR( Fig.13 / PMR5( Fig.14 WKP0 P50 0 WKP WKP // vector 18 WKP interrupt(vect=18 void INT WKP(void{} #pragma interrupt (INT WKP void INT WKP(void; 3 IRQ IRQ0 IRQ3 1A 13/22

14 Fig. 11: IEGR2 1A 14/22

15 Fig. 12: IENR1 1A 15/22

16 Fig. 13: IWPR 1A 16/22

17 5.2.3 Fig. 14: PMR5 1a-3 ON/OFF 1. 1a-3 2. sensor ON/OFF main 3. sensor 1B Fig.2 4 Vcc,GND,Signal Signal P50 I/O Signal VSWRC003 ON/OFF Buzzer ON/OFF V CC GND IC 4 1BFig.1 1A 17/22

18 5.2.4 ON/OFF ON/OFF ON/OFF 1B ON/OFF ON/OFF 1a sensor 1a-3 Hint sensorontime timer if /* */ if (sensorontime+? < timer{ // sensor 0.1 // sensor =? ; // sensor? =? ; // sersor } Hterm 0.5 LED1 ON/OFF 6. ROM ROM 5 ROM PC Hterm H8/36064 ROM 1000 Hterm ROM RAM 2k RAM ROM HEW Debug Release Release 6 warning (.mot Release FDT FDT Release mot Debug mot Hterm FDT 5 Read-Only Memory Read Only Member 6 Release 3.4 1A 18/22

19 7. PC PC 7.1 URL H8/ tiny/h836064/documentation.jsp# VS-WRC003 wrc003/download.html#03 VS-WRC003 wrc003/download.html#03 H8S,H8/300 h8s.pdf 7.2 HEW(High-Performance Embedded Workshop H8SX,H8S,H8 C/C++ V.7.00 Release 00 results/c c /evaluation software h8c.jsp 1. URL Download 4. My Renesas 7.3 h8v7000 ev.exe next ( H8SX H8S H8 C/C FDT(Flash Development Toolkit V.4.07 Release 01 results/c c /evaluation software fdt v4.jsp 1. URL Download 4. My Renesas 1A 19/22

20 7.5 fdtv407r01.exe next Select Language Select Features Select Options.mot ( 7.6 Hterm folder/sample program/seminar sample downh83h.jsp? Hterm program/seminar sample downh83h/htermmdi.exe htermmdi.exe OK C:/hterm Hterm.exe MONITOR.MOT FDT program/seminar sample downh83h/300thew3.exe 300thew3.exe OK C:/300t monitor.hws HEW MONITOR.MOT ( mtanaka/microcomputer/monitor.html#make Hterm Hterm 3.2 not found 1. pdf %20.jsp 2. 1A 20/22

21 7.7 HEW HEW OK Fig.15 OK abc Fig. 15: Fig.16 CPU 300H CPU CPU SERIES CPU TYPE OK Fig. 16: new project 3.4 :RAM HEW sample problem resetprg.c,intprg.c,iodefine.h workspace abc ( resetprg.c,intprg.c,iodefine.h HEW ( iodefine.h WDT( #include<machine.h> #include iodefine.h 1A 21/22

22 sample problem sample.hws sample.c void main(void resetprg.c intprg.c ( A 22/22

MechLab.dvi

MechLab.dvi Rev. 1.11, Jan. 2010 mtanaka@ctrl.titech.ac.jp torii@ctrl.titech.ac.jp 0 5 0.1 3 310 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 0.2 : : : : : : : : : : : : : : : : : : : : : : : : :