MechLab.dvi

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1 Rev. 1.0, August Hterm Hterm Hterm

2 HEW printf scanf , NMI ( V)

3 B B B ( ) ROM WDT(WatchDog Timer) PWM RC DC PWM PWM(Pulse Width Modulation) DC (H ) DC (TB6552) PWM RC RC GWS Micro2BBMG Z Z Z PWM Z Z Z

4 (QRB1134) A/D H8/36064 A/D A/D ,2,4 ( ) (H8/36064) (WRC-003) A iodefine.h 67 4

5 [ctrl***] * 3 S5-104 S (Microcomputer) (Microcontroller) DC DC ( ) DC ( ) H8 ATMEL AVR PIC H8 H8/36064 H8/36064 CPU A/D 5

6 0.3 VStone WRC-003 H8 H8/36064 CPU( H8 H8/36064 ) ( TB6552FN) USB- (Silicon Labs. CP2102) (Abracon Coporation ABMM [MHz]) LED 2 USB (mini-b ) 0.4 C C HEW(High-performance Embedded Workshop) HEW H HEW FDT ROM HTERM RAM 6

7 0.6 RAM C MonitorSample.c MonitorIntprg.c 0.8 C: Program Files Renesas doc index.html 1. VS-WRC VS-WRC003 C 3. HEW 4. VS-WRC H H8 C/C++ Ver H8 High-performance Embedded Workshop V H8 E8a 9. H8 E8/E8a 10. DC TB6552FN 11. USB- CP readme.htm 13. monitor.htm ( ) 7

8 H H H8/Tiny CQ 2005 [ ] H8 I/O 2007 [ ] H [ ] C 2006 [ ] H [ ] ( ) 3. VS-WRC003 (vs-wrc003b.pdf) H (rjj09b0049 h pdf) 6. iodefine.h 7. 8

9 printf ROM RAM ROM ROM ROM 1.1 ROM printf PC モニタプログラム (mot) FDT 転送書込 USB ケーブルマイコン ROM 領域モニタプログラム RAM 領域 PC HEW コンパイル自作プログラム (mot) USB ケーブル HTERM 転送実行マイコン電源 ON ROM 領域実行モニタプログラム RAM 領域自作プログラム (a) (b). 1.1: RAM PC HEW コンパイル自作プログラム (mot) FDT 転送書込 USB ケーブルマイコン電源 ON ROM 領域実行自作プログラム RAM 領域. 1.2: ROM 9

10 Table 1.1: ROM ROM ( ) ( )1,000 printf ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) : 1. (FDT)[ ] 2. (HEW) 3. (HEW) mot 4. mot (HTERM) 5. (HTERM) ROM mot RAM (USB ) mot ROM ROM FDT(Flash Development Toolkit) 10

11 1. MONITOR.MOT MONITOR.MOT 2. VS-WRC003 C (HEW samplemanual v0.2.pdf) p.19 FDT VS-WRC003 COM [COM3] 3. VS-WRC003 C (HEW samplemanual v0.2.pdf) p.8 VS-WRC003 MONITOR.MOT LED.mot MONITOR.MOT Full Name: H8/36064F : [Mhz] 4. HTERM HTERM readme.htm (monitor.htm) Hterm RAM RAM 2K (float, double) printf, scanf L2321 (E) Section B overlaps section P printf, scanf (char, int ) 11

12 1.4 Hterm Hterm Hterm Hterm Hterm 1. USB OFF 2. ON LED2( ) 3. Renesas Hterm 4. H8/36064 Series Normal Mode Monitor Ver. 2.0B Copyright (C) 2003 Renesas Technology Corp. 1. OFF 2. Hterm 3. ON 4. Hterm 5. ( ) 1. Hterm 2. Hterm Hterm 3. (C) COM3 (B):38400 OK HEW abs ( abs ) abs 12

13 abs 1. Hterm 2. Hterm Load F9 3. (T): ELF/DWARF (*.abs) 4. abs Hterm Go F5 mot 1 Z dump Hterm Dump 16 ASCII Hterm Console D D monitor.htm ( ) (monitor.htm) Hterm Periferal H (rjj09b0049 h pdf) 13

14 H8 H8 monitor.htm ( ) (monitor.htm) ( ) ( ASCII ) (bit) (byte) ( ) ( 36) = (word) A B C D E F AB12 AB printf printf printf printf (b ) (s ) Hterm 1 (Pstep) 1 CPU 14

15 monitor.htm ( ) (monitor.htm) printf scanf SET VECTOR TABLE resetprg.c main SET VECTOR TABLE SET VECTOR TABLE 1.5 C: WorkSpace 010MonitorMemory.zip HEW Renesas High-performance Embedded Workshop High-performance Embedded Workshop HEW C F7 Build 0 errors C: WorkSpace 010MonitorMemory MonitorSample Debug abs mot abs mot Hterm printf scanf 1 printf scanf printf Hterm scanf Hterm printf scanf ROM printf scanf printf scanf C 15

16 1.5.3 / 1.1 / void main(void) { int i, offset; int array[6]; char message[16]; printf( "Input offset: " ); scanf( "%d", &offset ); printf( "\n" ); for( i = 0; i < 6; i++ ){ array[i] = i i+offset; printf( "%d %3d 0x%02x\n", i, array[i], array[i] ); } printf( "\n" ); printf( "array dump: %x\n", array ); printf( "message dump: %x\n", message ); i = 0; message[i++] = 0x48; message[i++] = 0x65; message[i++] = 0x6C; message[i++] = 0x6C; message[i++] = 0x6F; message[i++] = 0x20; message[i++] = 0x54; message[i++] = 0x6F; message[i++] = 0x6B; message[i++] = 0x79; message[i++] = 0x6F; message[i++] = 0x54; message[i++] = 0x65; message[i++] = 0x63; message[i++] = 0x68; message[i++] = 0x21; } RESET(); 16

17 ROM array message ASCII

18 LED CPU CPU CPU A/D タイマ A/D 変換器周辺回路外部入力スイッチマウスキーボードセンサ通信ポート CPU メモリ ROM 領域 RAM 領域プログラムデータ外部出力 LED モータサーボアクチュエータ通信ポート. 2.1: CPU 18

19 A/D 2.1 CPU 2.2 Renesas H8/ CPU 2.2 CPU CPU (1) ( ) (2) CPU (1) ( ) (2). 2.2: (Renesas H8/36064 ). 2.3: (Renesas H8/36064 ) 19

20 CPU (1) (2) CPU ( ) ( ) ( ) ( ) 2.3 Renesas H8/ (0 1 ) LED LED 2.4 H8/36064 P64 P65 Vstone WRC VS-WRC003 (vs-wrc003b.pdf) 20

21 . 2.4: (Renesas H8/36064 ) Table 2.2: P21/RXD CP2102 TXD P22/TXD CP2102 RXD P60/FTIOA0 TB6552FN APWM Z TB6552FN CN1 P30 TB6552FN AIN1 TB6552FN CN1 P31 TB6552FN AIN2 TB6552FN CN1 P61/FTIOB0 TB6552FN BPWM Z TB6552FN CN2 P32 TB6552FN BIN1 TB6552FN CN2 P33 TB6552FN BIN2 TB6552FN CN2 P55/WKP5/ADTRG 0 1 NMI P55 NMI P64/FTIOA1 LED1 0 1 P65/FTIOB1 LED2 0 1 P76/TMOV V PB0/AN0 (CN4) PB1/AN1 (CN5) PB2/AN2 (CN6) PB3/AN3 (CN7) 21

22 2.4.2 H8 ( ) iodefine.h / PMR( ) H (rjj09b0049 h pdf) PCR( ) 1 0 PUCR( ) MOS 1 0 PDR( ) PORT PMR PCR PUCR PDR P1 IO.PMR1 IO.PCR1 IO.PUCR1 IO.PDR1 P2 IO.PMR3 IO.PCR2 - IO.PDR2 P3 - IO.PCR3 - IO.PDR3 P5 IO.PMR5 IO.PCR5 IO.PUCR5 IO.PDR5 P6 - IO.PCR6 - IO.PDR6 P7 - IO.PCR7 - IO.PDR7 P8 - IO.PCR8 - IO.PDR7 PB IO.PDRB BYTE BIT.B? iodefine.h 22

23 2.4.4 LED1 2.2 P64 LED1 P64 LED1 IO.PCR6 4 1 P64 IO.PDR6 4 0 LED1 LED1 / 2.1 / void main(void) { IO.PCR6 = 0x10; / IO.PCR6 4 1 (P64 ) / IO.PDR6.BIT.B4 = 0; / IO.PDR6.BIT.B4 0 (P64 Low ) / } for(;;){ / / } P55 P55 IO.PMR5 5 0 P55 IO.PCR5 5 0 P55 OFF IO.PDR / 2.2 / void main(void) { IO.PMR5.BIT.WKP5 = 0; / 5 0 (P55 ) / IO.PCR5 &= 0xDF; / 5 0 (P55 ) / } for(;;){ / / if( IO.PDR5.BIT.B5 == 0 ){ / / }else{ / / } } 23

24 P76/TMOV ON/OFF ON/OFF / 2.3 / void BuzzerSet(unsigned char pitch, unsigned char vol) { TV.TCRV0.BYTE=0x00; TV.TCRV1.BYTE=0x01; TV.TCSRV.BYTE=0x06; } TV.TCORA=(unsigned char)( ((unsigned int)(pitch) (unsigned int)(vol)) >> 8 ); TV.TCORB=pitch; void BuzzerON() / buzzer start / { TV.TCRV0.BIT.CKS = 0x03; } void BuzzerOFF() / buzzer stop / { TV.TCRV0.BIT.CKS = 0x00; } V TMOV V TMOV BuzzerSet BuzzerSet pitch vol pitch vol pitch vol BuzzerSet BuzzerON() BuzzerON() BuzzerOFF() OFF 24

25 LED LED1 LED2 LED1 LED V 2-4. V

26 ( ) C ( ) CPU GUI CPU 2 Windows Windows 26

27 CPU CPU CPU ( ) ( ) ( ) ( ) ( ) 1. ( ) ( ) T[sec] T[sec] (PC, Program Counter) ( ) 27

28 ベクタテーブル割り込み関数のアドレス割り込み関数のアドレス割り込み関数のアドレス割り込み要因毎に割り込み関数のアドレスが設定されている 4 割り込み関数のアドレス読込 5 割り込み処理開始 6 割り込み処理終了メモリ命令 1 命令 2 命令 3 PC(Program Counter) 命令 1 実行後, 命令 2 のアドレスへ移動メイン処理 1 割り込み要因発生 2 メイン処理中断割り込み処理 3 内部状態の待避内部状態 (PC や各種レジスタ ) メイン処理 8 メイン処理再開 7 内部状態の読込 Time スタック領域. 3.1: PC. 3.2: CPU 3 ( 3.2) ( ) 28

29 MonitorIntprg.c INT NMI H (rjj09b0049 h pdf) B1 B1 WKP Table 3.3: (Renesas H8/36064 ) NMI INT NMI WKP INT WKP V A INT TimerV B A/D A/D INT ADI Z0 INT TimerZ0 Z1 INT TimerZ1 B1 INT TimerB ( ) 29

30 High(1) Low(0) ポートの入力 OFF ON 不安定 ( チャタリング ) Time. 3.3: High(1) Low(0) High(1) Low(0) ポートの入力結果 OFF 割り込み ON Wait 再確認割り込み OFF Wait 再確認 (a) Time Time ポートの入力 High(1) OFF Low(0) サンプリング High(1) Low(0) 結果 ON (b) OFF Time 周期はチャタリング期間より長く設定 Time チャタリング時にサンプリングしても結果は安定 ( ただし, 二通りの可能性のどちらになるかは不明 ). 3.4: P ON OFF ON OFF

31 LPF(Low-Pass Filter) ( ) 3.4 ON/OFF (ON OFF OFF ON ) 1 1 割り込み要求フラグ 1 割り込み処理クリア割り込み処理クリア全ての割り込み禁止 set_imask_ccr((_ubyte)1) 0 Time 割り込み発生割り込み発生 (a) 割り込みの設定 ( レジスタの設定など ) 割り込み要求フラグ 1 割り込み処理割り込み処理割り込み処理割り込み要求フラグを 0 にクリア 0 Time 割り込み発生 (b). 3.5: 全ての割り込み許可 set_imask_ccr((_ubyte)0). 3.6: 31

32 3.2.8, NMI (a) (a) 1 0 CPU 3.6 set imask ccr 1 set imask ccr 0 set imask ccr(1); /* */ set imask ccr(0); /* */ NMI(Non Maskable Interrupt) NMI set imask ccr (WRC-003) NMI P ITU(, Integrated Timer Unit)

33 H8/36064 B1 V Z(2 ) 4 H8/36064 WDT( WatchDog Timer) 14 PWM H (rjj09b0049 h pdf) 3.7 (PWM) PWM PWM PWM PWM 3.7 H (rjj09b0049 h pdf) 入力信号立ち上がり立ち下がり両エッジカウンタ ( カウントアップ ) クリアコンペアレジスタ比較割り込み発生出力変更. 3.7: 33

34 3.3.3 ( V) V V V 8 2 PWM BuzzerSet TCRV0 TCRV1, TCSRV, TCORA TCORB 3.4 TCRV0 TCRV1 TCSRV 3.5 TCORA TCORB BuzzerSet V 3.5-(c) BuzzerSet CKS2 CKS1 CKS0 ICKS0 = CMIEB,CMIEA OVIE 0 CCLR1 CCLR0 = TCORA TCORB TCORB pitch TCORA pitch vol/256 >> C unsigned char 255 TCORA < TCORB OS3 OS2 = 0 1 (TCNTV) TCORB TMOV 0 OS1 OS0 = 1 0 (TCNTV) TCORA 34

35 0xFF TCORB TCORA TCNTV の値 ( カウンタの値 ) 0x00 High(1) Low(0) TOMV の出力 Time Time. 3.8: TOMV V TMOV 1 BuzzerSet BuzzerStart CKS 0x03 BuzzerStart CKS2 CKS1 CKS0 ICKS0 = (c) /128 WRC [MHz] BuzzerStop CKS 0x03 BuzzerStop CKS2 CKS1 CKS0 ICKS0 = (c) 3.8 V TOMV TOMV ON/OFF TCORA TOMV 1 TCORB TOMV

36 Table 3.4: V (a) TCRV CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 HEX x00 (c) TCRV TVEG1 TVEG0 TRGE - ICKS0 HEX x01 (c) TCSRV CMFV CMFA OVF - OS3 OS2 OS1 OS0 HEX x06 Table 3.5: V (Renesas H8/36064 ) (a) TCRV0 (b) TCRV1 (c) (CKS,ICKS) (d) TCSRV 36

37 3.4 B B1 B1 8 ( ) B1 3.9 B1 B1 B1 ( ) [msec] 10[msec] B1 5[msec] B1 3.6 B B / [MHz] B [MHz] / 512 = 28.8[KHz] 5[msec] 28.8[KHz] 5[msec] / 28.8[KHz] = 144[count] B1 8 (256) (TLB1) =112 B1 / B B1 B1 3.7 / IENR2 IRR2 2 37

38 IENR2 1 B1 IRR2 1 IENR2 1 IRR2 0 IRR

39 0xFF TCB1 の値 ( カウンタの値 ) 5[msec] TLB1 0x00 割り込み要求発生割り込み要求発生割り込み要求発生 Time High(1) 出力割り込み処理トグル出力割り込み処理トグル出力割り込み処理トグル出力 Low(0) 10[msec] Time. 3.9: B1 Table 3.6: B1 (TMB1)(Renesas H8/36064 ) Table 3.7: B1 (Renesas H8/36064 ) (a) / (IENR2) (b) (IRR2) 39

40 3.4.4 LED1 1/4 LED1 MonitorIntprg.c / / / global variables / / / unsigned char gcnt; / / / interrupt functions / / / void INT NMI(void) { RESET(); } void INT TimerB1(void) { IRR2.BIT.IRRTB1 = 0; / / IO.PDR7.BIT.B6 =!IO.PDR7.BIT.B6; / (P76) ( ) / } gcnt = gcnt + 1; / gcnt / gcnt = gcnt & 0x03; / 2 / if( gcnt == 0 ){ / 1/4 / IO.PDR6.BIT.B4 =!IO.PDR6.BIT.B4; / LED1 (P64) / } MonitorSample.c / / / main function / / / void main(void) { set imask ccr(1); / / IO.PCR6 = 0x10; / IO.PCR6 4 1 (P64 ) / TV.TCSRV.BIT.OS = 0; / P76 / IO.PCR7 = 0x40; / IO.PCR7 6 1 (P76 ) / TB1.TMB1.BIT.RLD = 1; / / TB1.TMB1.BIT.CKS = 2; / [010] /512 / TB1.TLB1 = 122; / TLB1 122, 144 / IRR2.BIT.IRRTB1 = 0; / TMB1 / IENR2.BIT.IENTB1 = 1; / TMB1 / set imask ccr(0); / / } for(;;){} / / 40

41 B1 B1 MonitorIntprg.c / / / global variables / / / unsigned char gp55old = 0xFF; / P55 / / / / interrupt functions / / / void INT NMI(void) { RESET(); } void INT TimerB1(void) { unsigned char P55; IRR2.BIT.IRRTB1 = 0; / / P55 = IO.PDR5.BIT.B5; / P55 / if( gp55old == 1 && P55 == 0 ){ / / }else if( gp55old == 0 && P55 == 1 ){ / / } } gp55old = P55; / P55 / 41

42 LED LED ( ) 3-2. LED LED (LED1,LED2) (, ) ( ) ( ) ( ) ( ) 3-3. LED 3-4. LED

43 LED1 LED2 1 LED1 LED2 (LED1 LED2 ) ( ) 30 LED1 LED2 ( ) LED1 LED2 4.3 ( ) ( ) ( ) ( )?? (a,i,u,e,o) (k,s,t,n,h,m,y,r,w,...) 入力待ち状態 a i u e o s k a か行入力状態 i u e o a さ行入力状態 i u e o あいうえおかきくけこさしすせそ. 4.1: 43

44 電源 ON 待機状態 LED1: 点灯,LED2 点灯押しボタン入力押しボタン入力アラーム状態 LED1: 点滅,LED2 点滅カウント状態 LED1: 点灯,LED2 消灯 LED1: 消灯,LED2 点灯設定時間経過. 4.2: k (a,i,u,e,o) a ON gstate V TOMV (TCROA,TCROB)

45 LED1 LED2 LED1 P64 LED2 P65 P64 P65 LED1 LED2 / P55 P B B LED MonitorSample.c main MonitorIntprg.c (gstatus) (gcount) B1 INT TimerB1 45

46 4.5 ROM ( ) MonitorSample.c MonitorIntprg.c ROM ROM : 1. Renesas High-performance Embedded Workshop Highperformance Embedded Workshop HEW 2. OK HEW 3. OK : Application : app ( ) : app ( ) : C WorkSpace app ( ) CPU : H8S,H8/300 : Hitachi H8S,H8/300 Standard 4. -1/9-CPU 1/9 : CPU : 300H CPU : CPU CPU 5. OK ( ) iodefine.h #include iodefine.h #include iodefine.h Dependencies iodefine.h 8. ( ) WDT(WatchDog Timer) 9. app.c main intprg.c VS- WRC003 C (HEW samplemanual v0.2.pdf) p.8 VS- WRC003 mot 46

47 4.5.3 WDT(WatchDog Timer) WDT(WatchDog Timer ) WDT WDT WDT WDT 0 WDT WDT 0 WDT 0 WDT WDT WDT WDT WDT 0 WDT 0 WDT 0 WDT (H8/36064) WDT WDT ROM WDT WDT WDT H (rjj09b0049 h pdf) #include iodefine.h WDT / / / / / FILE :app.c / / DATE :xxx, xxx xx, 20xx / / DESCRIPTION :Main Program / / CPU TYPE :H8/36064 / / / / This file is generated by Renesas Project Generator (Ver.4.9). / / / / / #include "iodefine.h" / / void main(void); #ifdef cplusplus extern "C" { 47

48 void abort(void); } #endif void main(void) { / WDT OFF / WDT.TCSRWD.BYTE=0x1E; / TCSRWD write enable && WDON: 0 && WRST: 0 (HWM ) / WDT.TCSRWD.BYTE=0x80; / TCSRWD write disnable (HWM ) / WDT.TCWD=0x00; / Timer Counter Reset / } #ifdef cplusplus void abort(void) { } #endif printf 4-3. printf 4-4. ROM

49 5 PWM RC PWM DC 5-3. RC 5.2 DC PWM PWM(Pulse Width Modulation) 0(Low) 1(High) DC (1) (0) 2 DC PWM(Pulse Width Modulation ) 5.1 PWM PWM PWM 1 DC 0 DC 1 ( 1 ) 10% 10% ( 1 ) 75% 75% PWM ( ) 5.2 PWM 1 ( ) PWM 5.1 DC DC DC DC 最大出力最大出力出力 25% 周期周期出力 75% 最大出力最大出力周期アナログ値制御周期 PWM 制御. 5.1: PWM. 5.2: PWM 4 D/A D/A H8/36064 D/A 49

50 ( ) DC PWM DC (H ) LED DC DC DC DC DC 5.3 H 5.3 (SW) ON/OFF 5.3 H 4 H H ON/OFF (a) (b) (c) (d) DC DC Vm (High) Vm (High) SW1 On SW2 Off SW1 Off SW2 On SW3 Off O1 H M O2 L SW4 On SW3 On O1 L M O2 H SW4 Off GND(Low) GND(Low) (a) (b) Vm (High) Vm (High) SW1 Off SW2 Off SW1 Off SW2 Off SW3 On O1 L M O2 L SW4 On SW3 Off O1 Z M O2 Z SW4 Off GND(Low) GND(Low) (c) (d). 5.3: H, Z 50

51 H8/36064 TB6552 FTIOA0/P60 P30 P31 FTIOB0/P61 P32 P33 APWM AIN1 AIN2 BPWM BIN1 BIN2 AO1 AO2 BO1 BO2 CN1 CN2 M M DC Motor1 DC Motor2 正転逆転 TB6552 APWM AO1 AIN1 AIN2 AO2 BPWM BIN1 BIN2 BO1 BO2 VA VB VA +Vm 0 -Vm VA +Vm 0 -Vm. 5.4:. 5.5: PWM O1 O2 ( ) DC DC DC DC DC PWM DC PWM H 4 ON/OFF H H DC IC DC IC TB DC (TB6552) PWM (H8/36064) DC (TB6552) DC 5.4 DC (TB6552) 5.8 VS-WRC003 (vs-wrc003b.pdf) DC TB6552FN Table 5.8: TB6552 (DC TB6552FN ), Z IN1 IN2 PWM O1 O2 H H L H L L L L H L H L H L L L H H H L L L H L L L Z Z 51

52 ªªª ªªª ªªª ªªª ªªª WRC-003 ( マイコンボード ) Vcc GND H8/36064 FTIOC1/P66 CN10 茶 26 赤 24 オレンジ 10 Micro2BBMG GND Vcc 制御信号. 5.6: RC. 5.7: RC (TB6552FL TB6552FNG ja datasheet pdf) 5.5 IN1 IN2 PWM DC 5.3 RC RC RC RC DC DC DC GWS Micro2BBMG GWS Micro2BBMG RC PWM RC [msec] Table 5.9: GWS Micro2BBMG [msec] 0.9[msec] 60[deg] [V] 1.5[msec] 0[deg] 0.17 [sec] / 60[deg] 2.1[msec] 60[deg] 5.4 [kg cm] 52

53 ±0.6[msec] ±60[deg] 0.1[msec] 10[deg] PWM [msec] RC CN Z H8/ Z PWM Z H8/36064 Z0 Z1 2 (2 ) 2 Z x0000 0xFFFF (GRA, GRB, GRC, GRD) / Z / Z PWM V 2 (TCROA,TCROB) 1 TCROA 1 TCROB 0 Table 5.10: Z Z0 Z1 GRA0 P60/FTIOA0 GRA1 P64/FTIOA1 GRB0 P61/FTIOB0 GRB1 P65/FTIOB1 GRC0 P62/FTIOC0 GRC1 P66/FTIOC1 GRD0 P63/FTIOD0 GRD1 P67/FTIOD1 53

54 0xFFFF TCNT の値 ( カウンタの値 ) GRA 0x0000 Time FTIOA 出力 High(1) 割り込み処理割り込み処理割り込み処理 Low(0) Time. 5.8: Z Z Z0 DC (TMDR,TPMR,TFCR) TMDR,TPMR, TFCR (TCR) TCR TPSC Z /4 TPSC2 TPSC1 TPSC0 =

55 (TCR) TCR CCLR CCLR2 CCLR1 CCLR0 = (TIER,TSR) TIER TSR OVIE = 1 TSR OVF 0 (TOER) P60/FTIOA0 P61/FTIOB0 TOER P60/FTIOA0 P61/FTIOB0 EA0 = 0 EB0 = 0 (TIORA, TIORC) TIORA TIORC FTIOA FTIOB TIORA FTIOC FTIOD TIORC FTIOA0 0 IOA2 IOA1 IOA0 = FTIOB0 0 IOB2 IOB1 IOB0 = (GRA,GRB,GRC,GRD) GRA0 FTIOA0 GRB0 FTIOB0 GRA0 GRB0 0xFFFF / (TSTR) Z0 TSTR STR0 1 TSTR STR Z 0 (TSR) TSR OVF 0 1 (TOCR) TOCR FTIOA0 1 TOA0 = 1 FTIOB0 1 TOB0 = 1 55

56 5.4.5 Z 1 Z DC DC 5-2. RC 5-3. DC scanf DC 5-4. RC scanf RC DC RC USB DC RC DC RC 56

57 (QRB1134) Vstone QRB QRB1134 LED 6.1 LED 5 LED 38[KHz] (WRC-003) Vcc 100 CN 4~7 Anode(Orange) Cathode(Green) QRB1134 E H8/36064 PB0/AN0(CN4) PB1/AN1(CN5) GND 33k Emitter(Blur) Collector(White) S Reflective Surface PB2/AN2(CN6) PB3/AN3(CN7). 6.1: 5 57

58 Vin Time Vin ADC 最上位ビット MSB LSB 最下位ビット Time GND. 6.2: A/D QRB1134 (QRB1134.pdf) A/D A/D AD ADC 6.2 A/D 6.2 Vin A/D 4 A/D H8/36064 A/D H8/36064 A/D 10 8 (PB0/AN0 PB7/AN7 8 ) 5[ sec] 6 1 A/D A/D A/D A/D A/D 6 3.5[ sec] 58

59 6.2.4 A/D A/D 4 (ADDRA, ADDRB, ADDRC, ADDRD) 16 (unsigned int) H8/36064 A/D (C >> 4 ) A/D 10 A/D A/D 1. ADCSR SCAN 0 2. A/D ( ) ADCSR CH 3. A/D ADCSR ADST 1 4. A/D ADCSR ADST 1 5. A/D ADDRA, ADDRB, ADDRC ADDRD A/D 6. Table 6.11: A/D Table 6.12: A/D B 15 B 14 B 13 B 12 B 11 B 10 B 9 B 8 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 A/D b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b

60 A/D H (rjj09b0049 h pdf) A/D A/D A/D A/D A/D 1. ADCSR SCAN 0 2. A/D ( ) ADCSR CH 3. A/D ADCSR ADST 1 4. A/D A/D A/D A/D ADCSR ADST 0 A/D A/D H (rjj09b0049 h pdf) ( ) LED LED 2 2 A /B 6.5 ( ) 60

ªªª ªªª ªªªª. 6.3: v (http://www.sugilab.

61 ªªª ªªª ªªªª. 6.3: v ( 6.4: v ªª ªª ªª ªª ª ª ªª. 6.5: A /B 1/4 A B Low(0) A B High(1) ,2,4 ( ) 6.5 A (EC202A100A) [deg] 6.5 A A B A 1 3.6[deg] A [deg] A B 4 61

62 Table 6.13: A /B 1,2,4 A High(1) Low(0) High(1) Low(0) B High(1) Low(0) High(1) Low(0) (-) (+) (+) (-) (+) (-) (-) (+) [deg] , A B 1/4 A B 4 (H8/36064) 4 (H8/36064) (H8/36064) (H8/36064) (WRC-003) (H8/36064) (WRC-003) (H8/36064) P14/IRQ0, P15/IRQ1, P16/IRQ2, P17/IRQ3, P50/WKP0, P51/WKP1, P52/WKP2, P53/WKP3, P54/WKP4, P55/WKP NMI 1 62

63 H8/36064 P50/WKP0 P51/WKP1 Rotary encoder A 相 H8/36064 P50/WKP0 P51/WKP1 P70 Rotary encoder1 A 相 B 相 Rotary P52/WKP2 P53/WKP3 B 相 P52/WKP2 P53/WKP3 P71 encoder2 A 相 B 相. 6.6: : 2 2 IRQ(P14,P15,P16, P17) (WRC-003) P55/WKP5 (WRC-003) P50/WKP0, P51/WKP1, P52/WKP2, P53/WKP3, P54/WKP4 5 5 CN10 CN A B (H8/36064) A A P50/WKP0 P51/WKP1 2 P50/WKP0 P51/WKP1 B P52/WKP2 P53/WKP A 2 A B (High Low ) B B

64 MonitorIntprg.c / / / global variables / / / unsigned int genccnt1; unsigned int genccnt2; / / / interrupt functions / / / void INT WKP(void) { / 1 / if( IWPR.BIT.IWPF0 == 1 ){ / A / IWPR.BIT.IWPF0 = 0; / / if( IO.PDR7.BIT.B0 == 0 ){ genccnt1++; / / }else{ genccnt1 ; / / } } if( IWPR.BIT.IWPF1 == 1 ){ / A / IWPR.BIT.IWPF1 = 0; / / if( IO.PDR7.BIT.B0 == 0 ){ genccnt1++; / / }else{ genccnt1 ; / / } } } / 2 / if( IWPR.BIT.IWPF2 == 1 ){ / A / IWPR.BIT.IWPF2 = 0; / / if( IO.PDR7.BIT.B1 == 0 ){ genccnt2++; / / }else{ genccnt2 ; / / } } if( IWPR.BIT.IWPF3 == 1 ){ / A / IWPR.BIT.IWPF3 = 0; / / if( IO.PDR7.BIT.B1 == 0 ){ genccnt2++; / / }else{ genccnt2 ; / / } } 64

65 MonitorSample.c / / / external variables / / / extern unsigned int genccnt1; / / extern unsigned int genccnt2; / / / / / main function / / / void main(void) { set imask ccr(1); / / genccnt1 = 0; / / genccnt2 = 0; / / IO.PCR7 &= 0xFC; / P70 P71 / IEGR2.BIT.WPEG0 = 1; / WKP0: / IEGR2.BIT.WPEG1 = 0; / WKP1: / IEGR2.BIT.WPEG2 = 1; / WKP2: / IEGR2.BIT.WPEG3 = 0; / WKP2: / IWPR.BIT.IWPF0 = 0; / WKP0 / IWPR.BIT.IWPF1 = 0; / WKP1 / IWPR.BIT.IWPF2 = 0; / WKP2 / IWPR.BIT.IWPF3 = 0; / WKP3 / IENR1.BIT.IENWP = 1; / WKP0 WKP5 / set imask ccr(0); / / } for(;;){} / / 65

66 printf 6-2. printf 6-3. LED 6-4. A LED1 B LED2 printf DC 6-6. DC

67 A iodefine.h / / / / / FILE :iodefine.h / / DATE :Thu, May 14, 2009 / / DESCRIPTION :Definition of I/O Register / / CPU TYPE :H8/36064 / / / / This file is generated by Renesas Project Generator (Ver.4.9). / / / / / #ifndef IODEFINE #define IODEFINE / / / H8/36064 Series Include File Ver 2.0 / / / struct st tz0 { / struct TZ0 / union { / TCR / unsigned char CCLR:3; / CCLR / unsigned char CKEG:2; / CKEG / unsigned char TPSC:3; / TPSC / } TCR; / / union { / TIORA / unsigned char :1; / / unsigned char IOB:3; / IOB / unsigned char :1; / / unsigned char IOA:3; / IOA / } TIORA; / / union { / TIORC / unsigned char :1; / / unsigned char IOD:3; / IOD / unsigned char :1; / / unsigned char IOC:3; / IOC / } TIORC; / / union { / TSR / unsigned char :3; / / unsigned char OVF :1; / OVF / unsigned char IMFD:1; / IMFD / unsigned char IMFC:1; / IMFC / unsigned char IMFB:1; / IMFB / unsigned char IMFA:1; / IMFA / } TSR; / / union { / TIER / unsigned char :3; / / unsigned char OVIE :1; / OVIE / unsigned char IMIED:1; / IMIED / unsigned char IMIEC:1; / IMIEC / unsigned char IMIEB:1; / IMIEB / unsigned char IMIEA:1; / IMIEA / } TIER; / / union { / POCR / unsigned char :5; / / unsigned char POLD:1; / POLD / unsigned char POLC:1; / POLC / unsigned char POLB:1; / POLB / } POCR; / / unsigned int TCNT; / TCNT / unsigned int GRA; / GRA / unsigned int GRB; / GRB / unsigned int GRC; / GRC / unsigned int GRD; / GRD / }; / / struct st tz1 { / struct TZ1 / union { / TCR / unsigned char CCLR:3; / CCLR / 67

68 unsigned char CKEG:2; / CKEG / unsigned char TPSC:3; / TPSC / } TCR; / / union { / TIORA / unsigned char :1; / / unsigned char IOB:3; / IOB / unsigned char :1; / / unsigned char IOA:3; / IOA / } TIORA; / / union { / TIORC / unsigned char :1; / / unsigned char IOD:3; / IOD / unsigned char :1; / / unsigned char IOC:3; / IOC / } TIORC; / / union { / TSR / unsigned char :2; / / unsigned char UDF :1; / UDF / unsigned char OVF :1; / OVF / unsigned char IMFD:1; / IMFD / unsigned char IMFC:1; / IMFC / unsigned char IMFB:1; / IMFB / unsigned char IMFA:1; / IMFA / } TSR; / / union { / TIER / unsigned char :3; / / unsigned char OVIE :1; / OVIE / unsigned char IMIED:1; / IMIED / unsigned char IMIEC:1; / IMIEC / unsigned char IMIEB:1; / IMIEB / unsigned char IMIEA:1; / IMIEA / } TIER; / / union { / TOCR / unsigned char :5; / / unsigned char POLD:1; / POLD / unsigned char POLC:1; / POLC / unsigned char POLB:1; / POLB / } POCR; / / unsigned int TCNT; / TCNT / unsigned int GRA; / GRA / unsigned int GRB; / GRB / unsigned int GRC; / GRC / unsigned int GRD; / GRD / }; / / struct st tz { / struct TZ / union { / TSTR / unsigned char :6; / / unsigned char STR1:1; / STR1 / unsigned char STR0:1; / STR0 / } TSTR; / / union { / TMDR / unsigned char BFD1:1; / BFD1 / unsigned char BFC1:1; / BFC1 / unsigned char BFD0:1; / BFD0 / unsigned char BFC0:1; / BFC0 / unsigned char :3; / / unsigned char SYNC:1; / SYNC / } TMDR; / / union { / TPMR / unsigned char :1; / / unsigned char PWMD1:1; / PWMD1 / unsigned char PWMC1:1; / PWMC1 / unsigned char PWMB1:1; / PWMB1 / unsigned char :1; / / unsigned char PWMD0:1; / PWMD0 / unsigned char PWMC0:1; / PWMC0 / unsigned char PWMB0:1; / PWMB0 / 68

69 } TPMR; / / union { / TFCR / unsigned char :1; / / unsigned char STCLK:1; / STCLK / unsigned char ADEG :1; / ADEG / unsigned char ADTRG:1; / ADTRG / unsigned char OLS1 :1; / OLS1 / unsigned char OLS0 :1; / OLS0 / unsigned char CMD :2; / CMD / } TFCR; / / union { / TOER / unsigned char ED1:1; / ED1 / unsigned char EC1:1; / EC1 / unsigned char EB1:1; / EB1 / unsigned char EA1:1; / EA1 / unsigned char ED0:1; / ED0 / unsigned char EC0:1; / EC0 / unsigned char EB0:1; / EB0 / unsigned char EA0:1; / EA0 / } TOER; / / union { / TOCR / unsigned char TOD1:1; / TOD1 / unsigned char TOC1:1; / TOC1 / unsigned char TOB1:1; / TOB1 / unsigned char TOA1:1; / TOA1 / unsigned char TOD0:1; / TOD0 / unsigned char TOC0:1; / TOC0 / unsigned char TOB0:1; / TOB0 / unsigned char TOA0:1; / TOA0 / } TOCR; / / }; / / struct st lvd { / struct LVD / union { / LVDCR / unsigned char LVDE :1; / LVDE / unsigned char :3; / / unsigned char LVDSEL:1; / LVDSEL / unsigned char LVDRE :1; / LVDRE / unsigned char LVDDE :1; / LVDDE / unsigned char LVDUE :1; / LVDUE / } CR; / / union { / LVDSR / unsigned char :6; / / unsigned char LVDDF:1; / LVDDF / unsigned char LVDUF:1; / LVDUF / } SR; / / }; / / struct st sci3 { / struct SCI3 / union { / SMR / unsigned char COM :1; / COM / unsigned char CHR :1; / CHR / unsigned char PE :1; / PE / unsigned char PM :1; / PM / unsigned char STOP:1; / STOP / unsigned char MP :1; / MP / unsigned char CKS :2; / CKS / } SMR; / / unsigned char BRR; / BRR / union { / SCR3 / unsigned char TIE :1; / TIE / unsigned char RIE :1; / RIE / unsigned char TE :1; / TE / unsigned char RE :1; / RE / unsigned char MPIE:1; / MPIE / unsigned char TEIE:1; / TEIE / unsigned char CKE :2; / CKE / } SCR3; / / unsigned char TDR; / TDR / union { / SSR / 69

70 unsigned char TDRE:1; / TDRE / unsigned char RDRF:1; / RDRF / unsigned char OER :1; / OER / unsigned char FER :1; / FER / unsigned char PER :1; / PER / unsigned char TEND:1; / TEND / unsigned char MPBR:1; / MPBR / unsigned char MPBT:1; / MPBT / } SSR; / / unsigned char RDR; / RDR / }; / / struct st iic2 { / struct IIC2 / union { / ICCR1 / unsigned char ICE :1; / ICE / unsigned char RCVD:1; / RCVD / unsigned char MST :1; / MST / unsigned char TRS :1; / TRS / unsigned char CKS :4; / CKS / } ICCR1; / / union { / ICCR2 / unsigned char BBSY :1; / BBSY / unsigned char SCP :1; / SCP / unsigned char SDAO :1; / SDAO / unsigned char SDAOP :1; / SDAOP / unsigned char SCLO :1; / SCLO / unsigned char :1; / / unsigned char IICRST:1; / IICRST / } ICCR2; / / union { / ICMR / unsigned char MLS :1; / MLS / unsigned char WAIT:1; / WAIT / unsigned char :2; / / unsigned char BCWP:1; / BCWP / unsigned char BC :3; / BC / } ICMR; / / union { / ICIER / unsigned char TIE :1; / TIE / unsigned char TEIE :1; / TEIE / unsigned char RIE :1; / RIE / unsigned char NAKIE:1; / NAKIE / unsigned char STIE :1; / STIE / unsigned char ACKE :1; / ACKE / unsigned char ACKBR:1; / ACKBR / unsigned char ACKBT:1; / ACKBT / } ICIER; / / union { / ICSR / unsigned char TDRE :1; / TDRE / unsigned char TEND :1; / TEND / unsigned char RDRF :1; / RDRF / unsigned char NACKF:1; / NACKF / unsigned char STOP :1; / STOP / unsigned char ALOVE:1; / ALOVE / unsigned char AAS :1; / AAS / unsigned char ADZ :1; / ADZ / } ICSR; / / union { / SAR / unsigned char SVA:7; / SVA / unsigned char FS :1; / FS / } SAR; / / unsigned char ICDRT; / ICDRT / unsigned char ICDRR; / ICDRR / }; / / struct st tb1 { / struct TB1 / union { / TMB1 / unsigned char RLD:1; / RLD / unsigned char :4; / / unsigned char CKS:3; / CKS / } TMB1; / / 70

71 unsigned char TCB1; / TCB1 / }; / / struct st flash { / struct FLASH / union { / FLMCR1 / unsigned char :1; / / unsigned char SWE:1; / SWE / unsigned char ESU:1; / ESU / unsigned char PSU:1; / PSU / unsigned char EV :1; / EV / unsigned char PV :1; / PV / unsigned char E :1; / E / unsigned char P :1; / P / } FLMCR1; / / union { / FLMCR2 / unsigned char FLER:1; / FLER / } FLMCR2; / / char wk1; / / union { / EBR1 / unsigned char :3; / / unsigned char EB4:1; / EB4 / unsigned char EB3:1; / EB3 / unsigned char EB2:1; / EB2 / unsigned char EB1:1; / EB1 / unsigned char EB0:1; / EB0 / } EBR1; / / char wk2[7]; / / union { / FENR / unsigned char FLSHE:1; / FLSHE / } FENR; / / }; / / struct st tv { / struct TV / union { / TCRV0 / unsigned char CMIEB:1; / CMIEB / unsigned char CMIEA:1; / CMIEA / unsigned char OVIE :1; / OVIE / unsigned char CCLR :2; / CCLR / unsigned char CKS :3; / CKS / } TCRV0; / / union { / TCSRV / unsigned char CMFB:1; / CMFB / unsigned char CMFA:1; / CMFA / unsigned char OVF :1; / OVF / unsigned char :1; / / unsigned char OS :4; / OS / } TCSRV; / / unsigned char TCORA; / TCORA / unsigned char TCORB; / TCORB / unsigned char TCNTV; / TCNT / union { / TCRV1 / unsigned char :3; / / unsigned char TVEG:2; / TVEG / unsigned char TRGE:1; / TRGE / unsigned char :1; / / unsigned char ICKS:1; / ICKS / } TCRV1; / / }; / / struct st ad { / struct A/D / unsigned int ADDRA; / ADDRA / unsigned int ADDRB; / ADDRB / unsigned int ADDRC; / ADDRC / unsigned int ADDRD; / ADDRD / union { / ADCSR / unsigned char ADF :1; / ADF / unsigned char ADIE:1; / ADIE / unsigned char ADST:1; / ADST / unsigned char SCAN:1; / SCAN / unsigned char CKS :1; / CKS / unsigned char CH :3; / CH / 71

72 } ADCSR; / / union { / ADCR / unsigned char TRGE:1; / TRGE / } ADCR; / / }; / / struct st pwm { / struct PWM / unsigned char PWDRL; / PWDRL / unsigned char PWDRU; / PWDRU / union { / PWCR / unsigned char :7; / / unsigned char CKS:1; / CKS / } PWCR; / / }; / / struct st wdt { / struct WDT / union { / TCSRWD / unsigned char B6WI :1; / B6WI / unsigned char TCWE :1; / TCWE / unsigned char B4WI :1; / B4WI / unsigned char TCSRWE:1; / TCSRWE / unsigned char B2WI :1; / B2WI / unsigned char WDON :1; / WDON / unsigned char B0WI :1; / B0WI / unsigned char WRST :1; / WRST / } TCSRWD; / / unsigned char TCWD; / TCWD / union { / TMWD / unsigned char :4; / / unsigned char CKS:4; / CKS / } TMWD; / / }; / / struct st abrk { / struct ABRK / union { / ABRKCR / unsigned char RTINTE:1; / RTINTE / unsigned char CSEL :2; / CSEL / unsigned char ACMP :3; / ACMP / unsigned char DCMP :2; / DCMP / } CR; / / union { / ABRKSR / unsigned char ABIF:1; / ABIF / unsigned char ABIE:1; / ABIE / } SR; / / void BAR; / BAR / unsigned int BDR; / BDR / }; / / struct st io { / struct IO / union { / PUCR1 / unsigned char B7:1; / Bit 7 / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / unsigned char B4:1; / Bit 4 / unsigned char :1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PUCR1; / / union { / PUCR5 / unsigned char :2; / Bit 7,6 / unsigned char B5:1; / Bit 5 / unsigned char B4:1; / Bit 4 / unsigned char B3:1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PUCR5; / / char wk1[2]; / / union { / PDR1 / 72

73 unsigned char B7:1; / Bit 7 / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / unsigned char B4:1; / Bit 4 / unsigned char :1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PDR1; / / union { / PDR2 / unsigned char :3; / Bit 7-5 / unsigned char B4:1; / Bit 4 / unsigned char B3:1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PDR2; / / union { / PDR3 / unsigned char B7:1; / Bit 7 / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / unsigned char B4:1; / Bit 4 / unsigned char B3:1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PDR3; / / char wk2; / / union { / PDR5 / unsigned char B7:1; / Bit 7 / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / unsigned char B4:1; / Bit 4 / unsigned char B3:1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PDR5; / / union { / PDR6 / unsigned char B7:1; / Bit 7 / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / unsigned char B4:1; / Bit 4 / unsigned char B3:1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PDR6; / / union { / PDR7 / unsigned char :1; / / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / unsigned char B4:1; / Bit 4 / unsigned char :1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PDR7; / / union { / PDR8 / unsigned char B7:1; / Bit 7 / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / } PDR8; / / char wk3; / / union { / PDRB / unsigned char B7:1; / Bit 7 / unsigned char B6:1; / Bit 6 / unsigned char B5:1; / Bit 5 / 73

74 unsigned char B4:1; / Bit 4 / unsigned char B3:1; / Bit 3 / unsigned char B2:1; / Bit 2 / unsigned char B1:1; / Bit 1 / unsigned char B0:1; / Bit 0 / } PDRB; / / char wk4[2]; / / union { / PMR1 / unsigned char IRQ3:1; / IRQ3 / unsigned char IRQ2:1; / IRQ2 / unsigned char IRQ1:1; / IRQ1 / unsigned char IRQ0:1; / IRQ0 / unsigned char TXD2:1; / TXD2 / unsigned char PWM:1; / PMW / unsigned char TXD :1; / TXD / } PMR1; / / union { / PMR5 / unsigned char :2; / / unsigned char WKP5:1; / WKP5 / unsigned char WKP4:1; / WKP4 / unsigned char WKP3:1; / WKP3 / unsigned char WKP2:1; / WKP2 / unsigned char WKP1:1; / WKP1 / unsigned char WKP0:1; / WKP0 / } PMR5; / / union { / PMR3 / unsigned char :3; / / unsigned char POF4:1; / POF4 / unsigned char POF3:1; / POF3 / } PMR3; / / char wk5; / / unsigned char PCR1; / PCR1 / unsigned char PCR2; / PCR2 / unsigned char PCR3; / PCR3 / char wk6; / / unsigned char PCR5; / PCR5 / unsigned char PCR6; / PCR6 / unsigned char PCR7; / PCR7 / unsigned char PCR8; / PCR8 / }; / / union un syscr1 { / union SYSCR1 / unsigned char SSBY :1; / SSBY / unsigned char STS :3; / STS / }; / / union un syscr2 { / union SYSCR2 / unsigned char SMSEL:1; / SMSEL / unsigned char :1; / / unsigned char DTON :1; / DTON / unsigned char MA :3; / MA / }; / / union un iegr1 { / union IEGR1 / unsigned char NMIEG:1; / NMIEG / unsigned char :3; / / unsigned char IEG3 :1; / IEG3 / unsigned char IEG2 :1; / IEG2 / unsigned char IEG1 :1; / IEG1 / unsigned char IEG0 :1; / IEG0 / }; / / union un iegr2 { / union IEGR2 / unsigned char :2; / / unsigned char WPEG5:1; / WPEG5 / unsigned char WPEG4:1; / WPEG4 / unsigned char WPEG3:1; / WPEG3 / unsigned char WPEG2:1; / WPEG2 / unsigned char WPEG1:1; / WPEG1 / unsigned char WPEG0:1; / WPEG0 / }; / / union un ienr1 { / union IENR1 / 74

75 unsigned char IENDT:1; / IENDT / unsigned char :1; / / unsigned char IENWP:1; / IENWP / unsigned char :1; / / unsigned char IEN3 :1; / IEN3 / unsigned char IEN2 :1; / IEN2 / unsigned char IEN1 :1; / IEN1 / unsigned char IEN0 :1; / IEN0 / }; / / union un ienr2 { / union IENR2 / unsigned char :2; / / unsigned char IENTB1:1; / IENTB1 / }; / / union un irr1 { / union IRR1 / unsigned char IRRDT:1; / IRRDT / unsigned char :3; / / unsigned char IRRI3:1; / IRRI3 / unsigned char IRRI2:1; / IRRI2 / unsigned char IRRI1:1; / IRRI1 / unsigned char IRRI0:1; / IRRI0 / }; / / union un irr2 { / union IRR2 / unsigned char :2; / / unsigned char IRRTB1:1; / IRRTB1 / }; / / union un iwpr { / union IWPR / unsigned char :2; / / unsigned char IWPF5:1; / IWPF5 / unsigned char IWPF4:1; / IWPF4 / unsigned char IWPF3:1; / IWPF3 / unsigned char IWPF2:1; / IWPF2 / unsigned char IWPF1:1; / IWPF1 / unsigned char IWPF0:1; / IWPF0 / }; / / union un mstcr1 { / union MSTCR1 / unsigned char :1; / / unsigned char MSTIIC:1; / MSTIIC / unsigned char MSTS3 :1; / MSTS3 / unsigned char MSTAD :1; / MSTAD / unsigned char MSTWD :1; / MSTWD / unsigned char :1; / / unsigned char MSTTV :1; / MSTTV / }; / / union un mstcr2 { / union MSTCR2 / unsigned char MSTS3 2:1; / MSTS3 2 / unsigned char :2; / / unsigned char MSTTB1 :1; / MSTTB1 / unsigned char :2; / / unsigned char MSTTZ :1; / MSTTZ / unsigned char MSTPWM :1; / MSTPWM / }; / / #define TZ0 ( (volatile struct st tz0 )0xF700) / TZ0 Address / #define TZ1 ( (volatile struct st tz1 )0xF710) / TZ1 Address / #define TZ ( (volatile struct st tz )0xF720) / TZ Address / #define LVD ( (volatile struct st lvd )0xF730) / LVD Address / #define SCI3 2 ( (volatile struct st sci3 )0xF740) / SCI3 2Address / #define IIC2 ( (volatile struct st iic2 )0xF748) / IIC2 Address / #define TB1 ( (volatile struct st tb1 )0xF760) / TB1 Address / #define FLASH ( (volatile struct st flash )0xFF90) / FLASH Address / #define TV ( (volatile struct st tv )0xFFA0) / TV Address / #define SCI3 ( (volatile struct st sci3 )0xFFA8) / SCI3 Address / #define AD ( (volatile struct st ad )0xFFB0) / A/D Address / #define PWM ( (volatile struct st pwm )0xFFBC) / PWM Address / #define WDT ( (volatile struct st wdt )0xFFC0) / WDT Address / #define ABRK ( (volatile struct st abrk )0xFFC8) / ABRK Address / #define IO ( (volatile struct st io )0xFFD0) / IO Address / #define SYSCR1 ( (volatile union un syscr1 )0xFFF0) / SYSCR1Address / #define SYSCR2 ( (volatile union un syscr2 )0xFFF1) / SYSCR2Address / #define IEGR1 ( (volatile union un iegr1 )0xFFF2) / IEGR1 Address / #define IEGR2 ( (volatile union un iegr2 )0xFFF3) / IEGR2 Address / #define IENR1 ( (volatile union un ienr1 )0xFFF4) / IENR1 Address / 75

76 #define IENR2 ( (volatile union un ienr2 )0xFFF5) / IENR2 Address / #define IRR1 ( (volatile union un irr1 )0xFFF6) / IRR1 Address / #define IRR2 ( (volatile union un irr2 )0xFFF7) / IRR2 Address / #define IWPR ( (volatile union un iwpr )0xFFF8) / IWPR Address / #define MSTCR1 ( (volatile union un mstcr1 )0xFFF9) / MSTCR1Address / #define MSTCR2 ( (volatile union un mstcr2 )0xFFFA) / MSTCR2Address / #define TLB1 TCB1 / Change TLB1 > TCB1 / #endif 76

MechLab.dvi

MechLab.dvi Rev. 1.11, Jan. 2010 mtanaka@ctrl.titech.ac.jp torii@ctrl.titech.ac.jp 0 5 0.1 3 310 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 0.2 : : : : : : : : : : : : : : : : : : : : : : : : :