SH7734グループ　SH7734初期設定例　アプリケーションノート

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1 R01AN0665JJ0101 Rev.1.01 CS0 CS0 NAND MMC esd HIF CS0 NOR SH-4A SH7730 RJJ06B0864 SH-4A SH SH7730 RJJ06B0864 R8A77343 SH7734 R01UH0233JJ R01AN0665JJ0101 Rev.1.01 Page 1 of 27

2 1. CPGLBSC DBSC3 7. SH7734 R0P7734C00000RZ LED SH CPG FPU LBSC DBSC3 GPIO SCIF TMU MTU2 ADC CPG R01UH0233JJ CPG 0 NOR JS28F512M29EWLA ( Numonyx ) x 1 16 SRAM R01UH0233JJ LBSC 2 3 DDR2-SDRAM MT47H64M16HR-3 ( Micron ) x 1 16 R01UH0233JJ DBSC3 LED puts printf R01AN0665JJ0101 Rev.1.01 Page 2 of 27

3 _Reset_handler WDT vhandler.src vecttbl.src vect.inc MMU FPSCR CPG END _io_init_dbsc3 DBSC3 DDR2-SDRAM 2 3 END io_lbsc.src io_dbsc3.src stacksct.h intprg.c _io_init_lbsc LBSC NOR 0 END PowerON_Reset() SCIF resetprg.c io_siochar.c siorw.c lowsrc.c VBR InitSct() _INIT_IOLIB() dbsct.c io_cache.c main() END sh7734_main.c SR main() sleep() END 1.1 R01AN0665JJ0101 Rev.1.01 Page 3 of 27

4 SH7734 R8A77343 EXTAL : MHz CPU clki400mhz SHwy clks200mhz SHwy clks1100mhz DDR MCK0/MCK0#/MCK1/MCK1#200MHz clkb50mhz clkp50mhz IO supply power 3.3V Core supply power 1.25V High-performance Embedded Workshop (Version ) C C/C++ Compiler Package for SuperH Family (V.9.04 release00) -cpu=sh4a -endian=little -include="$(projdir) inc" -change_message=warning -object="$(configdir) $(FILELEAF).obj" -debug -optimize=0 -gbr=auto -chgincpath -errorpath -global_volatile=0 -opt_range=all -infinite_loop=0 -del_vacant_loop=0 -struct_alloc=1 -nologo Ver 1.01 CS0 29 MMU WDT SH7734 R0P7734C00000RZ 3. SH7730 SH7730 RJJ06B0864 SH7730 SH7730 TMU RJJ06B0997 SH7730 SH7730 SCIF RJJ06B0954 SH7730 SH7730 ADC RJJ06B1088 R01AN0665JJ0101 Rev.1.01 Page 4 of 27

5 4. R01UH0233JJ SH7734 R0P7734C00000RZ 4.1 MD MD0 MD0=0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD9 400MHz 2 MD0=0 MD1=0 MD2=0 MD4 MD3 0 MD3=0 16 MD5=0 MD6=1 0 MD7=0 MD8=0 * 1 MD8 MD8=1 MD10 EXTAL MD10=0 MD11 MD12 12 MD11=0 MD12=0 MD13 29 MD13=0 MD14 CS0 MD16 MD14=0 MD16=0 MD17 MD17=0 MD18=0 MD18 MD19=0 MD19 PLL1 29/32 MD15 MD15=0 MD15=0 * 2 SH7734 CS0 NAND NAND *1 CPU LBSC R01UH0233JJLBSC *2 R01UH0233JJ R01AN0665JJ0101 Rev.1.01 Page 5 of 27

6 LBSC A[25:0] * DBSC3 D[15:0] CS0# CKO RD# RD/WR# WE1# WE0# WAIT# BS# CS1#/A26 EX_CS5~0# EX_WAIT0 2 DACK0 1 DREQ0 1 DRACK0 MCK0 MCK0# MCK0 MCKE CKE MCS# MWE# MRAS# MCAS# MA[13:0] MBA[2:0] MDQ[15:0] MDQS1 MDQS0 MDQS1# MDQS0# MDQS1 MDQ0 MDM1, MDM0 MODT SDRAM ODT MZQ VSS MRESET# DDR3-SDRAM DDR2-SDRAM SDBUP DDR2-SDRAM SDSELF DDR DDR MVREFCA GND R01AN0665JJ0101 Rev.1.01 Page 6 of 27

7 SCIF3 TXD RXD GPIO GP1[15] LED4 GP1[22] LED5 AD AN0 PS3 5 AN1 PS6 8 AN2 PS H-UDI LSI LSI LSI PULL_UP PULL_UP * GP0[25] GP0[26] GPIO fmtool A24 A25.hdc 5.2 SH7734 R0P7734C00000RZ R01AN0665JJ0101 Rev.1.01 Page 7 of 27

8 C R01AN0665JJ0101 Rev.1.01 Page 8 of 27

9 _ResetHandler H'A MMU MMU IC V OC V U 0 0 CPG STIF clks2 MD EXTAL STIF clks2lsi LBSC NOR-FLASH _io_init_lbsc MD7=0 MD9=0 0 SRAM NOR-FLASH 16 LBSC-DMAC ROM ATA EX_BUS PIO SuperHyway LBSC-DMAC LBSCILIL R01UH0233JJ LBSC LSILSI LSIPULL_UPPULL_UP DBSC3 DDR2-SDRAM _io_init_dbsc3 R01UH0233JJ DBSC R01AN0665JJ0101 Rev.1.01 Page 9 of 27

10 PowerON_Reset() VBR set_vbr() SH-4A VBR + H'100 - H'100 VBR ROM RAM DR B InitSct() P RAM io_cache_set_ccr() ROM RAMInitSct() ROM RAMInitSct() _INIT_IOLIB() puts printf_init_iolib SCIF3 _INIT_IOLIBlowsrc.c SR set_cr() BLIMASK RB1 RB0 main() sleep() END R01AN0665JJ0101 Rev.1.01 Page 10 of 27

11 vhandler.src vecttbl.src resetprg.c dbsct.c sh7734_main.c intprg.c vect.inc sbrk.c sbrk.h stacksct.h env.inc typedefine.h io_cache.c io_cache.h iodefine.h io_lbsc.src io_dbsc3.src lowsrc.c lowsrc.h io_siorw.c io_siochar.c io_led.c io_led.h io_key.c io_key.h io_tmu.c io_tmu.h rop7734c00000rz.h C PowerON_Reset() B 0 D R ROM RAM main().global SH7734 iodefine.h NOR 0 DDR2-SDRAM 2 3 _INIT_IOLIB LED SH7730 SH7730 RJJ06B0864 SuperH RISC engine C/C++ RJJ05B0557 SH7730 RJJ06B0868 SuperH RISC engine C/C++ RJJ05B0557 R01AN0665JJ0101 Rev.1.01 Page 11 of 27

12 IMASKclr H'FFFFFF0F SR IMASK vhandler.src RBBLclr vhandler.src H'CFFFFFFF SR RB BL MDRBBLset vhandler.src SR_Init vhandler.src INT_OFFSET vhandler.src D_CACHE_OFF io_cache.h D_CACHE_I_INVALID io_cache.h D_CACHE_I_ON io_cache.h D_CACHE_O_INVALID io_cache.h D_CACHE_O_ON io_cache.h D_CACHE_IO_ON io_cache.h D_CACHE_O_WT io_cache.h H' H' H' H' H' H' H' H' (CACHE_I_ON CACHE_O_ON) H' SR MD RB BL main() SR VBR CCR CCR ICI IC V 0 CCR ICE CCR OCI OC V U 0 CCR OCE R01AN0665JJ0101 Rev.1.01 Page 12 of 27

13 ROM RAM 6.3 P* 3 ROM H' P0 C ROM P$PSEC* 4 ROM MMU C$BSEC ROM C$DSEC ROM D ROM B RAM H'0C R RAM PRAM* 3 ROM P RAM S RAM 0x0FFFF9F0 PINTHandler* 5 ROM H' VECTTBL ROM INTTBL* 5 ROM PIntPRG* 5 ROM SP_S* 1 TLB RAM H'8FFFFDF0 RSTHandler ROM H'A PResetPRG ROM P_LBSC_ROM* 6 ROM LBSC ROM P_DBSC3_ROM* 6 ROM DBSC3 ROM PnonCache* 2 ROM P1 MMU P2 MMU INTTBL_OL* 5 RAM H'E500E000 OL PINTHandler_IL* 5 RAM H'E IL PIntPRG_IL* 5 RAM P_LBSC_IL* 6 ROM LBSC RAM *1 SH7730 SH7730 RJJ06B0864 *2 SH7730 SH7730 RJJ06B0864 *3 P NOR PRAM SDRAM *4 *3 _INITSCT() _INITSCT()P _INITSCT()ROM RAM P ROM PRAM RAM _INITSCT() _INITSCT() PRAM RAM _INITSCT() _INITSCT() InitSct() P$PSEC ROM R01AN0665JJ0101 Rev.1.01 Page 13 of 27

14 *5 IL INTTBL OL *6 LBSC DBSC3 ROM 0 IL 0 LBSC 0 DBSC ROM RAM ROM RAM P NOR PRAM SDRAM D NOR R SDRAM PINTHandler NOR PINTHandler_IL IL PIntPRG NOR PIntPRG_IL IL P_LBSC_ROM NOR P_LBSC_IL IL INTTBL NOR INTTBL_OL OL R01AN0665JJ0101 Rev.1.01 Page 14 of 27

7. SH7734 R0P7734C00000RZ 7.1 LED LED LED4 LED5 7.1 LED 7.1.1 7.1 LED main() 7.

15 7. SH7734 R0P7734C00000RZ 7.1 LED LED LED4 LED5 7.1 LED LED main() 7.1 LED io_led_init io_led_on io_led_off GP1[15] LED4GP1[22] LED5 LED ON LED OFF R01AN0665JJ0101 Rev.1.01 Page 15 of 27

16 7.1.2 io_led_init GP1[15] GP1[22] io_led.h void io_led_init(void) GP1[15] GP1[22] io_led_on LED ON io_led.h void io_led_on(e_id_user_led ledno) LED ON LED4 LED5 ON ledno D_ID_USER_LED4 LED4 ON D_ID_USER_LED5 LED5 ON D_ID_USER_LED_ALL LED4 LED5 ON io_led_off LED OFF io_led.h void io_led_off(e_id_user_led ledno) LED OFF LED4 LED5 OFF ledno D_ID_USER_LED4 LED4 OFF D_ID_USER_LED5 LED5 OFF D_ID_USER_LED_ALL LED4 LED5 OFF R01AN0665JJ0101 Rev.1.01 Page 16 of 27

17 7.1.3 void main(void) { } /* */ io_led_init(); io_led_on(d_id_user_led4); /* LED4 ON */ io_led_on(d_id_user_led5); /* LED5 ON */ io_led_off(d_id_user_led4); /* LED5 OFF */ io_led_off(d_id_user_led5); /* LED5 OFF */ io_led_on(d_id_user_led_all); /* LED4,5 ON */ io_led_off(d_id_user_led_all); /* LED4,5 OFF */ R01AN0665JJ0101 Rev.1.01 Page 17 of 27

18 7.2 (SCIF3) SCIF3 PC 7.2 (SCIF3) puts get printf SCIF3 _INIT_IOLIB lowsrc.c bps 8 1 R01AN0665JJ0101 Rev.1.01 Page 18 of 27

19 7.2.3 void main(void) { } puts( "" ); puts(" nsh7734 Sample Program. Ver "); puts("copyright (C) 2011 Renesas Electronics Corp. All Rights Reserved"); puts("and Renesas Solutions Corp. All Rights Reserved"); puts( "" ); printf("test sample n"); fflush(stdout); R01AN0665JJ0101 Rev.1.01 Page 19 of 27

20 7.3 TMU io_tmu0_create io_tmu0_start io_tmu0_stop io_tmu0_compare_match TMU io_tmu0_create TMU0 io_tmu.h void io_tmu0_create(t_tmu_timertype *i_ptimertype) i_ptimertype io_tmu0_start io_tmu0_stop io_tmu.h void tmu0_start(t_tmu_settcor_info *i_ptcorinfo, TMU_TIMEOUT_CALLBACK i_func) i_ptcorinfo TCOR i_func ms 1ms 1000ms 1ms io_tmu.h void tmu0_stop(void) R01AN0665JJ0101 Rev.1.01 Page 20 of 27

21 io_tmu0_compare_match io_tmu.h void tmu0_compare_match(void) io_tmu0_start() R01AN0665JJ0101 Rev.1.01 Page 21 of 27

22 ms LED led_onoff() /* */ void main(void) { T_TMU_TimerTYPE T_TMU_SETTCOR_INFO TimerType; SetTCORInfo; memset(&timertype, 0x00, sizeof(timertype)); memset(&settcorinfo, 0x00, sizeof(settcorinfo)); io_led_init(); /* LED */ /* */ TimerType.mClockSelect = D_TMU_DIV_64; /* clkp /64 */ TimerType.mIntcPri = D_TMU_PRI_1; /* 1 */ /* TMU0 */ io_tmu0_create(&timertype); /* */ SetTCORInfo.mTimeValue = 500; /* (500ms) */ /* TMU0 */ io_tmu0_start(&settcorinfo, led_onoff); } /* */ void INT_TMU00(void) { io_tmu0_compare_match(); } /* */ void led_onoff(void) { if(g_onoff == 0) { io_led_on(d_id_user_led4); g_onoff = 1; } else { io_led_off(d_id_user_led4); g_onoff = 0; } } R01AN0665JJ0101 Rev.1.01 Page 22 of 27

23 main() SH7734 R0P7734C00000RZ ADC Push AN0 AN2 ADC AN0 AN2 MTU2 10ms A/D A/D A/D Push Push PS9 PS11 > PS6 PS8 > PS3 PS5 7.4 io_key_init io_key_start io_key_stop io_key_int MTU2 ADC MTU2 MTU2 10ms A/D MTU AD R01AN0665JJ0101 Rev.1.01 Page 23 of 27

24 7.4.2 io_key_init MTU2 ADC io_key.h void io_key_init(t_key_mtx *key_mtx) MTU2 ADC Push *key_mtx io_key_start MTU2 MTU2 10ms A/D io_key.h void io_key_start(void) MTU2 10ms MTU2 10ms AD io_key_stop MTU2 AD io_key.h void io_key_stop(void) MTU2 AD io_key_int ADC io_key.h void io_key_int(void) AN0 AN2 A/D Push ADC SH7734 R0P7734C00000RZ R01AN0665JJ0101 Rev.1.01 Page 24 of 27

25 Push LED4 8 Push LED4 /* 0 Push */ void Key_0(void) { io_led_on(d_id_user_led4); } /* 8 Push */ void Key_8(void) { io_led_off(d_id_user_led4); } /* */ static T_KEY_MTX t_key_tbl[e_key_flg_max] = { Key_0, NULL, /* */ NULL, /* */ NULL, /* */ NULL, /* */ NULL, /* */ NULL, /* */ NULL, /* */ Key_8, } /* */ void main(void) { /* LED */ io_led_init(); } /* */ io_key_init(t_key_tbl); /* */ io_key_start(); /* */ void INT_ADC (void) { /* */ io_key_int(); } R01AN0665JJ0101 Rev.1.01 Page 25 of 27

26 8. 9. (R01UH0233JJ) Rev.1.00 C SuperH C/C++ V.9.04 Rev.1.00 R01AN0665JJ0101 Rev.1.01 Page 26 of 27

27 R01AN0665JJ0101 Rev.1.01 Page 27 of 27

28 Rev A-1

29 1. CMOS LSI LSI 2. LSI

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