3. & SII51003-4.0 IEEE Std. 1149.1 JTAG Stratix II IEEE Std. 1149.1 JTAG BST JTAG Stratix II Quartus II Jam.jam Jam Byte-Code.jbc JTAG Stratix II JTAG BST IOE I/O JTAG CONFIG_IO I/O Stratix II JTAG Stratix II JTAG I/O JTAG I/O I/O JTAG TDI TDO TMS TCK 4 TRST 1 TCK TDI TMS TRST JTAG 3.3 V VCCPD TDO 4 V CCIO Stratix II SignalTap JTAG Stratix II 3 1 JTAG Altera Corporation 3 1
Stratix II, Volume 1 Stratix II Stratix Cyclone II Cyclone JTAG 17 JTAG Stratix II Stratix Cyclone II Cyclone 18 SignalTap II Stratix II 10 USERCODE 32 3 2 3 3 Stratix II IDCODE 3 1. Stratix II JTAG ( / ) JTAG SAMPLE/PRELOAD 00 0000 0101 SignalTap II EXTEST(1) 00 0000 1111 BYPASS 11 1111 1111 TDI TDO 1 BST USERCODE 00 0000 0111 32 USERCODE TDI TDO USERCODE TDO IDCODE 00 0000 0110 IDCODE TDI TDO IDCODE TDO HIGHZ (1) 00 0000 1011 TDI TDO 1 I/O BST 3 2 Altera Corporation Preliminary
IEEE Std. 1149.1 JTAG 3 1. Stratix II JTAG ( / ) JTAG CLAMP (1) 00 0000 1010 TDI TDO 1 I/O BST ICR JTAG Stratix IIMasterBlaster TM ByteBlasterMV TM ByteBlaster II JRunner.jam.jbc PULSE_NCONFIG 00 0000 0001 nconfig Low CONFIG_IO (2) 00 0000 1101 JTAG I/O I/O JTAG CONFIG_IO nstatus Low IOE nstatus Low TAP UPDATE_DR SignalTap II Signal Tap II 3 1 (1) HIGHZ CLAMP EXTEST (2) CONFIG_IO MorphIO: An I/O Reconfigulation Solution for Altera Devices White Paper Altera Corporation 3 3 Preliminary
Stratix II, Volume 1 Quartus II JTAG Auto Usercode USERCODE Settings Assignments General Device & Pin Options Auto Usercode 3 2. Stratix II EP2S15 1,140 EP2S30 1,692 EP2S60 2,196 EP2S90 2,748 EP2S130 3,420 EP2S180 3,948 3 3. Stratix II 32 IDCODE IDCODE 32 (1) 4 16 ID 11 LSB 1 (2) EP2S15 0000 0010 0000 1001 0001 000 0110 1110 1 EP2S30 0000 0010 0000 1001 0010 000 0110 1110 1 EP2S60 0001 0010 0000 1001 0011 000 0110 1110 1 EP2S90 0000 0010 0000 1001 0100 000 0110 1110 1 EP2S130 0000 0010 0000 1001 0101 000 0110 1110 1 EP2S180 0000 0010 0000 1001 0110 000 0110 1110 1 3 3 (1) MSB (2) IDCODE LSB 1 3 4 Altera Corporation Preliminary
SignalTap II Stratix Stratix II Cyclone Cyclone II JTAG 17 JTAG Stratix Stratix II Cyclone Cyclone II 18 SignalTap II JTAG Stratix II Volume 2Stratix II GX Volume 2 IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing for Stratix II & Stratix II GX Devices Jam Programming & Test Language Specification SignalTap II Stratix II IEEE Std. 1149.1 JTAG SignalTap II I/O FineLine BGA Stratix II CMOS SRAM FPGA Stratix II MAX II Stratix II FPP AS PSPPA JTAG Stratix II Stratix II Altera Corporation 3 5 Preliminary
Stratix II, Volume 1 Stratix II AES Stratix II FPGA Stratix II Stratix II SRAM SRAM I/O I/O Stratix II SRAM 3 6 Altera Corporation Preliminary
PORSEL 12 ms 100 ms POR PORSEL POR 100 ms PORSEL V CC POR 12 ms nio PULLUP I/O I/O ncso ASDO DATA[7..0] nws nrs RDYnBSY ncs CS RUnLU PGM[2..0] CLKUSR INIT_DONE DEV_OE DEV_CLR High 1.5 V 1.8 V 2.5 V 3.3 V Low Stratix II JTAG 3.3V/2.5V 3.3V V CCPD V CCPD VCCSEL JTAG TCK TMS TDI TRSTVCCSEL 3 4 VCCSEL V CCIO V CCIO V IL V IH Altera Corporation 3 7 Preliminary
Stratix II, Volume 1 PLL_ENA 3 4 3.3 V/2.5 V 1.8 V/1.5 V VCCSEL 3 4 VCCSEL 3 4. VCCSEL VCCSEL = LOW (GND ) VCCSEL = HIGH (V CCPD ) nstatus ( ) nconfig CONF_DONE ( ) DATA[7..0] nce DCLK ( ) CS nws nrs ncs CLKUSR DEV_OE DEV_CLRn RUnLU PLL_ENA 3.3V/2.5V V CCPD 1.8V/1.5V I/O V CCIO VCCSEL VCCSEL VCCSEL V CCINT V CCPD High VCCSEL 1.8 V/1.5 V Low 3.3 V/2.5 V VCCSEL MAX II/ 3 8 Altera Corporation Preliminary
3.3 V/2.5 V VCCSEL Low I/O V CCIO 1.8 V/1.5 V VCCSEL High V CCIO 1.8 V/1.5 V TDO nceo Stratix II Volume 1 Stratix II Stratix II 5 3 5 Stratix II JTAG Stratix II nce nceo 5 Stratix II Stratix II FPGA Stratix II Altera Corporation 3 9 Preliminary
Stratix II, Volume 1 3 5 3 5. Stratix II FPP MAX II Flash (1) (1) (2) AS (3) PS MAX II Flash (4) PPA MAX II Flash JTAG (4) MAX II Flash 3 5 (1) 4 DCLK (2) Stratix II (3) AS (4) USB USB MasterBlaster /USB ByteBlaster II ByteBlasterMV Stratix II Stratix II GX Stratix II Volume 2 Stratix II GX Volume 2 Stratix II & Stratix II GX 3 10 Altera Corporation Preliminary
Stratix II FPGA (Advanced Encryption Standard AES FPGA 128 Stratix II FPGA Stratix II FPGA 128 Stratix II PSAS FPP 4 DCLK FPGA Stratix II FPGA Stratix II FPGA Stratix II FPGA SRAM Stratix II FPGA FPP MAX II / Flash AS PS PPA JTAG Altera Corporation 3 11 Preliminary
Stratix II, Volume 1 Stratix II Timeto-Market Stratix II FPGA Stratix II Nios RSC FPP AS PS PPA Stratix II RSC AES Stratix II Stratix II Stratix II Volume 2Stratix II GX Volume 2 Stratix II & Stratix II GX 3 12 Altera Corporation Preliminary
JRunner Stratix II FPGA JRunner JTAG ByteBlaster II ByteBlasterMV Stratix II FPGA Raw Binary File (.rbf) JRunner Quartus II Chain Description File (.cdf) JRunner JTAG /Windows NT OS JRunner JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper www.altera.co.jp SRunner SRunner SRunner SRunner.rpd SRunner Quartus II SRunner SRunner: An Embedded Solution for EPCS Programming White Paper www.altera.co.jp Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet Altera Corporation 3 13 Preliminary
Stratix II, Volume 1 MicroBlasterDviver Stratix II FPGA MicroBlaster TM RBF FPP PS Windows NT OS MicroBlaster www.altera.co.jp Configuring the MicroBlaster Fast Passive Parallel Software Driver White Paper Configuring the MicroBlaster Passive Serial Software Driver White Paper PLL Stratix II PLL Phase-Locked-Loop VCO I/O PLL PLL PLL Stratix II PLL Stratix II Volume 2Stratix II GX Volume 2 Stratix II & Stratix II GX PLL Stratix II Maxim Integrated Products MAX1617A MAX1619 Stratix II 8 7 Stratix II 3 14 Altera Corporation Preliminary
3-1 Stratix II 2tempdiodep tempdioden Stratix II 3-1. Stratix II tempdiodep tempdioden 3 6 Stratix II 3 6. IBIAS High 80 100 120 µa IBIAS Low 8 10 12 µa VBP - VBN 0.3 0.9 V VBN 0.7 V 3 Ω 3-2 Altera Corporation 3 15 Preliminary
Stratix II, Volume 1 3-2. 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 55 30 5 20 45 70 95 120 SEU Stratix II SEU Single Event Upset Quartus II Device & Pin Options CRC Cyclic Redundancy Check 32 CRC SEU CRC Stratix II Stratix II CRC CRC SRAM CRC_ERROR 3 16 Altera Corporation Preliminary
SEU Stratix II Stratix II SRAM 1 Quartus II 4.1 Device & Pin Options CRC CRC 400 khz 50 MHz CRC FPGA SRAM CRC AN 357: Error Detection Using CRC in Altera FPGA Devices Altera Corporation 3 17 Preliminary
Stratix II, Volume 1 3 18 Altera Corporation Preliminary