RSA High-Speed Multiplication for RSA ode using Redundant Binary System 6585 6 6
RSA FA FA AND Booth FA FA RSA 3 4 5
This paper summarizes High-Speed Multiplication for RSA ode using Redundant Binary System, which is performed for the degree of Master at the raduate School of Engineering, the Kochi University of Technology. In the communication field, many researches have been carried out into encryption, which is used to protect communication from unauthorized transmitter and receiver. This means that the information becomes more and more valuable in modern society; so-called an advanced information society. The encryption technology becomes popular in a daily life because the value of information is recognized higher and higher. ipher is used for information secrecy and authentication. The electronic signature is one example of authentication using cipher. The cipher is classified into two types. The one is common key cryptography, which perfumes encryption and decryption using a common key. The other is public key cryptography, which uses two keys; a secret key and a public key. Recently, the public key cryptography is used in communication area, because of its small number of keys comparing to the common key cryptography. The public key cryptography, however, requires complicated arithmetic operation for encryption and decryption. Therefore, high speed arithmetic processing is necessary in transmitters and receivers. This paper proposes a multiplier using Redundant Binary System (RBS as a circuit that performs index and surplus calculations at high speed. We compared the multiplier using RBS with two kinds of multipliers using Full-Adder (FA, with regard to data arrival time and gate count. As for data arrival time, the multiplier using RBS is faster than the multipliers using FA, and this tendency is grown when the number of input data bits is increased. Improvement in the speed is expected when Booth decoder is applied to the partial product generation. As for gate count, the multiplier using RBS requires more gates than the multipliers using FA. Future researches should focus on the reduction of gate count. This paper consists of 5 hapters. The first hapter describes background and purpose of this research. hapter explains the arithmetic operation method of RSA code comparing with ordinary ones. In hapter 3, we propose the multiplier using RBS, and hapter4 shows the comparison results of multipliers regarding to data arrival time and gate count. Finally, hapter 5 summarizes this paper suggesting future research subjects. This work is supported by VLSI Design and Education enter (VDE, the University of Tokyo in collaboration with Rohm orporation and Synopsys, Inc.
RSA 3 RSA 3 5 3 kary 7 4 8 3 7 3 7 3 7 33 4 4 7 5 36 37 38 39
( :Electronic Toll ollection System n k min k min (n-(n-(n-3 k min n
. RSA RSA 3 5
RSA RSA RSA 977 MIT( (Rivest (Shamir (Adleman RSA. B b B A c D d D. 3
RSA ( a,b n n a b a b n a b ( mod n ( RSA ( (a,n φ ( a n ( mod n ( φ ( n φ ( n ( p ( q (3 p q p q n P a P a a P a ( mod P ( a P ( mod P (4 (5 RSA P e ( mod M (6 P e M P 53 e M 33 6 5 3 5 6 ( mod 33 (7 4
(6 e P ( mod M (8 e e 7 6 6 7 83876 5( mod 33 (9 P 5 M 33 (P,M ( φ n 3 7 φ ( n ( P P P P P P P( mod 33 ( (6 (8 RSA (6 (8 k-ary [] k-ary AB ( mod ( mod AB AB ( mod X AR ( ( Y B mod (3 X, Y 5
XY ( mod (4 R XY R XY U R ( mod (5 U (4 (5 U U XY ( mod R (6 (5 X ( mod R (7 X Y U ( mod (8 R Y ( X <, Y < XY < ( mod R (9 ( mod R ( < R < R < R XY < < XY R R XY < R XY < R < (4 6
3 k-ary k-ary k-ary k A ( mod k-ary.(a,(b A A A : A(mod A (mod (A A(mod (A 5 A(mod (a A [b] A 3 A 3 (mod :A [b] A (A (mod (A 4 (mod A 8 A 3 (mod A ( mod (b k-ary k bb. k-ary. (a 7 (b k-ary 3 k-ary k-ary k-ary A 3 ( mod k k k-ary n k k ( 7
n k k {( n k } ( 4 ~4.3.3kbit (k4 k-ary RSA 4 k-ary RSA 4.4 8
.4 Booth Wallace tree (arry Look-ahead Adder:LA (Binary Look-ahead arry Adder:BLA [] Booth 6 Y Y 5 5 5 4 3 y5 y4 ( y3 y ( y y 4 ( y y y ( y y y ( y y y y 5 4 4 y 4 3 3 y 3 y 3 y y (3 MSB [ ] y 5 6 3 Booth. X 9
. Booth y j y j y j- Y j Z j One two N X j X j X j X j X j X j Y j Z j Y j Z j j X Y j Z j j X Y j Z j X j Y j Z j j X one,two,n one two N Booth.5 y j- one y j two y j N.5 Booth X j
X j-.6 X j X j- one two N Z j.6 Booth MSB [ ] y 5.6 Booth one,two N MSB X N- Z jn N X N- one,two.7 one two N Z jn X N-.7 Booth.5.7 Booth Wallace tree (Full adder:fatree
FA /3 tree.8 8 7 6 5 4.8 tree (48 tree LA BLA LA 4 LA A,B 3 A B ( A B (4
( B A B A (5 ( B A B A (6 ( 3 3 3 3 3 3 3 B A B A (7 (4 n n n B A (8 n n n B A (9 (3 (3 ( (3 ( (3 ( 3 3 3 3 3 3 3 3 (3 A,B MSB LSB MSB 4 4 4 LA.9 3
.9 4 LA LA BLA BLA LA BLA g q (33 ( A B ( A B (34 4
A B ( A B ( (35 g q (36 g, q (37 (33 ( (, ( g q ( g q (38 (33 g q (39 g q q g (4 (, q (, (, g (4 n ( g n, qn ( n, n ( n, n (, ( n, n (4, (4 g,q n n- tree tree. 5
( 7, 7 (g 7,q 7 ( 6, 6 (g 6,q 6 ( 5, 5 (g 5,q 5 ( 4, 4 (g 4,q 4 ( 3, 3 (g 3,q 3 (, (g,q (, (g,q (, (g,q ( -, - (g -,q -. tree 6 BLA. R,PB,NB SM XOR. 6 BLA 6
3 3 FA RSA 4 (Redundant Binary System 3 [3] 7 3. - (a (b 3. 7
7 - -- 7 3.,,,, A,B ss S i ss i i i i A i,b i i- A i- B i- i S i i ss i i- i- 3. 3. ( A i( A i( B i( B i( A i-( A i-( B i-( B i-( ss i( ss i( i( i( 3. ss {( A A ( B B } α i( i( i( i( i( (3 8
ss {( A A ( B B } α i( i( i( i( i( {( A A B B A A ( B B } α Ai ( Ai ( Bi( Bi( i( i( i( i( i( i( i( ( i( i {( A A B B A A ( B B } α Ai ( Ai ( Bi( Bi( i( i( i( i( i( i( i( ( i( i (3 (33 (34 α A A i ( i ( i ( i ( B B (35 3. 3. ( ss i( ss i( i-( i-( S i( S i( 3 don t care 3. S i( ssi( i ( (36 S i( ssi( i ( (37 (3 (37 3. 9
3. ( don t care 3.3
3.3 don t care ( A i( A i( B i( B i( A i-( B i-( ss i( ss i( i( i( don t care A i-( B i-( 3.3 ss A A B A A B A B B A B B α (38 i( ( i( i( i( i( i( i( i( i( i( i( i( i( ss A A B A A B A B B A B B α (39 i( ( i( i( i( i( i( i( i( i( i( i( i( i( A B A B A B i ( i ( i ( ( i ( i ( i ( i ( α (3 A B A B A B α (3 i ( i ( i ( ( i ( i ( i ( i ( α A i ( B i ( (3 3.4
3.4 don t care ( ss i( ss i( i-( i-( S i( S i( 34 don t care S i ( ss i ( i ( ss i ( i ( (33 S ss ss i ( i ( i ( i ( i ( (34 (38 (34 3.3 3.4 3.4 6,3,64 LABLA LA BLA [4] 33
A j-( B j-( A j( A j( B j( B j( j-( j-( ss j( ss j( j( j( S j( S j( 3.3 ( RA BLA 6bit 3bit 64bit (bit 3.4 3
33 3.5 X Y N N AND Z N- 3.5 AND 3.3 FA tree 6 3.6 4
3.6 6 FA 3.7 FA n( 3.7 n 5
n AND n Booth (n/ FA 3 i i ( n ( 3 (35 i n i ( (36 6
4 RSA 3 Wallace tree, LA 4.(a Booth, Wallace tree, BLA 4.(b 4.(c 6,8,6 4. (AND (Booth (AND Wallace tree Wallace tree (LA (BLA (a (b (c 4. VHDL (6 VHDL Synopsys design analyzer library rohm35_h 6 8 4.(a,(b,(c 7
4.(a 6 8
4.(a 8 9
4.(b 6 3
4.(b 8 3
4.(c 6 3
4.(c 8 33
4. 4. Bit 6 8 6 ircuit The number of ate Data arrival time [gate] [ns] (a 69 6.36 (b 6 5.55 (c 66 6.3 (a 377 9.4 (b 4 7.3 (c 5 6.38 (a 6 4.48 (b 87.54 (c 53 8.6 4. ircuit(a,(b,(c 4. Wallace tree, LA Booth, Wallace tree, BLA 4. 4. 4.3 4.4 34
Data arrival time (ns 6 5 4 3 9 8 7 6 5 4 3 6bit 8bit 6bit (a (b (c bit(bit 4.3 The number of ate (gate 6bit 8bit bit(bit 6bit 4.4 4.3 Booth, Wallace tree, BLA 8 6 35
5 FA AND Booth FA FA FA 36
37
[] RSA Vol.No.476pp.576November. [] MOS pp.557 Octover996. [3] http://www-tysm.ee.kanagawa-u.ac.jp/~toyo/data/master/996ariyama.pdf pp.45996. [4] RSA p.893. 38
6 6 VHDL VHDL Wallace tree, LA 6 VHDL ---------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity multiplier66_fa is port (X : in std_logic_vector(5 downto ; Y : in std_logic_vector( 5 downto ; zero : in std_logic; Z : out std_logic_vector( downto ; end multiplier66_fa; architecture rtl of multiplier66_fa is component FA port (A : in std_logic; B : in std_logic; : in std_logic; S : out std_logic; _out : out std_logic; end component; component LA_4 port (A : in std_logic_vector(3 downto ; B : in std_logic_vector(3 downto ; : in std_logic; S : out std_logic_vector(3 downto ; _out : out std_logic; 39
end component; component HA port (A : in std_logic; B : in std_logic; S : out std_logic; : out std_logic; end component; signal XY, XY, XY3, XY4, XY5, XY, XY, XY, XY3, XY4, XY5, XY, XY, XY, XY3, XY4, XY5, X3Y, X3Y, X3Y, X3Y3, X3Y4, X3Y5, X4Y, X4Y, X4Y, X4Y3, X4Y4, X4Y5, X5Y, X5Y, X5Y, X5Y3, X5Y4, X5Y5,,,, 3, 4, 5, 6, 7, 8, 9,,,, 3, 4, 5, 6, 7, 8, 9,,,, 3, 4, 5, S, S, S, S3, S4, S5, S6, S7, S8, S9, S, S, S, S3, S4, S5, S6, S7, S8, S9, S, S : std_logic; signal A, B : std_logic_vector(7 downto ; signal : std_logic; begin Z( < X( and Y(; XY < X( and Y(; XY < X( and Y(; X3Y < X(3 and Y(; X4Y < X(4 and Y(; X5Y < X(5 and Y(; XY < X( and Y(; XY < X( and Y(; XY < X( and Y(; X3Y < X(3 and Y(; X4Y < X(4 and Y(; X5Y < X(5 and Y(; XY < X( and Y(; XY < X( and Y(; XY < X( and Y(; 4
X3Y < X(3 and Y(; X4Y < X(4 and Y(; X5Y < X(5 and Y(; XY3 < X( and Y(3; XY3 < X( and Y(3; XY3 < X( and Y(3; X3Y3 < X(3 and Y(3; X4Y3 < X(4 and Y(3; X5Y3 < X(5 and Y(3; XY4 < X( and Y(4; XY4 < X( and Y(4; XY4 < X( and Y(4; X3Y4 < X(3 and Y(4; X4Y4 < X(4 and Y(4; X5Y4 < X(5 and Y(4; XY5 < X( and Y(5; XY5 < X( and Y(5; XY5 < X( and Y(5 ; X3Y5 < X(3 and Y(5; X4Y5 < X(4 and Y(5; X5Y5 < X(5 and Y(5; U : FA port map(zero, XY, XY, Z(, ; U : FA port map(xy, XY, XY, S, ; U : FA port map(xy, XY, X3Y, S, ; U3 : FA port map(xy, X3Y, X4Y, S, 3; U4 : FA port map(x3y, X4Y, X5Y, S3, 4; U5 : FA port map(x4y, X5Y, zero, S4, 5; U6 : FA port map(zero, XY4, XY3, S5, 6; U7 : FA port map(xy5, XY4, XY3, S6, 7; U8 : FA port map(xy5, XY4, X3Y3, S7, 8; U9 : FA port map(xy5, X3Y4, X4Y3, S8, 9; U : FA port map(x3y5, X4Y4, X5Y3, S9, ; U : FA port map(x4y5, X5Y4, zero, S, ; U : FA port map(zero, S,, Z(, ; U3 : FA port map(xy3, S,, S, 3; 4
U4 : FA port map(s5, S,, S, 4; U5 : FA port map(s6, S3, 3, S3, 5; U6 : FA port map(s7, S4, 4, S4, 6; U7 : FA port map(s8, X5Y, 5, S5, 7; U8 : FA port map(s3, 6, zero, S6, 8; U9 : FA port map(s4, 7, 5, S7, 9; U : FA port map(s5, 8, 6, S8, ; U : FA port map(s9, 9, 7, S9, ; U : FA port map(s,, zero, S, ; U3 : FA port map(x5y5,, zero, S, 3; A < S&S&S9&S8&S7&S6&S&S; B < &&&9&8&4&3&; U4 : LA_4 port map(a(3 downto, B(3 downto, zero, Z(6 downto 3, 4; U5 : LA_4 port map(a(7 downto 4, B(7 downto 4, 4, Z( downto 7, 5; U6 : HA port map(5, 3, Z(, ; end rtl; ---------------------------------------------------------------------------------------------------------- Booth, Wallace tree, BLA 6 VHDL ---------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOI_64.ALL; use IEEE.STD_LOI_ARITH.ALL; use IEEE.STD_LOI_UNSINED.ALL; entity multiplier66_ is Port ( X : in std_logic_vector(7 downto ; Y : in std_logic_vector(7 downto ; one : in std_logic; 4
zero : in std_logic; Z : out std_logic_vector(4 downto ; end multiplier66_; architecture Behavioral of multiplier66_ is component Booth_six is Port ( X : in std_logic_vector(5 downto ; X_minus : in std_logic; Y : in std_logic_vector(5 downto ; Y_minus : in std_logic; A : out std_logic_vector(5 downto ; A : out std_logic_vector(5 downto ; A : out std_logic_vector(5 downto ; A_bar_g : out std_logic; A_bar_g : out std_logic; A_bar_g : out std_logic; : out std_logic; : out std_logic; : out std_logic; end component; component Wallace_tree_six is Port ( A A : in std_logic_vector(5 downto ; : in std_logic_vector(5 downto ; A : in std_logic_vector(5 downto ; A_bar : in std_logic; A_bar : in std_logic; A_bar : in std_logic; : in std_logic; : in std_logic; : in std_logic; one : in std_logic; zero : in std_logic; S : out std_logic_vector( downto ; _out : out std_logic_vector(9 downto ; 43
end component; _minus : out std_logic; component BLA_six is Port ( A : in std_logic_vector( downto ; B : in std_logic_vector( downto ; g_minus : in std_logic; q_minus : in std_logic; g_minus_bar : in std_logic; q_minus_bar : in std_logic; g_minus : in std_logic; q_minus : in std_logic; g_minus_bar : in std_logic; q_minus_bar : in std_logic; _minus : in std_logic; S : out std_logic_vector(downto ; end component; signal A, A, A : std_logic_vector(5 downto ; signal A_bar_g, A_bar_g, A_bar_g,,,, _minus : std_logic; signal S, : std_logic_vector( downto ; signal _out : std_logic_vector(9 downto ; begin compbooth : Booth_six port map (X(5 downto, zero, Y(5 downto, zero, A(5 downto, A(5 downto, A(5 downto, A_bar_g, A_bar_g, A_bar_g,,, ; compwallace : Wallace_tree_six port map (A(5 downto, A(5 downto, A(5 downto, A_bar_g, A_bar_g, A_bar_g,,,, one, zero, S( downto, _out(9 downto, _minus; < _out(9 downto & _minus; compbla : BLA_six port map (S( downto, ( downto, zero, one, one, zero, zero, one, one, zero, one, 44
Z( downto ; end Behavioral; ---------------------------------------------------------------------------------------------------------- 3 6 VHDL ---------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOI_64.ALL; use IEEE.STD_LOI_ARITH.ALL; use IEEE.STD_LOI_UNSINED.ALL; entity multiplier66_rb is Port ( X : in std_logic_vector( downto ; Y : in std_logic_vector( downto ; zero : in std_logic; Z : outstd_logic_vector(3 downto ; end multiplier66_rb; architecture rtl of multiplier66_rb is component RBcell Port ( A : in std_logic_vector( downto ; B : in std_logic_vector( downto ; A_minus : in std_logic; B_minus : in std_logic; _minus : in std_logic_vector( downto ; S : out std_logic_vector( downto ; : out std_logic_vector( downto ; end component; signal XY, XY, XY3, XY4, XY5, XY, XY, XY, XY3, XY4, XY5, XY, XY, XY, XY3, XY4, XY5, X3Y, X3Y, X3Y, X3Y3, X3Y4, X3Y5, X4Y, X4Y, X4Y, X4Y3, X4Y4, X4Y5, X5Y, X5Y, X5Y, X5Y3, X5Y4, X5Y5,,,, 3, 4, 5, 6, 7, 8, 9,,,, 3, 4, 5, 6, 7, 8, 9,,,, 3, 4, 5, 6, 7, 8, 9, 3, 3, 45
3, 33, S, S, S, S3, S4, S5, S6, S7, S8, S9, S, S, S, S3, S4, S5, S6, S7, S8, S9, S, S, S, zz : std_logic_vector( downto ; begin Z( < (X( nand Y( nand (X( nand Y(; Z( < (X( nand Y( nand (X( nand Y(; XY( < (X( 3 nand Y( XY( < (X(3 nand Y( XY( < (X(5 nand Y( nand (X( nand Y(; nand (X( nand Y(; nand (X(4 nand Y(; XY( < (X(5 nand Y( nand (X(4 nand Y(; X3Y( < (X(7 nand Y( nand (X(6 nand Y(; X3Y( < (X(7 nand Y( X4Y( < (X(9 nand Y( X4Y( < (X(9 nand Y( nand (X(6 nand Y(; nand (X(8 nand Y(; nand (X(8 nand Y(; X5Y( < (X( nand Y( X5Y( < (X( nand Y( nand (X( nand Y(; nand (X( nand Y(; XY( < (X( nand Y(3 nand (X( nand Y(; XY( < (X( nand Y( XY( < (X(3 nand Y(3 nand (X( nand Y(3; nand (X( nand Y(; XY( < (X(3 nand Y( nand (X( nand Y(3; XY( < (X(5 nand Y(3 nand (X(4 nand Y(; XY( < (X(5 nand Y( X3Y( < (X(7 nand Y(3 X3Y( < (X(7 nand Y( X4Y( < (X(9 nand Y(3 X4Y( < (X(9 nand Y( X5Y( < (X( nand Y(3 X5Y( < (X( nand Y( nand (X(4 nand Y(3; nand (X(6 nand Y(; nand (X(6 nand Y(3; nand (X(8 nand Y(; nand (X(8 nand Y(3; nand (X( nand Y(; nand (X( nand Y(3; XY( < (X( nand Y(5 nand (X( nand Y(4; XY( < (X( nand Y(4 nand (X( nand Y(5; XY( < (X(3 nand Y(5 nand (X( nand Y(4; XY( < (X(3 nand Y(4 nand (X( nand Y(5; XY( < (X(5 nand Y(5 nand (X(4 nand Y(4; XY( < (X(5 nand Y(4 nand (X(4 nand Y(5; X3Y( < (X(7 nand Y(5 nand (X(6 nand Y(4; 46
X3Y( < (X(7 nand Y(4 nand (X(6 nand Y(5; X4Y( < (X(9 nand Y(5 nand (X(8 nand Y(4; X4Y( < (X(9 nand Y(4 nand (X(8 nand Y(5; X5Y( < (X( nand Y(5 nand (X( nand Y(4; X5Y( < (X( nand Y(4 nand (X( nand Y(5; XY3( < (X( nand Y(7 nand (X( nand Y(6; XY3( < (X( nand Y(6 nand (X( nand Y(7; XY3( < (X(3 nand Y(7 nand (X( nand Y(6; XY3( < (X(3 nand Y(6 nand (X( nand Y(7; XY3( < (X(5 nand Y(7 nand (X(4 nand Y(6; XY3( < (X(5 nand Y(6 nand (X(4 nand Y(7; X3Y3( < (X(7 nand Y(7 nand (X(6 nand Y(6; X3Y3( < (X(7 nand Y(6 nand (X(6 nand Y(7; X4Y3( < (X(9 nand Y(7 nand (X(8 nand Y(6; X4Y3( < (X(9 nand Y(6 nand (X(8 nand Y(7; X5Y3( < (X( nand Y(7 nand (X( nand Y(6; X5Y3( < (X( nand Y(6 nand (X( nand Y(7; XY4( < (X( nand Y(9 nand (X( nand Y(8; XY4( < (X( nand Y(8 nand (X( nand Y(9; XY4( < (X(3 nand Y(9 nand (X( nand Y(8; XY4( < (X(3 nand Y(8 nand (X( nand Y(9; XY4( < (X(5 nand Y(9 nand (X(4 nand Y(8; XY4( < (X(5 nand Y(8 nand (X(4 nand Y(9; X3Y4( < (X(7 nand Y(9 nand (X(6 nand Y(8; X3Y4( < (X(7 nand Y(8 nand (X(6 nand Y(9; X4Y4( < (X(9 nand Y(9 nand (X(8 nand Y(8; X4Y4( < (X(9 nand Y(8 nand (X(8 nand Y(9; X5Y4( < (X( nand Y(9 nand (X( nand Y(8; X5Y4( < (X( nand Y(8 nand (X( nand Y(9; XY5( < (X( nand Y( nand (X( nand Y(; XY5( < (X( nand Y( nand (X( nand Y(; XY5( < (X(3 nand Y( nand (X( nand Y(; XY5( < (X(3 nand Y( nand (X( nand Y(; XY5( < (X(5 nand Y( nand (X(4 nand Y(; XY5( < (X(5 nand Y( nand (X(4 nand Y(; X3Y5( < (X(7 nand Y( nand (X(6 nand Y(; 47
X3Y5( < (X(7 nand Y( nand (X(6 nand Y(; X4Y5( < (X(9 nand Y( nand (X(8 nand Y(; X4Y5( < (X(9 nand Y( nand (X(8 nand Y(; X5Y5( < (X( nand Y( nand (X( nand Y(; X5Y5( < (X( nand Y( nand (X( nand Y(; zz < zero & zero; comp : RBcell port map(xy, XY, zero, zero, zz, Z(3 downto, ; comp : RBcell port map(xy, XY, XY(, XY(,, S, ; comp : RBcell port map(xy, X3Y, XY(, XY(,, S, ; comp3 : RBcell port map(x3y, X4Y, XY(, X3Y(,, S, 3; comp4 : RBcell port map(x4y, X5Y, X3Y(, X4Y(, 3, S3, 4; comp5 : RBcell port map(x5y, zz, X4Y(, X5Y(, 4, S4, 5; comp6 : RBcell port map(xy3, XY, zero, zero, zz, S5, 6; comp7 : RBcell port map(xy3, XY, XY3(, XY(, 6, S6, 7; comp8 : RBcell port map(xy3, X3Y, XY3(, XY(, 7, S7, 8; comp9 : RBcell port map(x3y3, X4Y, XY3(, X3Y(, 8, S8, 9; comp : RBcell port map(x4y3, X5Y, X3Y3(, X4Y(, 9, S9, ; comp : RBcell port map(x5y3, zz, X4Y3(, X5Y(,, S, ; comp : RBcell port map(s, XY, zero, zero, zz, Z(5 downto 4, ; comp3 : RBcell port map(s, S5, S(, XY(,, Z(7 downto 6, 3; comp4 : RBcell port map(s, S6, S(, S5(, 3, S, 4; comp5 : RBcell port map(s3, S7, S(, S6(, 4, S, 5; comp6 : RBcell port map(s4, S8, S3(, S7(, 5, S3, 6; comp7 : RBcell port map(5, S9, S4(, S8(, 6, S4, 7; comp8 : RBcell port map(zz, S, 5(, S9(, 7, S5, 8; comp9 : RBcell port map(zz,, zero, S(, 8, S6, 9; comp : RBcell port map(xy5, XY4, zero, zero, zz, S7, ; comp : RBcell port map(xy5, XY4, XY5(, XY4(,, S8, ; comp : RBcell port map(xy5, X3Y4, XY5(, XY4(,, S9, ; comp3 : RBcell port map(x3y5, X4Y4, XY5(, X3Y4(,, S, 3; comp4 : RBcell port map(x4y5, X5Y4, X3Y5(, X4Y4(, 3, S, 4; comp5 : RBcell port map(x5y5, zz, X4Y5(, X5Y4(, 4, S, 5; comp6 : RBcell port map(s, XY4, zero, zero, zz, Z(9 downto 8, 6; comp7 : RBcell port map(s, S7, S(, XY4(, 6, Z( downto, 7; 48
comp8 : RBcell port map(s3, S8, S(, S7(, 7, Z(3 downto, 8; comp9 : RBcell port map(s4, S9, S3(, S8(, 8, Z(5 downto 4, 9; comp3 : RBcell port map(s5, S, S4(, S9(, 9, Z(7 downto 6, 3; comp3 : RBcell port map(s6, S, S5(, S(, 3, Z(9 downto 8, 3; comp3 : RBcell port map(9, S, S6(, S(, 3, Z( downto, 3; comp33 : RBcell port map(zz, 5, 9(, S(, 3, Z(3 downto, 33; end rtl; ---------------------------------------------------------------------------------------------------------- 49