if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =

Size: px

Start display at page:

Download "if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst ="

ちとらあきくぼ
6 years ago
Views:

1 VHDL 2 1 VHDL 1 VHDL FPGA VHDL 2 HDL VHDL 2.1 D 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; regs.vhdl entity regs is clk, rst : in std_logic; clear : in std_logic; we : in std_logic; D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0)); end regs; architecture rtl of regs is process (clk, rst) if rst = 0 then Q <= " "; elsif clk event and clk = 1 then 1

2 if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst = 0 then -- Q <= "0000"; elsif clk event and clk = 1 then -- rst clear we clk we 1 adr 3 D 4 Q 4 we 1 adr 0 adr 7 D adr Q 2

3 regfile.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity regfile is clk : in std_logic; we : in std_logic; adr : in std_logic_vector(2 downto 0); D : in std_logic_vector(3 downto 0); Q : out std_logic_vector(3 downto 0)); end entity regfile; architecture behv of regfile is type ramtype is array (0 to 7) of std_logic_vector(3 downto 0); signal mem : ramtype; Q <= mem(conv_integer(adr)); process (clk) is if clk event and clk = 1 then if we = 1 then mem(conv_integer(adr)) <= D; end architecture behv; regfile.vhdl VHDL array 4 8 ramtype ramtype mem 0 7 mem(0) mem(3) adr 3 std logic vector VHDL conv integer() n 1 2 n 3

4 10 VHDL count10 clk rst rst VHDL Q Qreg Q count10.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count10 is clk, rst : in std_logic; Q : out std_logic_vector(3 downto 0)); end count10; architecture rtl of count10 is signal Qreg : std_logic_vector(3 downto 0); Q <= Qreg; process (clk, rst) if rst = 0 then Qreg <= "0000"; elsif clk event and clk = 1 then if Qreg = "1001" then Qreg <= "0000"; else Qreg <= Qreg + 1; end rtl; count10.vhdl clk Qreg 1 if if clk event and clk = 1 then Qreg <= Qreg + 1; 4

5 2.4 clk n 4 load 1 count Q 4 zero 1 load 1 n load 0 count 1 1 load count 0 Q 0 zero 1 downcounter.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity downcounter is clk : in std_logic; n : in std_logic_vector(3 downto 0); load : in std_logic; count : in std_logic; Q : out std_logic_vector(3 downto 0); zero : out std_logic); end entity downcounter; architecture behv of downcounter is signal Qreg : std_logic_vector(3 downto 0); -- Output Q <= Qreg; -- Down counter process (clk) is if clk event and clk = 1 then if load = 1 then Qreg <= n; elsif count = 1 then 5

6 Qreg <= Qreg - 1; -- zero process (Qreg) is if Qreg = "0000" then zero <= 1 ; else zero <= 0 ; end architecture behv; downcounter.vhdl 3 n 1 n summation 1: sum = 0 2: INPUT n 3: while (n >= 0) 4: { 5: sum = sum + n 6: n = n - 1 7: } 8: OUTPUT sum summation n 1 n n 0 1 6

7 1 1 n clk rst 1 load, count, clear, sumload 1 2 n 4 3 7

8 sum 1 n 8 cnt 4 zero Sreg 8 2. load 1 n 3. load 0 count clear 1 Sreg 0 5. sumload 1 Sreg 6. sum Sreg 7. cval 8. zero *1 datapath.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity datapath is clk : in std_logic; rst : in std_logic; load : in std_logic; count : in std_logic; clear : in std_logic; sumload : in std_logic; n : in std_logic_vector(3 downto 0); sum : out std_logic_vector(7 downto 0); cval : out std_logic_vector(3 downto 0); zero : out std_logic); end datapath; architecture rtl of datapath is *1 VHDL 2 8

9 component regs is clk, rst : in std_logic; clear : in std_logic; we : in std_logic; D : in std_logic_vector(7 downto 0); Q : out std_logic_vector(7 downto 0)); end component regs; component downcounter is clk : in std_logic; n : in std_logic_vector(3 downto 0); load : in std_logic; count : in std_logic; Q : out std_logic_vector(3 downto 0); zero : out std_logic); end component downcounter; -- 8-bits register signal Sreg : std_logic_vector(7 downto 0); -- lines signal addout : std_logic_vector(7 downto 0); signal cnt : std_logic_vector(3 downto 0); DCN0 : downcounter port map ( clk => clk, n => n, load => load, count => count, Q => cnt, zero => zero); -- Output sum <= Sreg; cval <= cnt; -- Sreg 9

10 SUMREG : regs port map ( clk => clk, rst => rst, clear => clear, we => sumload, D => addout, Q => Sreg); -- Adder process (cnt, Sreg) is addout <= ("0000" & cnt) + Sreg; end architecture rtl; datapath.vhdl load, count, clear, sumload Finite State Machine FSM 3 1 start 1 zero VHDL controller.vhdl VHDL 1. state 10

11 1 load count clear sumload done s s s s s s state start zero 3. state process controller.vhdl 6 s0 s5 3 constant controller.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity controller is clk : in std_logic; rst : in std_logic; start : in std_logic; zero : in std_logic; cur : out std_logic_vector(2 downto 0); load : out std_logic; count : out std_logic; clear : out std_logic; sumload : out std_logic; done : out std_logic); end entity controller; architecture behv of controller is signal state : std_logic_vector(2 downto 0); signal next_state : std_logic_vector(2 downto 0); -- state constant s0 : std_logic_vector(2 downto 0) := "000"; 11

12 constant s1 : std_logic_vector(2 downto 0) := "001"; constant s2 : std_logic_vector(2 downto 0) := "010"; constant s3 : std_logic_vector(2 downto 0) := "011"; constant s4 : std_logic_vector(2 downto 0) := "100"; constant s5 : std_logic_vector(2 downto 0) := "101"; constant UNKNOWN : std_logic_vector(2 downto 0) := "XXX"; -- output cur <= state; -- Register process (clk, rst) is if rst = 0 then state <= s0; elsif clk event and clk = 1 then state <= next_state; -- calclate next_state process (start, state, zero) is case state is when s0 => if start = 1 then next_state <= s1; else next_state <= s0; -- when others => next_state <= UNKNOWN; end case; -- output from controller process (state) is load <= 0 ; count <= 0 ; sumload <= 0 ; clear <= 0 ; 12

13 done <= 0 ; case state is when s0 => clear <= 1 ; -- when others => null; end case; end architecture behv; controller.vhdl 4 Quartus II FPGA DE1 VHDL FPGA 4.1 regs.vhdl VHDL DE1 4.2 regfile.vhdl VHDL DE1 4.3 downcounter.vhdl VHDL DE1 4.4 datapath.vhdl DE1 4.5 controller.vhdl DE1 4.6 n 1 n summation datapath controller DE1 13

14 summation.vhdl entity summation is clk : in std_logic; rst : in std_logic; start : in std_logic; n : in std_logic_vector(3 downto 0); sum : out std_logic_vector(7 downto 0); cval : out std_logic_vector(3 downto 0); load : out std_logic; done : out std_logic); end entity summation; summation.vhdl clk rst start n sum cval load load n done done 5 VHDL URL 14

15 [1] 1999 [2] VHDL CQ 1995 [3] 2009 [4] Altera University Program, [5] E.O. Hwang, Digital Logic and Microprocessor Design with VHDL, Thomson, Canada,

1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i

1030195 15 2 10 1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i 4-3-3 47 5 52 53 54 55 ii 1 VHDL IC VHDL 5 2 3 IC 4 5 1 2