CMOS 376-851511 0277 (30) 1788 0277 (30)1707 e-mail: k_haruo@el.gunma-u.ac.jp
AD AD AD []
AD AD AD []
ISSCC 2007 TSMC
ISSCC2007
ISSCC2007
/DAC
(regulation) (AGC)
ADC/DAC
AD AD AD []
AD CMOS
SAR ADC Gr),, STARC
1 AD - -
3 11 01 10 11 110
3 0.5 3
11 01 10 1001 10 0011 01 10
: [1] F. Kuttner (Infineon) A 1.2V 10b 20MS/S Non-Binary SAR ADC in 0.13um, ISSCC (2002). [2] M. Heserner (Infineon) A 14b 40MS/S Redundant SAR ADC with 480MHz Clock in 0.13um, ISSCC (2007). Binary ( NonBinary (
< Vin < 10110 11000 Vin 1 0 1 1 0 1 1 0 0 0 4bit 1010
< Vin < 10101 01111 Vin 1 0 1 0 1 0 1 1 1 1 4bit 1001
< Vin < 10010 01110 Vin 1 0 0 1 0 0 1 1 1 0 4bit 1000
ADC/ ADC DAC ADC, ADC ADC ADCDAC
A 14-bit 200-MHz Current-Steering DAC with Switching- Sequence Post-Adjustment Calibration T. Chen, G. Gielen, ESAT-MICAS, K.U.Leuven,ASSCC, China (2006)
Switching-Sequence Post-Adjustment (SSPA)
SSPA -INL, DNL - SSPA SSPA DNLpp = 0.081LSB INLpp = 0.053LSB DNLpp = 0.081LSB INLpp = 0.81LSB
SSPA - SFDR, SNDR - SSPA SSPA SFDR = 82.6 [db] SNDR = 61.1 [db] SFDR = 73.3 [db] SNDR = 59.0 [db]
AD AD AD []
RF Zero-IF DC, 1/f RF Low-IF DC, 1/f AD Direct conversion receiver Low-IF receiver Conventional Quadrature-IF
Low-IF AD DAC I Iin Qin + Analog Input + - - H(z) Complex Banpass Filter E i ADC I ADC Q E q Iout Digital Output Qout DAC Q I out + jq H 1+ H out (I in = + jq in ) + 1 1+ H (E i + je q )
DAC I Iin + Analog Input Qin + - - 1+ 1- H(z) Complex Bandpass Filter E i ADC I ADC Q E q Iout Digital Output Qout DAC Q
I, Q
DAC Analog Ain Filter ADC Multi-bit DAC Dout Digital X H(Z) E Y :Single-bit Output :Multi-bit Output H ( z) 1 Y ( z) = δ z 1+ H ( z) 1+ H ( z) { X ( z) ( z) } + E( ) ()
/ Single-Bit Multi-Bit DAC
DWA I + e 0 I + e 0 I + e 7 S 0 I + e 7 S 0 S 7 I + e 1 S 7 I + e 1 S 1 S 1 S 6 I + e 6 I + e2 S 2 S 6 I + e 6 I + e2 S 2 S 5 S 4 S 3 I + e 3 S 5 S 4 S 3 I + e 3 I + e 5 I + e 4 I + e 5 I + e 4 Output I Output Q
I, Q
ADC
RFADC AD DAC 3
AD AD AD AD
AD fin=3fs/4 RF DAC
RF DACAD 3 1 f f 4 s s 2 f s
RF DAC1 1
RF DAC2 0
RF DAC fs IOUT Data Switch Driver M 2 M 3 I OUT N1 f OSC cos(2(2fs)t)
ADC DAC
RF DAC
25% RTZ DACAD
25% RTZ DACAD SNDR SNR
RF DACAD
RF DACAD SNDR RTZ DAC
AD AD AD []
AD Vdd1
ADC 1 ADC ADC ADC
AD Signal Level Signal Comparator Output Reference Clock Tout1 Tout2 Tout3 Time Time
- - t 1/fref = T t A t V ref π 2 cos ) ( = A t A T t in n ) ( arccos ) ( 2 cos t A T t A in = π Ain Vref
- -
Time-to-Digital Converter) CLK 1 2 3 1 2 3 CK1 CK2 CK3
AD AD AD []
Vin Trigger t 2 t 3 t 4 t time t = T_delay
ADC
MADCM S/N
- - V os 1 ( V os ) rms WL
- - ADC
ADC1 ADC2 ADCADC1, ADC2,
ADC 2
ADC AD ADC
ADC ADC CMOS ADC
AD/DA ADC/DAC
AD X H Multi Bandpass Filter ADC DAC E Y H Z -N Power 1-Z -N 0 1/N 2/N 3/N 4/N Fin/fs DC
(DA) Vout () X(t) = Acost Vin Y(t) = A 0 + A 1 cost + A 2 cos2t + A 3 cos3t +
X(t) = Acost Y(t) Y(t) = A 0 + A 1 cos + A 2 cos2 + A 3 cos3 + 0234AD Z -N 1-Z -N Power 0 0 2 3 1/N 2/N 3/N 4/N
Secure Digital Sytems(ISSCC 2007)
AD AD AD []
Envelop Tracking Integrated Power Electronics EEREnvelope Elimination and Reconstruction
Vdd C Vout=Vdd/4 Vdd Vdd/4 Vout=Vdd/4
OFF Q Q E 1 2 = = = 1 2 C C C 1 1 2 V V 2 1 1 V 2 + 1 2 C 2 V 2 2
ON Q Q 1 2 ' ' = = C C 1 2 V 1 E ' = ( C + 2 V m m C ) 1 2 Vm 2
SW OFF ON SW OFF ON SW ON ' ' 2 1 2 1 Q Q Q Q + + ) ( 1 2 2 1 1 2 1 V C V C C C V m + + = E' E E loss = 2 2 1 2 1 2 1 ) ( 2 1 V V C C C C + =
C 2Vdd - - 2 E = = total 2V dd i( t) dt = Vdd Q 4CV dd 0 2 1 E c = C dd = 2 2 2 ( 2V ) 2CV dd E = R 2 2CVdd
C 2Vdd - - Vdd R C 2Vdd R C State1 State2
Dickson
A/D CM 1 CM 2 C1 Co C o m C m 2 C o
EMI () () EMI
PRM DCDC di V = L dt
DC-DC Reset PRM DC-DC PRM DC-DC PWM PWM) VOUT
16.2dBm 6.9dBm 2.6dBm 3.5dBm -1.5dBm -1.0dBm () 12.7dB 5bitMPRM ()
AD through put latency PWM Digital-to-Time Converter ()
V1 V M
MEMS (Micro Electro Mechanical System ): CMOS
MEMS CoventorWare MEMS MEMS
L 1 L 2
AD AD AD []
ADC/DAC
AD AD AD []
CMOS
kt/c Eni R L C Vout Gm-C
A/DS/H (SoCADC) ()
S/H S/H Sample Hold SWON Vout(t) = Vin(t) Sample SWOFF Vout(t) = Vin(t OFF ) Hold
S/H 1 2 R on R SG 2 C S/H 1 : (R on +R SG )C 2 :
1 SNR N rms = kt C
2 SNR 1/C 1 Signal C
2 V Rn S/H P n, out = kt C ktr = 4 2 2 2 4π R C f 0 2 df + 1 CP noise
S/H R SG SW C
S/H R SG SW Ron C
2 >> 1 SoCADC LSB/2 R LSB/2 V in C V out
2 >> 1 S1 N rms =kt/c SNR SNR BW 1/RC C R 1 V in C V out
2 << 1 2 C 2 R V in C V out
2 << 1 S1/C N rms =kt/c SNR BW 2 SNR 1 C 1/C
f BW S/H SNR 1opt 2opt SPICE
1opt 2opt 1 2 11.50
1opt 2opt SNR
2 / 1 SNR SNR Log( 2 / 1 )
S/H SNR SNR
S/H LeCroy T/H ()