Wide Temperature Range Version 4M SRAM (256-kword 16-bit) RJJ03C0237-0100 Rev. 1.00 2007.05.24 262,144 16 4M RAM TFT 44 TSOP II 48 CSP 0.75mm 3.0V 2.7V 3.6V 55/70ns max 3µW typ V CC =3.0V 2CS 40 +85 C Rev.1.00, 2007.05.24, page 1 of 15
Type No. Access time Package R1LV0416DSB-5SI R1LV0416DSB-7LI R1LV0416DBG-5SI R1LV0416DBG-7LI 55 ns 70 ns 55ns 70ns 400-mil 44-pin plastic TSOP II PTSB0044GA-A (44P3W-H) 48-ball CSP with 0.75mm ball pitch PTBG0048HB-A (48FHH) Rev.1.00, 2007.05.24, page 2 of 15
44-pin TSOP 48-ball CSP A4 A3 A2 A1 A0 CS1# I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE# A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE# UB# LB# I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12 A B C D E F G H 1 2 3 4 5 6 LB# I/O8 I/O9 VSS VCC I/O14 I/O15 NC OE# UB# I/O10 I/O11 I/O12 I/O13 NC A8 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CS2 CS1# I/O0 I/O1 I/O2 I/O3 VCC I/O4 VSS I/O5 I/O6 WE# I/O7 A11 NC (Top view) (Top view) Pin name A0 to A17 Address input I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 OE# (OE) Output enable WE# (WE) Write enable LB# (LB) Lower byte select UB# (UB) Upper byte select V CC V SS NC Power supply Ground No connection Function Rev.1.00, 2007.05.24, page 3 of 15
LSB MSB A13 A7 A8 A9 A10 A11 A12 A6 A14 A15 A16 Row decoder Memory matrix 2,048 x 2,048 V CC V SS I/O0 Column I/O Input data control Column decoder I/O15 LSB A0 A1 A2 A3 A4 A5 A17 MSB CS2 CS1# LB# UB# WE# Control logic OE# Rev.1.00, 2007.05.24, page 4 of 15
CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation H High-Z High-Z Standby L High-Z High-Z Standby H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L L L Din Din write L H L H L Din High-Z Lower byte write L H L L H High-Z Din Upper byte write L H H H High-Z High-Z Output disable H: V IH, L: V IL, : V IH or V IL Parameter Symbol Value Unit Power supply voltage relative to V SS V CC 0.5 to +4.6 V Terminal voltage on any pin relative to V SS V T 0.5* 1 to V CC + 0.3* 2 V Power dissipation P T 0.7 W Operating temperature Topr -40 to +85 C Storage temperature range Tstg 65 to +150 C Storage temperature range under bias Tbias 40 to +85 C 1. 30ns 3.0V(Min) 2. +4.6V DC Parameter Symbol Min Typ Max Unit Note Supply voltage V CC 2.7 3.0 3.6 V V SS 0 0 0 V Input high voltage V IH 2.2 V CC + 0.3 V Input low voltage V IL 0.3 0.6 V 1 Ambient temperature range Ta 40 +85 C 1. 30ns 3.0V(Min) Rev.1.00, 2007.05.24, page 5 of 15
DC Parameter Symbol Min Typ Max Unit Test conditions Input leakage current I LI 1 µa Vin = V SS to V CC Output leakage current I LO 1 µa CS1# = V IH or CS2 = V IL or OE# = V IH or WE# = V IL or LB# = UB# = V IH, V I/O = V SS to V CC Operating current I CC 20 ma CS1# = V IL, CS2 = V IH, Others = V IH /V IL, I I/O = 0 ma Average operating current I CC1 25 ma Min. cycle, duty = 100%, I I/O = 0 ma, CS1# = V IL, CS2 = V IH, Others = V IH /V IL I CC2 5 ma Cycle time = 1 µs, duty = 100%, I I/O = 0 ma, CS1# 0.2 V, CS2 V CC 0.2 V V IH V CC 0.2 V, V IL 0.2 V Standby current I SB 0.1* 1 0.3 ma CS2 = V IL Standby 5SI +85 C I SB1 10 µa Vin 0 V current +70 C I SB1 8 µa (1) 0 V CS2 0.2 V or 7LI Output high voltage Output low voltage +40 C I SB1 3 µa (2) CS1# V CC 0.2 V, +25 C I SB1 1* 1 2.5 µa CS2 V CC 0.2 V or +85 C I SB1 20 µa (3) LB# = UB# V CC 0.2 V, +70 C I SB1 16 µa CS2 V CC 0.2 V, +40 C I SB1 10 µa CS1# 0.2 V +25 C I SB1 1* 1 10 µa Average values V OH 2.4 V I OH = 1 ma V OH2 V CC 0.2 V I OH = 100 µa V OL 0.4 V I OL = 2 ma V OL2 0.2 V I OL = 100 µa 1. Typ. V CC = 3.0V Ta = +25 C Rev.1.00, 2007.05.24, page 6 of 15
Ta = +25 C f = 1MHz Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pf Vin = 0 V 1 Input/output capacitance C I/O 10 pf V I/O = 0 V 1 1. AC (V CC = 2.7V 3.6V, Ta = 40 +85 C) V IL = 0.4V, V IH = 2.4V 5ns 1.4V 1.4 V RL=500 Ω Dout 50pF Output load Rev.1.00, 2007.05.24, page 7 of 15
R1LV0416D** -5SI -7LI Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 55 70 ns Address access time t AA 55 70 ns Chip select access time t ACS1 55 70 ns t ACS2 55 70 ns Output enable to output valid t OE 35 40 ns Output hold from address change t OH 10 10 ns LB#, UB# access time t BA 55 70 ns Chip select to output in low-z t CLZ1 10 10 ns 2, 3 t CLZ2 10 10 ns 2, 3 LB#, UB# disable to low-z t BLZ 5 5 ns 2, 3 Output enable to output in low-z t OLZ 5 5 ns 2, 3 Chip deselect to output in high-z t CHZ1 0 20 0 25 ns 1, 2, 3 t CHZ2 0 20 0 25 ns 1, 2, 3 LB#, UB# disable to high-z t BHZ 0 20 0 25 ns 1, 2, 3 Output disable to output in high-z t OHZ 0 20 0 25 ns 1, 2, 3 Rev.1.00, 2007.05.24, page 8 of 15
-5SI R1LV0416D** Parameter Symbol Min Max Min Max Unit Notes Write cycle time t WC 55 70 ns Address valid to end of write t AW 50 60 ns Chip selection to end of write t CW 50 60 ns 5 Write pulse width t WP 40 50 ns 4 LB#, UB# valid to end of write t BW 50 55 ns Address setup time t AS 0 0 ns 6 Write recovery time t WR 0 0 ns 7 Data to write time overlap t DW 25 30 ns Data hold from write time t DH 0 0 ns Output active from end of write t OW 5 5 ns 2 Output disable to output in high-z t OHZ 0 20 0 25 ns 1, 2, 3 Write to output in high-z t WHZ 0 20 0 25 ns 1, 2 1. t CHZ t OHZ t WHZ t BHZ 2. 3. t HZ max t LZ min 4. CS1# Low CS2 High WE# Low LB# UB# Low t WP CS1# Low CS2 High WE# Low LB# UB# Low CS1# High CS2 Low WE# High LB# UB# High t WP 5. t CW CS1# Low CS2 High 6. t AS 7. t WR WE# CS1# High CS2 Low -7LI Rev.1.00, 2007.05.24, page 9 of 15
WE# = V IH t RC Address Valid address t AA CS1# tacs1 t CLZ1 * 2, 3 t * 1, 2, 3 CHZ1 CS2 t ACS2 t CLZ2 * 2, 3 t * 1, 2, 3 CHZ2 LB#, UB# OE# t BA t BLZ * 2, 3 t OE t OLZ * 2, 3 t * 1, 2, 3 BHZ t * 1, 2, 3 OHZ t OH Dout High impedance Valid data Rev.1.00, 2007.05.24, page 10 of 15
1 WE# t WC Address Valid address t CW * 5 t WR * 7 CS1# t CW * 5 CS2 t BW LB#, UB# t AW WE# t AS * 6 t WP * 4 t DW t DH Din Dout t WHZ * 1, 2 Valid data High impedance t OW * 2 Rev.1.00, 2007.05.24, page 11 of 15
2 CS# Clock, OE# = V IH t WC Address Valid address t AS * 6 t AW t CW * 5 t WR * 7 CS1# t CW * 5 CS2 t BW LB#, UB# WE# t WP * 4 t DW t DH Din Valid data Dout High impedance Rev.1.00, 2007.05.24, page 12 of 15
3 LB#, UB# Clock, OE# = V IH t WC Address Valid address t AW t CW * 5 t WR * 7 CS1# t CW * 5 CS2 t AS * 6 t BW LB#, UB# WE# t WP * 4 t DW t DH Din Valid data Dout High impedance Rev.1.00, 2007.05.24, page 13 of 15
Ta = 40 +85 C Parameter Symbol Min Typ Max Unit Test conditions V CC for data retention V DR 2.0 V Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V CC 0.2 V, CS1# V CC 0.2 V or (3) LB# = UB# V CC 0.2 V, CS2 V CC 0.2 V, CS1# 0.2 V Data retention current 5SI 7LI +85 C I CCDR 10 µa +70 C I CCDR 8 µa +40 C I CCDR 3 µa +25 C I CCDR 1* 1 2.5 µa +85 C I CCDR 20 µa +70 C I CCDR 16 µa +40 C I CCDR 10 µa +25 C I CCDR 1* 1 10 µa V CC = 3.0 V, Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V CC 0.2 V, CS1# V CC 0.2 V or (3) LB# = UB# V CC 0.2 V, CS2 V CC 0.2 V, CS1# 0.2 V Average values Chip deselect to data retention time t CDR 0 ns See retention waveform Operation recovery time t R 5 ms 1. Typ. V CC = 3.0V Ta = +25 C Rev.1.00, 2007.05.24, page 14 of 15
(1) (CS1# Controlled) (V CC = 2.7V 3.6V) V CC 2.7 V t CDR Data retention mode t R 2.2 V V DR CS1# 0 V CS1# V CC 0.2 V (2) (CS2 Controlled) (V CC = 2.7V 3.6V) V CC 2.7 V CS2 tcdr Data retention mode t R V DR 0.6 V 0 V 0 V < CS2 < 0.2 V (3) (LB#, UB# Controlled) (V CC = 2.7V 3.6V) V CC 2.7 V t CDR Data retention mode t R 2.2 V V DR LB#, UB# 0 V LB#, UB# V CC 0.2 V Rev.1.00, 2007.05.24, page 15 of 15
Rev. 0.01 2006.11.28 1.00 2007.05.24 2 3 4 5 6 7 14 R1LV0416DSB-5S% R1LV0416DSB-5SI R1LV0416DSB-7L% R1LV0416DSB-7LI R1LV0416DBG-5S% R1LV0416DBG-5SI R1LV0416DBG-7L% R1LV0416DBG-7LI A6 A13 A13 A6 R ver. DC R ver. DC I SB1 (-5SI) (~+25 C) max 3µA to 2.5µA AC I CCDR (-5SI) (~+25 C) max 3µA to 2.5µA 2
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