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[] Ver. 1.1 200512 PCI-4159 1.0 200510 63-1 - Interface Corporation
1 4 1.1 ID... 4 1.2HDLC... 4 1.2.1HDLC... 5 1.2.2HDLC... 6 1.2.3OvROvF... 6 1.2.4... 7 1.2.5... 7 1.2.6RS-485... 8 1.2.7... 9 1.2.8TX BRG... 10 1.2.9RX BRG... 10 1.2.10... 11 1.2.11... 12 1.2.12... 12 1.2.13... 13 1.2.14... 14 1.2.15... 14 1.2.16... 15 1.2.17... 15 1.2.18RSW... 15 1.3HDLC... 16 2 HDLC 17 2.1 HDCL... 17 2.1.1... 18 2.1.2... 19 2.1.3... 20 2.1.4... 21 2.1.5... 21 2.2... 21 2.3HDCL... 22 2.4... 22 2.4.1... 22 2.4.2... 22 2.5... 22 2.6... 23 2.7... 23 2.7.1... 24 2.7.2... 25 2.7.3... 26 2.7.4... 30 Interface Corporation - 2 -
2.7.5... 30 2.7.6... 31 2.7.7... 31 2.8... 31 2.8.1... 32 2.8.2... 33 2.8.3... 33 2.8.4... 33 2.8.5... 34 2.8.6... 36 2.8.7... 37 2.8.8... 38 3 39 3.1... 39 3.1.1... 40 3.1.2... 41 3.1.3MSET... 41 3.1.4... 41 3.1.5(MDST )... 42 3.1.6(LOPN )... 45 3.1.7...47 3.1.8(LCLS )... 51 3.2... 52 3.3... 53 4 DOS BPD-0805 54 4.1... 54 4.2... 54 4.3... 54 4.4... 55 APCI-4159... 61 BPCI-4159... 62 63-3 - Interface Corporation
1 1.1ID ID ID ID ID 1147h 104Ch 1147h 0001h Base Address Register 0 32 CH1HDLC Base Address Register 1 1M CH1HDLC Base Address Register 2 32 CH2HDLC Base Address Register 3 1M CH2HDLC Base Address Register 4 Base Address Register 5 IRQ 1 1.2HDLC CH1, CH2 PCI 00h 01h 04h 08h 09h 0Ah 0Ch0Dh 0Eh0Fh 10h 11h 12h HDLC HDLC OvROvF RS-485 RS-485 TXBRG TXBRG RXBRG RXBRG Interface Corporation - 4 -
13h 14h 18h19h 1Ah 1Ch 1Dh 1Fh RSW +00h+1Fh 1.2.1HDLC Offset +00h Byte Word Dword Size 8bit Read Write bit 76 5 4 30 NRDY INT 00 0 0 0000 R/W R R NRDY INT 0 HDLC HDLC HDLC - 5 - Interface Corporation
1.2.2HDLC Offset +00h Byte Word Dword Size 8bit Read Write bit 74 3 2 1 0 CLRI CRST CCRQ 0 0 0 R/W W W W CLRI CRST CCRQ 1HDLC 0 10 1HDLC 0 10 1HDLC 0 10 1.2.3OvROvF Offset +01h Byte Word Dword Size 8bit Read Write bit 72 1 0 OvR OvF 000000 0 0 R/W R R OvR OvF 0 OvR 0 1 0 OvF 0 1 Interface Corporation - 6 -
1.2.4 Offset +04h Byte Word Dword Size 8bit Read Write bit 73 20 CS3CS1 00000 000 R/W R/W CS3CS1 Communication Base Clock CS3 CS2 CS1 19.6608MHz 0 0 0 14.7456MHz 0 0 1 8.192MHz 0 1 0 32 MHz 0 1 1 12.288MHz 1 0 0 58.9824MHz 1 0 1 49.152MHz 1 1 0 1 1 1 1.2.5 Offset +08h Byte Word Dword Size 8bit Read Write bit 73 2 10 I 00000 00 R/W R bit 72 1 0 C 0 R/W W I C I I I 0 (OFF) 1 (ON) C C C 0 (OFF) 1 (ON) - 7 - Interface Corporation
1.2.6RS-485 Offset +09h Byte Word Dword Size 8bit Read Write bit 76 5 4 30 Tenable STenable Renable Cenable 00 00 00 00 R/W R/W R/W R/W R/W Tenable STenable Renable Cenable T Tenable T 00 01 Hdenable1 10 Hdenable0 11 ST STenable ST 00 01 Hdenable1 10 Hdenable0 11 R Renable R 00 01 Hdenable1 10 Hdenable0 11 C Cenable C 00 01 Hdenable1 10 Hdenable0 11 HDenable533.3 Interface Corporation - 8 -
1.2.7 Offset +0Ah Byte Word Dword Size 8bit Read Write bit 76 5 4 3 21 0 DPLL LoopC In/Ex LoopD 00 0 0 0 00 0 R/W R/W R/W R/W R/W DPLL DPLL LoopC DPLL loopc Signal used to generate the RX Clock 0 0 RT() 0 1 TX Clock () 1 X DPLL () In/Ex In/Ex Signal used to generate the TX Clock 00 ST() 01 RT() 1X () LoopD loopd RX Data input 0 R 1 TX Data () NRZ, NRZI 15hRx ClockTx ClockTx ClockInternalRx DataTx Data - 9 - Interface Corporation
1.2.8TX BRG Offset +0Ch, Byte Word Dword +0Dh Size 16bit Read Write bit 70 TB7TB0 00000001 R/W R/W bit 158 TB15TB8 00000000 R/W R/W TB15TB0 0000h (+0Dh) 1.2.9RX BRG Offset +0Eh, Byte Word Dword +0Fh Size 16bit Read Write bit 70 RB7RB0 00000001 R/W R/W bit 158 RB15RB8 00000000 R/W R/W RB15RB0 0000h (+0Fh) Interface Corporation - 10 -
1.2.10 Offset +10h Byte Word Dword Size 8bit Read Write bit 74 30 TD4TD1 0000 0000 R/W R bit 7 64 30 SCLK3SCLK1 TCTL4TCTL1 000 0000 R/W W W TD4TD1 SCK3SCK1 TCTL4TCTL1 TD4TD1TCTL4TCTL1 0h 000 SCK3 0 1 SCK2 0 1 0 1 SCK1 TCTL4 TCTL3 TCTL2 TCTL1 0 1 0 1 0 1 0 1 0 0 0 1 10 100 1m 10m 100m 1 0 20 200 2m 20m 200m 0 1 30 300 3m 30m 300m 0 0 40 400 4m 40m 400m 1 1 50 500 5m 50m 500m 1 0 60 600 6m 60m 600m 1 70 700 7m 70m 700m 0 0 80 800 8m 80m 800m 0 1 90 900 9m 90m 900m 1 0 100 1000 10m 100m 1000m 1 1 110 1100 11m 110m 1100m 0 0 120 1200 12m 120m 1200m 1 1 130 1300 13m 130m 1300m 1 0 140 1400 14m 140m 1400m 1 150 1500 15m 150m 1500m TCTL4 TCTL1 0h - 11 - Interface Corporation
1.2.11 Offset +11h Byte Word Dword Size 8bit Read Write bit 71 0 RST 000000 0 R/W W RST 1 1.2.12 Offset +12h Byte Word Dword Size 8bit Read Write bit 7 6 5 4 3 2 10 OvF/OvR IDLE HDLCI INT I 0 0 0 0 0 0 00 R/W R R R R R OvF/OvR IDLE HDLCI INT I 0 OvF/OvR 0 1 0 IDLE 0 1 HDLC 0 HDLCI HDLC 0 1 0 INT 0 1 I 0 I I 0 1 Interface Corporation - 12 -
1.2.13 Offset +13h Byte Word Dword Size 8bit Read Write bit 7 6 5 4 3 2 10 OvF/OvR IDLE HDLCI INT I 0 0 0 0 0 0 00 R/W R/W R/W R/W R/W R/W OvF/OvR OvF/OvR 0 1 IDLE IDLE 0 1 HDLCI HDLC HDLCI HDLC 0 1 INT INT 0 1 I I I I 0 1-13 - Interface Corporation
1.2.14 Offset +14h Byte Word Dword Size 8bit Read Write bit 73 2 10 I 00000 0 00 R/W R/W I I I I 0 1 1.2.15 Offset +18h, +19h, Byte Word Dword +1Ah Size 24bit Read Write bit 70 ID7ID0 00000000 R/W R/W bit 158 ID15ID8 00000000 R/W R/W bit 2316 ID23ID16 00000000 R/W R/W ID23ID00 =ID23ID0 1µs 000000h (+1Ah) Interface Corporation - 14 -
1.2.16 Offset +1Ch Byte Word Dword Size 8bit Read Write bit 70 HDED7HDED0 00000000 R/W R/W HDED7 HDED0 = HDED7HDED0 1 / 1.2.17 Offset +1Dh Byte Word Dword Size 8bit Read Write bit 70 HDDD7HDDD0 00000000 R/W R/W HDDD7 HDDED0 =HDDD7HDDD0 1 / 1.2.18RSW Offset +1Fh Byte Word Dword Size 8bit Read Write bit 74 30 BID3BID0 R/W R BID3BID0 IDRSW BID3BID0 RSW 0000 0 0001 1 1110 E 1111 F - 15 - Interface Corporation
1.3HDLC HDLC CH1,CH21M172HDLC Interface Corporation - 16 -
2HDLC HDLCCPU CPU 2.1 HDCL - 17 - Interface Corporation
2.1.1 HDLC MSET LCWLink Command Word16 nlcwlcwn1n128n2mset CMDN 0xFF 0x00 CMDS 0xFC HDLC 0xFE HDLC 0x0C HDLC INFO Command Table LCW0 LCW1.... CMDN CMDS * * * * * * * * * * * * * * Link Command Word (LCW) 16 bytes LCW(n-1) *: INFO Interface Corporation - 18 -
2.1.2 HDLC LSWLink Status Word16 nlswlswn1n128n2mset STSN INFO FFh FFhHDLC Status Table 0<n<129 LSW0 LSW1.... STSN * * * * * * * * * * * * * * * Link Status Word (LSW) 16 bytes LSW(n-1) *: INFO - 19 - Interface Corporation
2.1.3 HDLC LRBWLink Receive Buffer Address Word4nLRBW LRBWn1n128n2MSET BRDY RBA HDLC00h FFh F0h FFh 00h HDLC00h HDLC LOPN Receive Buffer Address Table 0<n<129 LRBW0 LRBW1.... BRDY RBA (LSBs) RBA RBA (MSBs) The RBA is the actual RX Buffer Address Link RX Buffer Word (LRBW) 4 bytes LRBW(n-1) LRBW(1)LRBW(3)LRBW(0)00h Interface Corporation - 20 -
2.1.4 HDLC MDST 16383 2.1.5 HDLC DTSD 16383 2.2 MSET ADDR 000000h NLCW 32 NLSW 32 NLRBW 16 Memory Address 0x0000 to 0x01FF 0x0200 to 0x03FF 0x0400 to 0x043F Command Table Status Table RX Buffer Address Table 32 LCWs (16 bytes/lcw) 32 LSWs (16 bytes/lsw) 16 LRBWs (4 bytes/lrbw) 0x10000 to 0x4FFFF 0x50000 to 0x8FFFF TX Buffer RX Buffer 16 Buffer Slots (0x4000 bytes/slot) 16 Buffer Slots (0x4000 bytes/slot) - 21 - Interface Corporation
2.3HDCL HDLCCPU FFh 2.4 2 2.4.1 00h1MSET HDLCCCRQ1 2.4.2 MSET (1) LCWCMDS FCh, FEh, FFh CMDS FCh, FEh, FFh LCWCMDS FCh, FEh, FFh (2) LCW(2)(15)LCW(0) LCW(1)00hLCW(1) (3) HDLCCCRQ1 CMDS FCh, FEh 2.5 CPUHDLC CCRQ1 (1) (2) HDLCCCRQ 1 Interface Corporation - 22 -
2.6 HDLC HDLCINT1 HDLCHDLC CPUINTHDLC (1) HDLCCLRI1INT (2) (3) LSW(0)FFh (2) 2.7 HDLC 31h DTSD 34h MSET 35h MDST 36h AFST 37h LOPN 38h LCLS 3Dh SIRD - 23 - Interface Corporation
2.7.1 7 6 5 4 3 2 1 0 LCW(0) CMDN(31h) LCW(1) 0 0 0 0 0 0 0 0 LCW(2) CB 0 0 0 TXBC LCW(3) LCW(4) LCW(5) LCW(6) LCW(7) LCW(8) LCW(9) LCW(10) LCW(11) LCW(12) LCW(13) LCW(14) LCW(15) BC BUFA TXDT TXBC 08 8 BC BC0163830H3FFFh BUFA CB CB 0 1 TXDT CMDN Interface Corporation - 24 -
2.7.2 7 6 5 4 3 2 1 0 LCW(0) CMDN(34h) LCW(1) 0 0 0 0 0 0 0 0 LCW(2) LCW(3) LCW(4) (L) ADDR (M) (H) LCW(5) NLCW LCW(6) NLSW LCW(7) NLRBW ADDR NLCW NLCW11282116 NLSW NLSW11282116 NLRBW NLRBW1128214 ADDR の下位 4 ビットは 0 を設定してください - 25 - Interface Corporation
2.7.3 7 6 5 4 3 2 1 0 LCW(0) CMDN(35h) LCW(1) 0 0 0 0 0 0 0 0 LCW(2) 0 TFIL CODE SAF DMAW LCW(3) 0 0 0 SHORT AUTO LCW(4) 0 LAP 0 0 FCS D LCW(5) 0 0 0 TXED STBC LCW(6) 0 0 0 0 0 0 0 0 LCW(7) RXBS(LSB) LCW(8) RXBS(MSB) LCW(9) MAXD(LSB) LCW(10) MAXD(MSB) LCW(11) 0 0 0 0 0 0 0 0 LCW(12) 0 0 0 0 0 0 0 0 TFIL 0 TFIL 0 1 1 1 CODE 0 CODE 0 NRZ 1 NRZI SAF 0 SAF 0 1 Interface Corporation - 26 -
DMAW DMA 4 SHORT 00 SHORT 00 2 01 3 10 4 11 ショートフレームについての注意事項 16bitFCS 設定の場合 フラグ - フラグ間が 24bit 未満のフレームはアボート フレームとして扱われます ( ショート アボート フレーム ) 32bitFCS 設定の場合 フラグ - フラグ間が 40bit 未満のフレームはアボート フレームとして扱われます ( ショート アボート フレーム ) ショート アボート フレームとアボート フレームの見分け方は次の通り ショート アボート フレーム : アボートかつ受信データの最後の 1 バイトが 7Eh アボート フレーム : アボートかつ受信データの最後の 1 バイト 7Eh でない AUTO 00 AUTO 00 01 10 11 LAPD LAPD1LAPD 0533.3-27 - Interface Corporation
FCS FCS 0000 Bit3 Bit2 Bit1 Bit0 16-bit/ CRC-16/ Initial Final 32-bit CCITT (*1) XOR XOR 0 0 0 0 CRC-16 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 CRC-CCITT 0 1 0 1 0 1 1 0 0 1 1 1 FCS 16 1 X 0 0 1 X 0 1 1 X 1 0 1 X 1 1 FCS 32 *116bitFCS CRC-CCITT G(x) = x 16 +x 12 +x 5 +1 CRC-16 G(x) = x 16 +x 15 +x 2 +1 TXED TXED 0 TXED 0 1 STBC STBC0 STBCAUTOSHORT AUTO SHORT STBC 00 00 STBC=0, 2STBC8 00 01 STBC=0, 3STBC8 00 10 STBC=0, 4STBC8 01/11 00 2STBC8 01/11 01 3STBC8 01/11 10 4STBC8 RXBS RXBS0163830h3FFFh Interface Corporation - 28 -
MAXD MAXD RXBS (NLRBW 4) NLRBWMSET MAXD0163830h3FFFh MDST DMAB DMA DMAB 8/ LOAK LOAK LOAK OCT OCT BUFC BUFC BUFE BUFE - 29 - Interface Corporation
2.7.4 7 6 5 4 3 2 1 0 LCW(0) CMDN(36h) LCW(1) 0 0 0 0 0 0 0 0 LCW(2) 0 0 0 0 BC LCW(3) LCW(4) LCW(5) LCW(6) LCW(7) LCW(8) LCW(9) AF LCW(10) LCW(11) LCW(12) LCW(13) LCW(14) AUTO BC MDST AUTO=01 1BC12 AUTO=11 BC=2.4.6.8.10.12 AF AUTO=01LCW3141 AUTO=11LCW31LCW42 2 2.7.5 7 6 5 4 3 2 1 0 LCW(0) CMDN(37h) LCW(1) 0 0 0 0 0 0 0 0 TFIL 0 Interface Corporation - 30 -
2.7.6 7 6 5 4 3 2 1 0 LCW(0) CMDN(38h) LCW(1) 0 0 0 0 0 0 0 0 TFIL 0 2.7.7 7 6 5 4 3 2 1 0 LCW(0) CMDN(3Dh) LCW(1) 0 0 0 0 0 0 0 0 SIAK 2.8 HDLC 31h DTRV 37h LOAK 38h LCAK 39h TXED 3Dh SIAK 3Fh CILG 41h GI2C 43h OLSW - 31 - Interface Corporation
2.8.1 7 6 5 4 3 2 1 0 LCW(0) STSN(31h) LCW(1) Don t care LCW(2) CB ERR RXBC LCW(3) LCW(4) BC LCW(5) LCW(6) BUFA LCW(7) LCW(8) LCW(9) LCW(10) LCW(11) LCW(12) RXDT LCW(13) LCW(14) LCW(15) RXBC 08 8 ERR DTRV MDSTSAF1 Priority Meaning Code - Normal Frame (no error) 000 1 (high) Abort Frame 001 2 Short Frame 100 3 No Address 101 4 Long Frame 011 5 (low) FCS Error Frame 010 BC BC016383(0H3FFFH) CB 0 1 Interface Corporation - 32 -
BUFA RXDT DTRV 2.8.2 LCW(0) 7 6 5 4 3 2 1 0 STSN(37h) LOPN 2.8.3 LCW(0) 7 6 5 4 3 2 1 0 STSN(38h) LCLS 2.8.4 LCW(0) LCW(1) 7 6 5 4 3 2 1 0 STSN(39h) TXEN MDSTTXED=1DTSD TXEN - 33 - Interface Corporation
2.8.5 LCW(0) LCW(1) LCW(2) LCW(3) LCW(4) LCW(5) LCW(6) LCW(7) LCW(8) LCW(9) LCW(10) LCW(11) LCW(12) 7 6 5 4 3 2 1 0 STSN(3Dh) COUNT OVRN UNRN (00h) SHORT ADDR LONG ABORT FCS (00h) FLSW FLRBW SIRD COUNT LSW(2)LSW(12)00hCOUNT00h LSW(2)LSW(12)01h OVRN FIFO UNRM FIFO SHORT Interface Corporation - 34 -
ADDR MDSTAUTO=01 AFST LONG MDSTRXBS ABORT 7 1 FCS CRCFCS FLSW FLRBW 1 2 3 4 5 6 FCS FFhFFh - 35 - Interface Corporation
2.8.6 LCW(0) LCW(1) LCW(2) LCW(3) LCW(4) 7 6 5 4 3 2 1 0 STSN(3Fh) ILST LSTN (00h) CMDN ILST 00h 02hFIFO 03hDTSD LSTN 00h 02h CMDN Interface Corporation - 36 -
2.8.7 7 6 5 4 3 2 1 0 LCW(0) STSN(41h) LCW(1) GI2F GI1F GO2F GO1F GI2 GO1F GO1 GO1F GO1 0 L 1 H GO2F GO2 GO2F GO2 0 L 1 H GI1F GI1 GI1F GI1 0 L 1 H GI2F GI2 GI2F GI2 0 L 1 H GI2533.3 GO1, GO2, GI2-37 - Interface Corporation
2.8.8 7 6 5 4 3 2 1 0 LCW(0) STSN(43h) LCW(1) GI2F GI1F GO2F GO1F LCW(2) LSTN GO1F GO1 GO1F GO1 0 L 1 H GO2F GO2 GO2F GO2 0 L 1 H GI1F GI1 GI1F GI1 0 L 1 H GI2F GI2 GI2F GI2 0 L 1 H LSTN 00h 02h GI2533.3 GO1, GO2, GI2 Interface Corporation - 38 -
3 3.1 MSET MDST LOPN LCLS - 39 - Interface Corporation
3.1.1 RS-485 91.2.7 (bps) (bps) = (bps) = 16 71.2.4 TXBRGRXBRG 101.2.8TX BRG 101.2.9RX BRG RS-485 TCSTR RS-48581.2.6RS-485 1 HDLC Interface Corporation - 40 -
3.1.2 HDLCFFh2 3.1.3MSET MEST 2 000000h 32 32 16 3.1.4 HDLC MSET 3.1.300400h0043fh 00000h 001FFh 00200h 003FFh 00400h 0043Fh 00440h FFFFFh - 41 - Interface Corporation
3.1.5(MDST) MDST 3 TFIL 0 CODE 0 NRZ SAF 0 DMAW 4 = 4 SHORT 0 AUTO 0 LAPD 0 LAPD FCS 0 FCS = CRC-16 TXED 0 LSW STBC 0 = 0 RXBS 3FFFh = 3FFFh MAXD 3FFFh = 3FFFh Interface Corporation - 42 -
- 43 - Interface Corporation 2 HDLC
Interface Corporation - 44-3 HDLC
- 45 - Interface Corporation 3.1.6(LOPN) LOPNHDLC LOPN4 MDSTTFIL TFIL 0 1 1 1 HDLCLOPNLOAK 5 HDLC 4LOPN HDLC
Interface Corporation - 46-5 HDLC
3.1.7 DTSD DTSD6 HDLCMDSTTXED DTSDDTSD 8 DTSDDTSD HDLCDTSDBUFA DTSD 116K DTSD DSTDDTSDCB1 DTSD DTSD HDLCDTRV 7 HDLCDTRV DTRVMDSTSTBC DTRVMDSTSTBC HDLCMDSTRXBSMAXD DTRVBUFABC - 47 - Interface Corporation
HDLC MDSTAUTO AFST AFST MDSTSAF SAF 0 SAF 1 262.7.3 Abort Frame FCS Error Frame Long Frame Short Frame No Address 7 1 FCS MDSTRXBS MDSTSHORT AFST Interface Corporation - 48 -
- 49 - Interface Corporation 6 HDLC
Interface Corporation - 50-7 HDLC
- 51 - Interface Corporation 3.1.8(LCLS) LCLSHDLC HDLCLCLS LCLS8 HDLCLCLSLCAK 8LCLS HDLC
3.2 アイドル検出 NRZ NRZI R R 0µs16777215µs 141.2.15 0µs 131.2.13 アイドル検出時間設定時 すでに設定した検出時間以上アイドル状態が続いていれば 直ちに割り込みが出力されます Interface Corporation - 52 -
3.3 半二重制御 LAP-D LAP-DRS-485T, ST, C, RHdenable 81.2.6RS-485 HDenableHDLCGO3 GI2 /GO3 HDLC HDLC /GI2 HDLC HDLC HDenableGI2 151.2.16151.2.17 GO3GO3-53 - Interface Corporation
第 4 章 DOS からのリソース取得 (BPD-0805) 4.1 概要 DOSPCIBPD-0805 BPD-0805Web sitereadme.txt 4.2 プログラム作成時の注意 4.3 対応言語 PC-9801/9821 IBM PC/AT Borland C++ Ver. 4.0 Borland C++ Ver. 4.0 Borland C++ Ver. 4.5 Borland C++ Ver. 4.5 Borland C++ Ver. 5.0 Borland C++ Ver. 5.0 Turbo C++ 1.01 2nd Edition Turbo C++ Ver. 4.0 Turbo C++ Ver. 4.0 Microsoft C Ver. 6.0 Microsoft C Ver. 6.0 Microsoft C/C++ Ver. 7.0 Microsoft C/C++Ver. 7.0 Interface Corporation - 54 -
4.4 関数説明 PciGetConfigReg PCI BIOSPCI int PciGetConfigReg( int index, unsigned int ven_id, unsigned int dev_id, unsigned long bar[], char *irq ) index RSW1 1 ven_id ID ID1147h dev_id ID ID417216104C bar[6] BaseAddress0BaseAddress5 bar[0]baseaddress0ch1 HDLC bar[1]baseaddress1ch1 HDLC bar[2]baseaddress2ch2 HDLC bar[3]baseaddress3ch2 HDLC irq 0 1PCI BIOS 21 3-55 - Interface Corporation
#include <stdio.h> #include GETBAR.H void main ( void ) { unsigned long bar[6], adr0, adr1, adr2, adr3; char irq; } PciGetConfigReg ( 1, 0x1147, 4172, bar, &irq ); // Adr0 = bar[0]; // CH1 HDLC Adr1 = bar[1]; // CH1 HDLC Adr2 = bar[2]; // CH2 HDLC Adr3 = bar[3]; // CH2 HDLC printf ( CH1 %8x, %8x n, adr0, adr1); printf ( CH2 %8x, %8x n, adr2, adr3); printf ( %d n, irq ); Interface Corporation - 56 -
PciGetConfigRegEx PCI BIOSPCI int PciGetConfigRegEx( int index, unsigned int ven_id, unsigned int dev_id, unsigned int subven_id, unsigned int subsys_id, unsigned int *bus_info, PPCI_CONFIG PciData ) index RSW1 11 ven_id ID ID1147h dev_id ID ID417216104Ch subven_id ID ID1147h subsys_id ID ID0001h bus_info bit15bit8 bit7bit3 bit2bit0 PciData PCI 0 1PCI BIOS 21 3-57 - Interface Corporation
#include <stdio.h> #include GETBAR.H void main ( void ) { unsigned long adr0, adr1, adr2, adr3; unsigned int bus_info; PCI_CONFIG PciData; PciGetConfigRegEx ( 1, 0x1147, 4172, 0x1147, 0x0001, &bus_info, &PciData ); // } adr0 = bar[0]; // CH1 HDLC adr1 = bar[1]; // CH1 HDLC adr2 = bar[2]; // CH2 HDLC adr3 = bar[3]; // CH2 HDLC printf ( CH1 %8x, %8x n, adr0, adr1); printf ( CH2 %8x, %8x n, adr2, adr3); Interface Corporation - 58 -
PCI_CONFIG PCI typedef struct _PCI_CONFIG { unsigned short VendorID; // 00: Vendor ID unsigned short DeviceID; // 02: Device ID unsigned short Command; // 04: Command unsigned short Status; // 06: Status unsigned char RevisionID; // 08: Revision unsigned char ProgIf; // 09: ProgIf unsigned char SubClass; // 0A: Sub Class unsigned char BaseClass; // 0B: Base unsigned char CacheLineSize; // 0C: Cache Line unsigned char LatencyTimer; // 0D: Latency unsigned char HeaderType; // 0E: Header unsigned char BIST; // 0F: BIST unsigned long BaseAddresses[6]; // 10: Base Address unsigned long CIS; // 28: CIS Pointer unsigned short SubVendorID; // 2C: Subsystem Vendor ID unsigned short SubSystemID; // 2E: Subsystem ID unsigned long ROMBaseAddress; // 30: ROM Base Address unsigned char CapabilitiesPtr; // 34: Capabilities Pointer unsigned char Reserved1[3]; // 35: Reserved unsigned long Reserved2[1]; // 38: Reserved unsigned char InterruptLine; // 3C: INT Line unsigned char InterruptPin; // 3D: INT Pin unsigned char MinimumGrant; // 3E: MIN_GNT unsigned char MaximumLatency; // 3F: MAX_LAT unsigned char DeviceSpecific[192]; // 40: } PCI_CONFIG, *PPCI_CONFIG; - 59 - Interface Corporation
BaseAddresses[6] BaseAddress0BaseAddress5 bar[0]baseaddress0ch1 HDLC bar[1]baseaddress1ch1 HDLC bar[2]baseaddress2ch2 HDLC bar[3]baseaddress3ch2 HDLC InterruptLine RevisionID Revision PCI Interface Corporation - 60 -
付録 A PCI-4159 との機能比較 HDLC *1 (*1) PCI-4159 M M DTSD '0' MSET MDST AFST LOPN LCLS MARD MDRD AFRD SIRD GOWR GPRD SIRE GRPE MDSE AFSE DTRV '0' TXUR TOUT LOAK LCAK TXED MAAK MDAK AFAK SIAK CILG GI1C GI2C GPAK OLSW SIAF GPAE NRZ NRZI FCS / CRC-16 CRC-ITU-T FCS-16 FCS-32 1/8bit 2/8bit 1/16bit *1 0µs 16777215µs 8ms 100ms - 61 - Interface Corporation
付録 B PCI-4159 とのレジスタマップ比較 00h 01h 04h 08h + 09h 0Ah 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 18h 19h 1Ah 1Ch 1Dh 1Fh PCI-4159 HDLC µpd72103 HDLC µpd72103 OvROvF RS-485 / RS-485 / TXBRG TXBRG BRG RXBRG RXBRG BRG RSW RSW1 Interface Corporation - 62 -
重要な情報 / USER S MANUAL - 63 - Interface Corporation
I/O 2005 12 IPB-J4172Ver.1.1 Dream & Freedom 732-0828 10-21 TEL 082-262-7777 FAX 082-262-5066 Interface Corporation - 64 -
IPB-J4172Ver. 1.1Vol. 1/1