TC59LM836DKG-33,-40 MOS CMOS 288M FCRAM2 2,097,152 4 36 TC59LM836DKG CMOS 301,989,888 (FCRAM TM ) TC59LM836DKG 2,097,152 4 36bit / 600M / FCRAM TM DDR SDRAM TC59LM836DKG t CK ( ) TC59LM836DKG -33-40 4.5 ns 5.0 ns CL = 5 3.75 ns 4.5 ns CL = 6 3.33 ns 4.0 ns t RC / ( ) 22.5 ns 25 ns t RAC ( ) 22.5 ns 25 ns I DD1S ( ) ) 360 ma 340 ma l DD2P ( ) ) 95 ma 90 ma l DD6 ( ) 15 ma 15 ma (DDR) /( / ) / ( & ) CS FN ( & ) : 300 MHz : 600 M / 4 & ( 3.9 µs) = CAS 1 CAS / CAS = 4, 5, 6 = 2, 4 : 2,097,152 4 36 VDD: 2.5 V ± 0.125V VD: 1.4 V ~ 1.9 V : SSTL_18 (Half strength driver) / HSTL JTAG : 144Ball BGA, 1mm 0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ) : FCRAM ( ) 2005-11-08 1/65
A0~A13 BA0, BA1 0~35 CS FN PD, L, U L, U V DD V SS V D V SSQ V REF NC TMS, TDI, TCK, TDO (+2.5 V) ( ) (+1.5V / +1.8 V) ( ) ( ) ( ) 2005-11-08 2/65
( ) ball pitch=1.0 x 0.8mm 1 2 3 4 5 6 7 8 9 10 11 12 Index 0.8mm A V DD V SS V SS V DD V DD V SS V SS V DD B V D 16 17 V D V D 0 1 V D 1mm C V SSQ 14 15 V SSQ V SSQ 2 3 V SSQ D V D 12 13 V D V D 4 5 V D E V SSQ 10 11 V SSQ V SSQ 6 7 V SSQ F V D L 9 V D V D 8 L V D G V SSQ V REF V SSQ V SSQ A13 FN V SSQ H V SS PD V SS V SS CS NC V SS J V DD A12 A11 V DD V DD BA1 BA0 V DD K V SS A9 A8 V SS V SS A0 A10 V SS L V DD A7 A6 V DD V DD A2 A1 V DD M V D A5 A4 V D V D NC A3 V D N V SSQ U 26 V SSQ V SSQ 27 U V SSQ P V D 25 24 V D V D 29 28 V D R V SSQ 23 22 V SSQ V SSQ 31 30 V SSQ T V D 21 20 V D V D 33 32 V D U V SSQ 19 18 V SSQ V SSQ 35 34 V SSQ V TMS TCK V SS V DD V DD V SS TDO TDI : Depopulated ball 2005-11-08 3/65
PD CS FN A0~A13 BA0, BA1 DLL #1 #0 #3 #2 / L L U U 0~17 18~35 : TC59LM836DKG 4 16384 128 36 2005-11-08 4/65
V DD 0.3~ 3.3 V V D ( ) 0.3~V DD + 0.3 V V IN 0.3~V DD + 0.3 V V OUT ( ) 0.3~V D + 0.3 V V REF 0.3~V DD + 0.3 V T opr ( ) 0~85 C T stg 55~150 C T solder (10 ) 260 C P D 2.5 W I OUT ±50 ma : DC, AC ( : 1)(T CASE = 0~85 C) V DD 2.375 2.5 2.625 V V D ( ) 1.4 1.9 V V REF V D /2 95% V D /2 V D /2 105% V 2 V IH (DC) V IL (DC) V ICK (DC) V ID (DC) V IH (AC) V IL (AC) V ID (AC) V X (AC) V ISO (AC) (DC) V REF + 0.125 V D + 0.2 V 5 (DC) 0.1 V REF 0.125 V 5 DC 0.1 V D + 0.1 V 10 (DC) 0.4 V D + 0.2 V 7, 10 (AC) V REF + 0.2 V D + 0.2 V 3, 6 (AC) 0.1 V REF 0.2 V 4, 6 (AC) 0.55 V D + 0.2 V 7, 10 (AC) V D /2 0.125 V D /2 + 0.125 V 8, 10 (AC) V D /2 0.125 V D /2 + 0.125 V 9, 10 2005-11-08 5/65
: (1) VSS VSSQ (2) VREF VD (DC) VREF VREF (DC) ±2% (3) : 5 ns VIH (max) = VD + 0.7 V (4) : 5 ns VIL (min) = 0.7 V (5) VIH (DC) VIL (DC) (6) VIH (AC) VIL (AC) (7) VID (8) VX (AC) VD/2 (9) VISO {VICK () + VICK ( )} /2 (10) V SS V ID (AC) V x V x V x V x V x V ICK V ICK V ICK V ICK V ID (AC) 0 V Differential V ISO V ISO (min) V ISO (max) V SS (11) (VTT) VREF (DC) ± 0.04 V (V DD = 2.5V, V D = 1.8 V, f = 1 MHz, Ta = 25 C) (MAX) C IN C INC C I/O (, ) 1.5 3.0 0.25 pf (, ) 1.5 3.0 0.25 pf (, L, U, L, U) 2.5 3.5 0.5 pf C NC NC 1.5 pf : 2005-11-08 6/65
(V DD = 2.5V ± 0.125V, V D = 1.4V ~ 1.9V, T CASE = 0 ~ 85 C) TC59LM836DKG-33,-40-33 -40 I DD1S I DD2N I DD2P I DD4W I DD4R I DD5B I DD6 / t CK = min I RC = min I OUT = 0mA Burst Length = 4 CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D I RC 2 1 2 : t CK = min CS = V IH PD = V IH 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D 4 t CK 1 1 2 360 340 1, 2 110 100 1, 2 ( ) : t CK = min PD = V IL ( ) CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max), V IH (AC) (min) V IN V D 4 t CK 1 (V D /2) 95 90 1, 2 (4 ) 4 t CK = min, I RC = min ma Burst Length = 4 CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D 1 1 2 800 750 1, 2 (4 ) 4 t CK = min I RC = min I OUT = 0mA Burst Length = 4 CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D 1 1 2 800 750 1, 2 t CK = min I REFC = min CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D I REFC 2 1 2 360 340 1, 2, 3 PD = 0.2 V 15 15 (V D /2) (V D /2) 2 : 1. t CK t RC I RC 2. V DD V SS 3. I DD5B t REFI 2005-11-08 7/65
(V DD = 2.5V ± 0.125V, V D = 1.4V ~ 1.9V, T CASE = 0 ~ 85 C) ( ) I LI I LO ( 0 V V IN V D 0 V) ( 0 V V OUT V D ) 5 5 µa 5 5 µa I REF V REF 5 5 µa I OH (DC) Normal Output V OH = 1.420 V 5.6 I OL (DC) Driver V OL = 0.280 V 5.6 I OH (DC) Strong Output V OH = 1.420 V 9.8 I OL (DC) Driver (V D = 1.7V~1.9V) V OL = 0.280 V 9.8 ma 1 I OH (DC) Weak V OH = 1.420 V 2.8 I OL (DC) Output Driver V OL = 0.280 V 2.8 I OH (DC) Normal Output V OH = V D 0.4V 4 I OL (DC) Driver V OL = 0.4V 4 I OH (DC) Strong Output V OH = V D 0.4V 8 I OL (DC) Driver (V D = 1.4V~1.6V) V OL = 0.4V 8 ma 1 I OH (DC) Weak Output I OL (DC) Driver : 1. 2005-11-08 8/65
AC ( : 1, 2) (V DD = 2.5 ± 0.125V, V D = 1.4 1.9V, T CASE = 0 85 C) -33-40 t RC 22.5 25 3 C L = 4 4.5 7.5 5.0 7.5 3 t CK C L = 5 3.75 7.5 4.5 7.5 3 C L = 6 3.33 7.5 4.0 7.5 3 t RAC 22.5 25 3 t CH 0.45 t CK 0.45 t CK 3 t CL 0.45 t CK 0.45 t CK 3 t CK 0.45 0.45 0.5 0.5 3, 8, 10 t Q 0.25 0.3 t QA ( ) 0.35 0.4 t AC 0.5 0. 5 0.6 0.6 3, 8, 10 t OH 0.5 0.5 0.6 0.6 3, 8 t HP t P Min(t CH, (t CH t CL ) t CL ) min(t CH, t CL ) 3 ( ) t HP t QHS t HP t QHS 4, 8 t QV t HP t QHS t HP t QHS 4, 8 t QHS t SS t PRE 0.055 t, CK +0.17 0.055 t CK +0.17 ( ) ns 0.8 t CK 1.2 t CK 0.8 t CK 1.2 t CK 3 ( ) 0.4 t CK 0.4 t CK 4 t PRES 1st 0 0 3 t PREH 1st 0.3 t CK 0.3 t CK 3 t P 0.45 t CK 0.55 t CK 0.45 t CK 0.55 t CK 4 t S t PST t PSTH C L = 4 0.8 1.0 3, 4 ( ) C L = 5 0.8 1.0 3, 4 C L = 6 0.8 1.0 3, 4 ( ) 0.45 t CK 0.45 t CK 4 C L = 4 0.8 1.0 3, 4 ( ) C L = 5 0.8 1.0 3, 4 C L = 6 0.8 1.0 3, 4 t SK U L 0.4 t CK 0.4 t CK 0.4 t CK 0.4 t CK t 0.35 0.4 4, 11 t DH 0.35 0.4 4, 11 t IS t IH / 0.6 0.7 3 / 0.6 0.7 3 2005-11-08 9/65
AC ( : 1, 2) ( ) -33-40 t LZ t HZ 0.5 0.6 3, 6, 8 0.5 0.6 3, 7, 8 t QPDH PD 0 0 t PDEX 0.6 0.7 ns 3 t T t FPDL / 0.1 1 0.1 1 PD ( ) 0.5 t CK 5 0.5 t CK 5 t REFI 0.4 3.9 0.4 3.9 5 µs t PAUSE 200 200 I RC I RCD I RAS I RBD C L = 4 5 5 / ( ) C L = 5 6 6 C L = 6 7 7 RDA/WRA LAL ( ) 1 1 1 1 C L = 4 4 4 LAL RDA/WRA C L = 5 ( ) 5 5 C L = 6 6 6 2 2 ( ) 3 I RWD I WRD I RSC I PD I PDA I PDV I REFC I CKD I LOCK B L = 2 2 2 RDA LAL WRA ( ) B L = 4 3 3 WRA LAL RDA ( ) 1 1 C L = 4 7 7 C L = 5 7 7 C L = 6 7 7 PD 2 2 PD 1 1 C L = 4 19 19 REF C L = 5 23 23 C L = 6 25 25 C L = 4 19 19 C L = 5 23 23 C L = 6 25 25 REF I REFC I REFC ( ) DLL (RDA ) 200 200 cycle 2005-11-08 10/65
AC V IH (min) V IL (max) (AC) V REF + 0.2 V (AC) V REF 0.2 V V REF V D /2 V V TT V REF V V SWING 0.8 V Vr V X (AC) V V ID (AC), 1.0 V SLEW 2.5 V/ns V OTR V D /2 V 9 V D V SWING V IH min (AC) V REF Output 25 Ω V TT V IL max (AC) V SS T T SLEW = (V IH min (AC) V IL max (AC))/ T Measurement point AC Test Load : (1) VIH min (DC) VIL max (DC) (2) Cycle tck 2 ( : tss = 0.8 tck, tck = 3.3 ns, 0.8 3.3 ns = 2.64 ns 2.7 ns.) (3) ( ) AC (4) VREF (5) trefi (max) trefi (min) trefi (min) 8 400ns 3.2 µs (8 400 ns) (6) VD/2 ± 0.1 V (7) (8) (9) Normal Output Driver VD = 1.4V~1.6V Strong Output Driver (10) tck 6.0ns tck 6.0ns Speed version tck (MIN/MAX) = 0.6ns / 0.6ns, tac (MIN/MAX) = 0.65ns / 0.65ns (11) VD = 1.7V~1.9V VD = 1.4V~1.6V Speed version t(min) = 0.4ns, tdh(min) = 0.4ns 2005-11-08 11/65
(1) (VDD VD) PD ( 0.2 V) (2) VD VDD VDD (3) VREF VD VD (4) ( ) 200 µs (5) NOP(DESL) PD (6) EMRS DLL ( 1) (7) MRS CAS (CL) (BT) (BL) ( 1) (8) 2 ( 1) (9) EMRS 200 : (1) (6) (7) (8) (2) (3) V DD 2.5V(TYP) 1.5V or 1.8V(TYP) V D 1/2 V D (TYP) V REF t PDEX 200us(min) l RSC l RSC l REFC l REFC PD l PDA l LOCK = 200clock cycle(min) Command DESL RDA MRS DESL RDA MRS DESL WRA REF DESL WRA REF DESL Address op-code EMRS op-code MRS (Input) L/U (Uni- mode) L/U (Free Running mode) EMRS MRS Auto Refresh cycle Normal Operation 2005-11-08 12/65
t CK t CK t CH t CL t IS t IH t IS t IH CS 1st 2nd t IS t IH t IS t IH FN 1st 2nd t IS t IH t IS t IH A0~A13 BA0, BA1 UA, BA LA L/U t t DH t tdh n t t DH t t DH m, t CH t CL V IH V IH (AC) V IL (AC) V IL t CK t T t T V IH V ID (AC) V X V X V X V IL 2005-11-08 13/65
(Burst Length = 4) Unidirectional / mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 4 t CK t P t P t CK t CK L t QA t QA t LZ t QV t QV t Q t HZ t Q t Q L t AC t AC t AC Q0 Q1 Q2 Q3 t QA t QA t OH t CK t P t P t CK U t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH CAS latency = 5 t CK t P t P t CK t CK L t QA t QA t LZ t Q t Q t QV t Q t QV t HZ L t AC t AC t AC Q0 Q1 Q2 Q3 t QA t QA t OH t CK t CK t P t P U t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH 2005-11-08 14/65
(Burst Length = 4) Unidirectional / mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 6 L L U t QA t LZ t Q t CK t CK t Q t P t P t CK t QV t Q t QV t HZ t AC t AC t AC Q0 Q1 Q2 Q3 t QA t CK t QA t QA t P t P t OH t CK t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH : L U L U 0~17 18~35 2005-11-08 15/65
(Burst Length = 4) Unidirectional /Free Running mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 4 L L U t QA t LZ t Q t CK t P t P t CK t Q t CK t QV t QV t Q t HZ t AC t AC t AC Q0 Q1 Q2 Q3 t QA t QA t QA t OH t CK t P t P t CK t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH CAS latency = 5 t CK t P t P t CK t CK L t QA t QA t LZ t Q t Q t QV t Q t QV t HZ L tac t AC t AC Q0 Q1 Q2 Q3 t QA t QA t OH t CK t CK t P t P U t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH 2005-11-08 16/65
(Burst Length = 4) Unidirectional /Free Running mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 6 L L U t QA t LZ t Q t CK t CK t Q t P t P t CK t QV t Q t QV t HZ t AC t AC t AC Q0 Q1 Q2 Q3 t QA t CK t QA t QA t P t P t OH t CK t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH : L U L 0~17 U 18~35 2005-11-08 17/65
(Burst Length = 4) Unidirectional / mode, Unidirectional /Free Running mode TC59LM836DKG-33,-40 t CH t CL t CK Input (control & addresses) t IS t IH LAL (after WRA) DESL t SS t PSTH t PRES t S CAS latency = 4 L/U CAS latency = 5 L/U t PREH t P t P t P t PST Preamble t S Postamble t PRE t t DH t t DH t t DH D0 D1 D2 D3 t SS t S t PRES t S t PSTH t t P PREH t P t P t PST Preamble Postamble t PRE t t DH t t t DH t DH D0 D1 D2 D3 t SS t SS t S CAS latency = 6 L/U t PRES t S t PSTH t PREH t P t P t P t PST Preamble Postamble t PRE t t t t DH t DH t DH D0 D1 D2 D3 t SS t SS L/U (Uni-) L/U (Free Runninig) : L U L U 0~17 18~35 2005-11-08 18/65
trefi, tpause, IXXXX t REFI, t PAUSE, I XXXX t IS t IH t IS t IH Input (control & addresses) Command Command : I XXXX I RC I RCD I RAS 2005-11-08 19/65
( : 1, 2, 3) ( : 4) 1st CS FN BA1~BA0 A13~A10 A9~A8 A7 A6~A0 DESL Device Deselect H RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA 2nd BA1~ CS FN BA0 A13~ A12 A11~ A10 A9 A8 A7 A6~A0 LAL er Address Latch H V LA REF Auto-Refresh L MRS Mode Register Set L V L L L L V V : 1. L = Logic, H = Logic High, = either L or H, V = Valid (specified value), BA = Address, UA = Upper Address, LA = er Address 2. 3. SELFX PDEX 4. 1 2 ( ) CS FN BA1~BA0 A13~A10 A9~A8 A7 A6~A0 NOTES RDA (1st) L H BA UA UA UA UA LAL (2nd) H LA ( ) CS FN BA1~ BA0 A13 A12 A11 A10 A9~A8 A7 A6~A0 WRA (1st) L L BA UA UA UA UA UA UA UA LAL (2nd) H VW0 VW1 LA : 5. A13~ A12 (VW) VW0 VW1 BL=2 Write All Words L Write First One Word H Reserved L L BL=4 Write All Words H L Write First Two Words L H Write First One Word H H 2005-11-08 20/65
( ) ( ) CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES RDA (1st) L H MRS (2nd) L V V V V V 6 : 6. PD ( ) n 1 n CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L Auto-Refresh REF (2nd) Active H H L PD ( ) n 1 n CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L Self-Refresh Entry REF (2nd) Active H L L 7, 8 Self-Refresh Continue Self-Refresh L L Self-Refresh Exit SELFX Self-Refresh L H H 9 PD ( ) n 1 n CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES Power Down Entry PDEN Standby H L H 8 Power Down Continue Power Down L L Power Down Exit PDEX Power Down L H H 9 : 7. PD REF t FPDL 8. PD 9. PD 2005-11-08 21/65
Idle ( ) PD n 1 n CS FN Row Active for Read Row Active for Write Read Write Auto-Refreshing Mode Register Accessing Power Down Self-Refreshing : H H H DESL NOP H H L H BA, UA RDA Row activate for Read H H L L BA, UA WRA Row activate for Write H L H PDEN Power Down Entry 10 H L L Illegal L Refer to Power Down State H H H LA LAL Begin Read H H L Op-code MRS/EMRS Access to Mode Register H L H PDEN Illegal H L L MRS/EMRS Illegal L Invalid H H H LA LAL Begin Write H H L REF Auto-Refresh H L H PDEN Illegal H L L REF (self) Self-Refresh Entry L Invalid H H H DESL Continue Burst Read to End H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H PDEN Illegal H L L Illegal L Invalid H H H DESL Data Write&Continue Burst Write to End H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H PDEN Illegal H L L Illegal L Invalid H H H DESL NOP Idle after I REFC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H PDEN Self-Refresh Entry 12 H L L Illegal L Refer to Self-Refreshing State H H H DESL NOP Idle after I RSC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H PDEN Illegal H L L Illegal L Invalid H Invalid L L Maintain Power Down Mode L H H PDEX Exit Power Down Mode Idle after t PDEX L H L Illegal H Invalid L L Maintain Self-Refresh L H H SELFX Exit Self-Refresh Idle after I REFC L H L Illegal 10. 11. 12. t FPDL 2005-11-08 22/65
MRS ( ) ( : 1) ADDRESS BA1 *1 BA0 *1 A13~A8 A7 *3 A6~A4 A3 A2~A0 Register 0 0 0 TE CL BT BL A7 TEST MODE (TE) A3 BURST TYPE (BT) 0 Regular (default) 0 Sequential 1 Test Mode Entry 1 Interleave A6 A5 A4 CAS LATENCY (CL) A2 A1 A0 BURST LENGTH (BL) 0 0 Reserved *2 0 0 0 Reserved *2 0 1 0 Reserved *2 0 0 1 2 0 1 1 Reserved *2 0 1 0 4 1 0 0 4 0 1 1 1 0 1 5 1 Reserved *2 1 1 0 6 1 1 1 Reserved *2 EMRS ( ) ( : 4) ADDRESS BA1 *4 BA0 *4 A13~A7 A6~A5 A4~A3 A2~A1 A0 *5 Register 0 1 0 SS DIC () DIC () A6 A5 STROBE SELECT A4 A3 A2 A1 OUTPUT DRIVE IMPEDANCE CONTROL (DIC) 0 0 Reserved *2 0 0 0 0 Normal Output Driver 0 1 Reserved *2 0 1 0 1 Strong Output Driver 1 0 Unidirectional / 1 0 1 0 Weak Output Driver 1 1 Unidirectional /Free Running 1 1 1 1 Reserved A0 DLL SWITCH () 0 DLL Enable 1 DLL Disable : 1. BA0 = 0 BA1 = 0 2. Reserved 3. A7 0 ( ) 4. BA0 = 1 BA1 = 0 5. A0 "0"( ) 2005-11-08 23/65
SELF- REFRESH POWER DOWN SELFX ( PD = H) PDEX ( PD = H) PD = L PDEN ( PD = L) PD = H STANDBY (IDLE) AUTO- REFRESH MODE REGISTER WRA RDA REF MRS ACTIVE (RESTORE) ACTIVE LAL LAL WRITE (BUFFER) READ Command input Automatic return 2 RDA WRA 1 2005-11-08 24/65
() 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 5 cycles I RC = 5 cycles I RC = 5 cycles Command RDA LAL DESL RDA LAL DESL RDA LAL DESL RDA I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles Address UA LA UA LA UA LA UA Add. #0 #0 #0 #0 Unidirectional / mode BL = 2 Q0 Q1 Q0 Q1 Q0 BL = 4 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Unidirectional /Free Running mode BL = 2 Q0 Q1 Q0 Q1 Q0 BL = 4 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 2005-11-08 25/65
(CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 6 cycles I RC = 6 cycles Command RDA LAL DESL RDA LAL DESL RDA LAL DESL I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 5 CL = 5 Q0 Q1 Q0 Q1 BL = 4 CL = 5 CL = 5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Unidirectional /Free Running mode BL = 2 CL = 5 CL = 5 Q0 Q1 Q0 Q1 BL = 4 CL = 5 CL = 5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 2005-11-08 26/65
(CL = 6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 7 cycles I RC = 7 cycles Command RDA LAL DESL RDA LAL DESL RDA LAL I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 6 CL = 6 Q0 Q1 Q0 Q1 BL = 4 CL = 6 CL = 6 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Unidirectional /Free Running mode BL = 2 CL = 6 CL = 6 Q0 Q1 Q0 Q1 BL = 4 CL = 6 CL = 6 Q0 Q1 Q2 Q3 Q0 Q1 Q2 2005-11-08 27/65
() 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 5 cycles I RC = 5 cycles I RC = 5 cycles Command WRA LAL DESL WRA LAL DESL WRA LAL DESL WRA I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles Address UA LA UA LA UA LA UA Add. #0 #0 #0 #0 Unidirectional / mode BL = 2 WL = 3 WL = 3 WL = 3 D0 D1 D0 D1 D0 D1 BL = 4 WL = 3 WL = 3 WL = 3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 WL = 3 WL = 3 WL = 3 D0 D1 D0 D1 D0 D1 BL = 4 WL = 3 WL = 3 WL = 3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 2005-11-08 28/65
(CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 6 cycles I RC = 6 cycles Command WRA LAL DESL WRA LAL DESL WRA LAL DESL I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 WL = 4 WL = 4 D0 D1 D0 D1 BL = 4 WL = 4 WL = 4 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 4 WL = 4 D0 D1 WL = 4 WL = 4 D0 D1 D2 D3 D0 D1 D0 D1 D2 D3 2005-11-08 29/65
(CL = 6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 7 cycles I RC = 7 cycles Command WRA LAL DESL WRA LAL DESL WRA LAL I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 WL = 5 WL = 5 D0 D1 D0 D1 BL = 4 WL = 5 WL = 5 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 5 WL = 5 D0 D1 D0 D1 WL = 5 WL = 5 D0 D1 D2 D3 D0 D1 D2 D3 2005-11-08 30/65
/ () 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 5 cycles I RC = 5 cycles I RC = 5 cycles Command RDA LAL DESL WRA LAL DESL RDA LAL DESL WRA Address UA LA UA LA UA LA UA Add. #0 #0 #0 #0 Unidirectional / mode BL = 2 WL = 3 Q0 Q1 D0 D1 Q0 BL = 4 WL = 3 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Unidirectional /Free Running mode BL = 2 WL = 3 Q0 Q1 D0 D1 Q0 BL = 4 WL = 3 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Read data Write data 2005-11-08 31/65
/ (CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 6 cycles I RC = 6 cycles Command RDA LAL DESL WRA LAL DESL RDA LAL DESL Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 5 WL = 4 Q0 Q1 D0 D1 BL = 4 CL = 5 WL = 4 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 CL = 5 WL = 4 Q0 Q1 D0 D1 BL = 4 CL = 5 WL = 4 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Read data Write data 2005-11-08 32/65
/ (CL = 6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RC = 7 cycles I RC = 7 cycles Command RDA LAL DESL WRA LAL DESL RDA LAL Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 6 WL = 5 Q0 Q1 D0 D1 BL = 4 CL = 6 WL = 5 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 CL = 6 WL = 5 Q0 Q1 D0 D1 BL = 4 CL = 6 WL = 5 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Read data Write data 2005-11-08 33/65
() 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cyclesi RBD = 2 cycles I RBD = 2 cycles Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA UA Add. "a" "b" "a" "b" "c" "d" "a" "b" I RC ("a") = 5 cycles I RC ("b") = 5 cycles Unidirectional / mode BL = 2 Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0Qc1 BL = 4 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Qa3 Qb0 Qb1 Qb2 Qb3Qc0Qc1Qc2 Unidirectional /Free Running mode BL = 2 Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0Qc1 BL = 4 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Qa3 Qb0 Qb1 Qb2 Qb3Qc0Qc1Qc2 : l RC 2005-11-08 34/65
(CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA Add. "a" "b" "a" "b" "c" "d" "a" I RC ("a") = 6 cycles Unidirectional / mode BL = 2 I RC ("b") = 6 cycles CL = 5 CL = 5 Qa0Qa1 Qb0Qb1 Qa0 Qa1 Qb0Qb1 BL = 4 CL = 5 CL = 5 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0 Qa1 Qa2 Qa3Qb0Qb1Qb2 Unidirectional /Free Running mode BL = 2 CL = 5 CL = 5 Qa0Qa1 Qb0Qb1 Qa0 Qa1 Qb0Qb1 BL = 4 CL = 5 CL = 5 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 : l RC Qa0 Qa1 Qa2 Qa3Qb0Qb1Qb2 2005-11-08 35/65
(CL = 6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA Address UA LA UA LA UA LA UA LA UA LA UA LA UA Add. "a" "b" "a" "b" "c" "d" "a" I RC ("a") = 7 cycles Unidirectional / mode BL = 2 I RC ("b") = 7 cycles CL = 6 CL = 6 Qa0Qa1 Qb0Qb1 Qa0Qa1 BL = 4 CL = 6 CL = 6 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Unidirectional /Free Running mode BL = 2 CL = 6 CL = 6 Qa0Qa1 Qb0Qb1 Qa0Qa1 BL = 4 CL = 6 CL = 6 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 2005-11-08 36/65
() 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA UA Add. "a" "b" "a" "b" "c" "d" "a" "b" I RC ("a") = 5 cycles I RC ("b") = 5 cycles Unidirectional / mode BL = 2 WL = 3 WL = 3 Da0 Da1 Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Dd0Dd1 BL = 4 WL = 3 WL = 3 Da0 Da1Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2Dc3Dd0Dd1 Unidirectional /Free Running mode BL = 2 WL = 3 WL = 3 Da0 Da1 Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Dd0Dd1 BL = 4 WL = 3 WL = 3 Da0 Da1Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2Dc3Dd0Dd1 : l RC 2005-11-08 37/65
(CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA Add. Unidirectional / mode BL = 2 "a" "b" I RC ("a") = 6 cycles WL = 4 WL = 4 "a" I RC ("b") = 6 cycles Da0Da1 "b" "c" "d" "a" Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1 BL = 4 WL = 4 WL = 4 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 4 WL = 4 Da0Da1 Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1 WL = 4 WL = 4 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1 : l RC 2005-11-08 38/65
(CL = 6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA Address UA LA UA LA UA LA UA LA UA LA UA LA UA Add. Unidirectional / mode BL = 2 "a" "b" I RC ("a") = 7 cycles WL = 5 WL = 5 "a" I RC ("b") = 7 cycles Da0Da1 "b" "c" "d" "a" Db0Db1 Da0 Da1 Db0Db1 BL = 4 WL = 5 WL = 5 Da0Da1Da2Da3Db0Db1Db2Db3 Da0 Da1 Da2Da3Db0Db1 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 5 WL = 5 Da0Da1 Db0Db1 Da0 Da1 Db0Db1 WL = 5 WL = 5 Da0Da1Da2Da3Db0Db1Db2Db3 : l RC Da0 Da1 Da2Da3Db0Db1 2005-11-08 39/65
/ (BL = 2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles Command WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA I WRD = 1 cycle I RWD = 2 cycles I WRD = 1 cycle I RWD = 2 cycles Address UA LA UA LA UA LA UA LA UA LA UA LA UA Add. Unidirectional / mode WL = 3 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 5 CL = 6 "a" "b" WL = 4 WL = 5 Unidirectional /Free Running mode "c" "d" I RC ("a") I RC ("b") CL = 5 CL = 6 "a" "b" "c" Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 WL = 3 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 5 CL = 6 WL = 4 WL = 5 CL = 5 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 6 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 : l RC 2005-11-08 40/65
/ (BL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I RBD = 2 cycles Command WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA I WRD = 1 cycle I RWD = 3 cycles I WRD = 1 cycle I RWD = 3 cycles I WRD = 1 cycle LAL Address UA LA UA LA UA LA UA LA UA LA UA LA Add. Unidirectional / mode CL = 5 CL = 6 "a" "b" WL = 3 WL = 4 WL = 5 "c" I RC ("a") CL = 5 CL = 6 "d" I RC ("b") "a" "b" Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2Qd3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 CL = 5 WL = 3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 WL = 4 CL = 5 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 WL = 5 CL = 6 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0Qd1 : l RC 2005-11-08 41/65
(VW) () TC59LM836DKG-33,-40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BL = 2, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL Address UA LA=#3 VW=All UA LA=#1 VW=1 VW0 = VW1 = don't care VW0 = High VW1 = don't care Add. "a" "a" BL = 4, SEQUENTIAL MODE D0 D1 er Address #3 #2 #1 (#0) D0 Last one data is masked. Command WRA LAL DESL WRA LAL DESL WRA LAL DESL Address UA LA=#3 VW=All UA LA=#1 VW=1 UA LA=#2 VW=2 VW0 = High VW1 = VW0 = High VW1 = High VW0 = VW1 = High Add. "a" "a" "a" D0 D1 D2 D3 D0 er Address #3 #0 #1 #2 #1(#2)(#3)(#0) Last three data are masked. D0 D1 #2 #3 (#0)(#1) Last two data are masked. : MRS 2005-11-08 42/65
(, BL = 4) TC59LM836DKG-33,-40 0 1 2 3 4 5 6 7 8 9 10 n-2 n-1 n n+1 n+2 I PDA Command RDA LAL DESL DESL RDA or WRA Address UA LA UA t IH t IS I PD = 2 cycle PD Unidirectional / mode t QPDH l RC(min), t REFI(max) t PDEX Q0 Q1 Q2 Q3 Unidirectional /Free Running mode Q0 Q1 Q2 Q3 Power Down Entry Power Down Exit : PD PD t REFI (max.) PD PD l PDA 2005-11-08 43/65
(, BL = 4) TC59LM836DKG-33,-40 0 1 2 3 4 5 6 7 8 9 10 n-2 n-1 n n+1 n+2 I PDA Command WRA LAL DESL DESL RDA or WRA Address UA LA UA t IH t IS I PD = 2 cycle PD WL = 3 2 clock cycles l RC(min), t REFI(max) t PDEX Unidirectional / mode WL = 3 D0 D1 D2 D3 Unidirectional /Free Running mode WL = 3 D0 D1 D2 D3 : PD LAL WL+2 PD t REFI (max.) PD PD l PDA 2005-11-08 44/65
(, BL = 2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I RSC = 7 cycles 15 Command RDA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="0" BA1="0" BA CL + BL/2 Unidirectional / mode Q0 Q1 Unidirectional /Free Running mode Q0 Q1 : RDA LAL MRS RDA CL+BL/2 2005-11-08 45/65
(, BL = 4) TC59LM836DKG-33,-40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I RSC = 7 cycles 15 Command WRA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="0" BA1="0" BA WL+BL/2 Unidirectional / mode D0 D1 D2 D3 Unidirectional /Free Running mode D0 D1 D2 D3 : WRA LAL MRS RDA WL+BL/2 2005-11-08 46/65
(, BL = 2) TC59LM836DKG-33,-40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I RSC = 7 cycles 15 Command RDA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="1" BA1="0" BA CL + BL/2 Unidirectional / mode Q0 Q1 Unidirectional /Free Running mode Q0 Q1 : RDA LAL EMRS RDA CL+BL/2 EMRS l RSC DLL EMRS DLL 2005-11-08 47/65
(, BL = 4) TC59LM836DKG-33,-40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I RSC = 7 cycles 15 Command WRA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="1" BA1="0" BA WL+BL/2 Unidirectional / mode D0 D1 D2 D3 Unidirectional /Free Running mode D0 D1 D2 D3 : WRA LAL EMRS RDA WL+BL/2 EMRS l RSC DLL EMRS DLL 2005-11-08 48/65
(, BL = 4) Unidirectional / mode 0 1 2 3 4 5 6 7 n 1 n n + 1 n + 2 I RC = 5 cycles I REFC = 19 cycles Command RDA LAL DESL WRA REF DESL RDA or WRA LAL or MRS or REF, Address, UA LA I RCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle Q0 Q1 Q2 Q3 Unidirectional /Free Running mode I RC = 5 cycles I REFC = 19 cycles Command RDA LAL DESL WRA REF DESL RDA or WRA LAL or MRS or REF, Address, UA LA I RCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle : Q0 Q1 Q2 Q3 I REFC 19 t REFI t REFI 8 t 1 t 2 t 3 t 7 t 8 WRA REF WRA REF WRA REF WRA REF WRA REF t REFI = Total time of 8 Refresh cycle 8 8 Refresh cycle t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 = 8 t REFI 2005-11-08 49/65
Unidirectional / mode 0 1 2 3 4 5 m 1 m m + 1 I RCD = 1 cycle I REFC Command WRA REF DESL t FPDL (min) t FPDL (max) Auto Refresh PD t QPDH Self Refresh Entry I *2 PDV I CKD Qx : 1. 2. PD t FPDL (min) t FPDL (max) l PDV PD t FPDL (max) l PDV 3. PD REF l CKD 4. WRA LAL REF (WL)+2 Unidirectional / mode 0 1 2 m 1 m m + 1 m + 2 n 1 n n + 1 p 1 p Command *2 I REFC I REFC Command (1st) *5 Command (2nd) *5 DESL *3 WRA *4 REF *4 DESL RDA *6 LAL *6 I RCD = 1 cycle I RCD = 1 cycle PD t PDEX I LOCK Self-Refresh Exit 2. PD : 1. 3. PD I REFC DESL 4. 5. I REFC 6. (RDA + LAL) I LOCK 2005-11-08 50/65
Unidirectional /Free Running mode 0 1 2 3 4 5 m 1 m m + 1 I RCD = 1 cycle I REFC Command WRA REF DESL PD t FPDL (min) t FPDL (max) t QPDH Auto Refresh Self Refresh Entry I *2 PDV I CKD Qx : 1. 2. PD t FPDL (min) t FPDL (max) l PDV PD t FPDL (max) l PDV 3. PD REF l CKD Unidirectional /Free Running mode 0 1 2 m 1 m m + 1 m + 2 n 1 n n + 1 p 1 p Command *2 I REFC I REFC Command (1st) *5 Command (2nd) *5 DESL *3 WRA *4 REF *4 DESL RDA *6 LAL *6 I RCD = 1 cycle I RCD = 1 cycle PD t PDEX I LOCK 2. PD Self-Refresh Exit : 1. 3. PD I REFC DESL 4. 5. I REFC 6. (RDA + LAL) I LOCK 7. DLL 2005-11-08 51/65
Network FCRAM TM FCRAM TM Fast Cycle Random Access Memory FCRAM TM : & CS FN : PD PD PD SDRAM CKE PD & : CS & FN CS FN FCRAM TM CS FN 2 : BA0 & BA1 BA0 BA1 RDA WRA (MRS EMRS) BA0 BA1 #0 0 0 #1 1 0 #2 0 1 #3 1 1 : A0~A13 RDA WRA LAL A0~A13 I/O 36 A0~A13 A0~A6 2005-11-08 52/65
: 0~35 TC59LM836DKG-33,-40 0 35 / 0 35 / : L U L U L L 0 17 U U 18 35 (1) Unidirectional / / / NOP (2) Unidirectional / Free running / / Pin to pin : VDD VD VSS VSSQ VDD VSS VD VSSQ : VREF VREF 2005-11-08 53/65
TC59LM836DKG 2 1 2 (1 + 2 = RDA + LAL) / RDA RDA ( ) LAL / ( ) LAL CAS CAS RDA lrc (1 + 2 = WRA + LAL) / WRA WRA ( ) LAL / ( ) LAL CAS 1 LAL (VW) CAS WRA lrc (1 + 2 = WRA + REF) TC59LM836DKG SDRAM WRA REF WRA WRA ( ) LAL REF lrefc 3.9µs 8 400ns 3.2µs(8 400ns) 8 (1 + 2 = WRA + REF with PD = L ) WRA REF tfpdl PD 3.9µs lrefc DESL lckd PD PD DESL High DESL lrefc lrefc 1 ( PD = L ) PD PD PD High lpda DESL 2005-11-08 54/65
(1 + 2 = RDA + MRS) TC59LM836DKG-33,-40 RDA MRS RDA RDA ( ) LAL MRS A0~A13 BA0 BA1 TC59LM836DKG MRS BA0 BA1 4 4 (R-1) (R-2) (R-3) CAS (R-4) 3 (E-1) DLL / DLL (E-2) (E-3) MRS OFF / (BA0, BA1) MRS MRS BA1 BA0 Mode Register Set 0 0 Regular MRS 0 1 Extended MRS 1 Reserved (R-1) (A2 A0) A2 A0 2 4 A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 Reserved 1 Reserved (R-2) (A3) A3 0 A3 1 2 4 A3 BURST TYPE 0 Sequential 1 Interleave 2005-11-08 55/65
(+1) CAS Latency = 4 (Free Running mode) Command RDA LAL Data 0 Data 1 Data 2 Data 3 Addressing sequence for Sequential mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n Data 1 n + 1 Data 2 n + 2 Data 3 n + 3 2 ( LA0) LA0 LA1 4 ( LA1, LA0) LA1 LA2 Addressing sequence for Interleave mode DATA ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A 0 Data 2 A8 A7 A6 A5 A4 A3 A2 A 1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A 1 A 0 2 4 (R-3) CAS (A6 A4) RDA LAL CAS LAL CAS 1 A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 Reserved (R-4) (A7) 0 (R-5) (A8 A13) 0 2005-11-08 56/65
(E-1) DLL (A0) DLL A0 0 DLL (E-2) (A1 A4) 3 A2 A1 A4 A3 A4 A3 A2 A1 OUTPUT DRIVER IMPEDANCE CONTROL 0 0 0 0 Normal Output Driver 0 1 0 1 Strong Output Driver 1 0 1 0 Weak Output Driver 1 1 1 1 Reserved (E-3) (A6 / A5) 2 (1) Unidirectional / (2) Unidirectional / Free running A6 A5 STROBE SELECT 0 0 Reserved 0 1 Reserved 1 0 Unidirectional / mode 1 1 Unidirectional /Free running mode (E-4) (A7 A13) 0 2005-11-08 57/65
IEEE 1149.1 1990 TAP (the serial boundary scan test access port) 1149.1 1990 TAP TCK VSS VDD (TCK ) TCK TMS TDI TDO TCK TAP TCK V SS V DD TCK TMS Test-Logic-Reset TDI TCK TAP TDI TDI ( ) TCK TDO IR [ 2 : 0 ] 3 5 (EXTEST Sample-Z Sample Bypass ID code). ID IDR [ 31 : 0 ] 32 Revision TOSHIBA ID BR 1 TDI TDO BSR [ 62 : 0 ] 63 (BSC) TDI TDO TAP IR2 IR1 IR0 0 0 0 EXTEST BSC 0 0 1 ID CODE ID code 0 1 0 SAMPLE Z BSC 0 1 1 RESERVED 1 0 0 SAMPLE BSC BSC 1 0 1 RESERVED 1 1 0 RESERVED 1 1 1 BYPASS TDI TDO : TDI (IR0) 2005-11-08 58/65
ID BIT # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 TOSHIBA ID BIT BIT 0 U10 35 30 B10 0 1 U11 34 31 B3 17 2 T10 33 32 B2 16 3 T11 32 33 C3 15 4 R10 31 34 C2 14 5 R11 30 35 D3 13 6 P10 29 36 7 P11 28 37 D2 12 8 N10 27 38 E3 11 9 N11 U 39 E2 10 10 M3 A4 40 F3 9 11 M11 A3 41 F2 L 12 L10 A2 42 G3 / 13 L11 A1 43 H3 14 K10 A0 44 H2 /PD 15 K11 A10 45 J2 A12 16 J10 BA1 46 J3 A11 17 J11 BA0 47 K2 A9 18 G10 A13 48 K3 A8 19 G11 FN 49 L2 A7 20 H10 /CS 50 L3 A6 21 F11 L 51 M2 A5 22 F10 8 52 N2 U 23 E11 7 53 N3 26 24 E10 6 54 P2 25 25 D11 5 55 P3 24 26 D10 4 56 R2 23 27 C11 3 57 28 C10 2 58 R3 22 29 B11 1 59 T2 21 60 T3 20 61 U2 19 62 U3 18 2005-11-08 59/65
TMS = 1 Test Logic - Reset TMS = 0 TMS = 0 TMS = 1 TMS = 1 TMS = 1 Run Test / Idle Select DR - Scan Select IR - Scan TMS = 0 TMS = 0 Capture - DR TMS = 1 Capture - IR TMS = 0 TMS = 1 TMS = 0 TMS = 0 Shift - DR Shift - IR TMS = 0 TMS = 1 TMS = 1 TMS = 1 Exit1 - DR Exit1 - IR TMS = 1 TMS = 0 TMS = 0 TMS = 0 Pause - DR Pause - IR TMS = 0 TMS = 1 TMS = 1 TMS = 0 Exit2 - DR TMS = 0 Exit2 - IR TMS = 1 TMS = 1 Update - DR Update - IR TMS = 1 TMS = 1 TMS = 0 TMS = 0 : 1. Test-Logic-Reset TMS 5 High 2. TDO (Shift-DR Shift-IR) 2005-11-08 60/65
TAP DC I LO I I V IH V IL (TDO ) (TCK TMS TDI ) (TCK TMS TDI ) (TCK TMS TDI ) 10 10 µa V OUT =0 to V DD V IN = 1.7V to V DD 20 10 µa V IN = 0 to 0.7V 100 10 µa V REF +0.4 V DD +0.2 V 0.1 V REF 0.4 V V OH V OL (TDO ) I OH = 2 ma 1.5 V DD V (TDO ) I OL = 2 ma 0.45 V TAP AC ( VDD = 2.5V ± 0.125V, VD = 1.4V ~ 1.9V, T CASE = 0 ~ 85 C) t THTH TCK 50 t THTL TCK 20 t TLTH TCK 20 t MVTH TMS 10 t THMX TMS 10 t CS 10 t CH 10 ns t DVTH TDI 10 t THDX TDI 10 t TLQV TCK 20 t TLQX TCK 0 t TLQLZ TCK 5 t TLQHZ TCK 5 2005-11-08 61/65
TAP AC TDO Z = 50 Ω 1.8V / 0.0V 2ns R L = 50 Ω V L = 0.9V 0.9V 0.9V TAP t THTH t THTL t TLTH TCK t MVTH t THMX TMS t DVTH t THDX TDI t CS t CH Capture Data t TLQLZ t TLQX t TLQV t TLQHZ TDO 2005-11-08 62/65
P-TFBGA144-1119-0.80BZ 4 0.2 SA 0.15 18.5 0.2 SB 11.0 0.2 S S 0.1 S 0.5 0.05 0.08 SAB 1.2MAX 0.4 0.05 0.15MIN INDEX A B C D E F G A H J K L M N P R T U V 0.75 0.8 B 1.1 1 2 3 4 5 6 7 8 9 10 11 12 2.0 2.0 0.5 1.0 : 0.30g ( ) 2005-11-08 63/65
Rev.1.3 (2005 3 7 ) TC59LM836DMB (2005 11 8 ) -30 ( 333MHz clock / 666Mbps )version 2005-11-08 64/65
030519TBA 2005-11-08 65/65