1
2 1997 1M SRAM 1 25 ns 1 100 250 1,000 DRAM 60 120 ns 50 5 10 50 10 20 ms 5,000,000 0.1 0.2 1
CPU 1 1 2 2 n CPU SRAM DRAM CPU 3
4
5
6
7 N+ N+ P
SRAM DRAM 8
Computer Architecture 9 DRAM 3 4
10
11 Ta 2 O 5 Capacitor Word line Bit line
International Technology Roadmap for Semiconductors 2002 12 m 5.0 Process 32G 64G Trs Process Technology 2.0 1.0 0.5 0.2 0.1 0.05 0.02 3.0 64K 2.0 256K 1.3 Memory 1M 0.8 4M 8G 4G 2G 16G 1G 4.4G 256M 2.2G 697M1.1G 64M 439M CPU 0.5 276M 0.35 16M 0.25 0.18 0.13 0.065 0.09 0.045 0.032 1G 1M 1980 1990 2000 2010 Year
13
COMS 14 20nm 280fs nm
15
16
Cache 17 CPU 000 00000 001 00001 010 00010 011 00011 100 00100 101 00101 110 00110 111 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010
31 12 11 2 1 0 31 0 30 n n 18 1024 2 10 n 10 0 1 1 20 32 1022 1023 53
19
20
21
22
23
24
25 31 16 15 2 1 0 31 16 15 4 3 2 1 0 16 14 16 12 2 1 / 4 / 1 16 3216K 1 1632 32 32 324K 49 145
26 40% 35% 30% Miss rate 25% 20% 15% 10% 5% 0% 4 16 64 256 Block size (bytes) 1 KB 8 KB 16 KB 64 KB 256 KB
27 1cyc/adr 4w/block 1cyc/w 1w/bank 15cyc/w 1+4 1+4 15=65cyc 1cyc/4w 1+1+15=17 1+4 1+15 =20
28
29