LVDS 1
( LVDS) / 50% 2
( LVDS) / 50% 3
USB2.0 480Mbps Serial ATA Gen1 1.5Gbps PCI Express Gen1 2.5Gbps 4
Host Data Device Clock 5
Data Skew Host Data Device Clock Setup Hold Data Skew 6
Host Data Device Clock Setup Hold Propagation Delay 7
EMC Current Host Data Device Clock Current 8
/ USB2.0 400mV 2,083ps 10%-90% 500ps min (0.24UI) Serial ATA 500mV 667ps 20%-80% Gen 1 100ps min 0.15UI) 273ps max PCI Express 400mV 400ps 20%-80% Gen 1 0.125UI min (50ps min) 0.2Vcc-0.6Vcc PCI 3.3V (0V-3.3V) 30,000ps 1ns min (0.033UI) 4ns max 9
Low Voltage Differential Signaling 10
90% dv/dt = 4V/ns 5V 10% 1ns dv/dt = 4V/ns 90% 10% 1V 200ps 11
dv/dt = 1.32V/ns 0.6Vcc 3.3V PCI 3.,3V 0.2Vcc 1ns dv/dt = 1.32V/ns 80% 20% 500mV Serial ATA 303ps 273psmax 111% 12
80% 90% 20% 1UI 10% PCI PCI Express Serial ATA USB2.0 13
14
(D+) 500mV (D-) 500mV (D+) (D-) -500mV 1V 500mV 15
EMI EMI Current (D+) (D-) Current LVDS 16
( LVDS) / 50% 17
/ / 18
/ 19
PCI Expres 13.2dB 0.3UI 20
Dr. Howard Johnson Signal Consulting Inc. http://www.sigcon.com/pubs/misc/mls.pdf 21
22
23
24
1 0 1 0 1 0 1 0 1 0 1 0 : 1Gbps 500MHz 1 1 0 0 1 1 0 0 1 1 0 0 250MHz 1 1 1 0 0 0 1 1 1 0 0 0 167MHz 1 -> UI :1ns 1010 25
26
0 1 0 1 0 1 0 1 0 1 1ns 2ns 500MHz 0 1 1 0 0 1 1 0 0 1 4ns 250MHz 0 0 0 1 1 1 0 0 0 1 6ns 167MHz 0 0 0 0 1 1 1 1 0 0 125MHz 8ns 27
( 50cm) 0 1 0 1 0 1 0 1 0 1 0.667 1ns 2ns 500MHz 0.769 0.814 0 1 1 0 0 1 1 0 0 1 4ns 0 0 0 1 1 1 0 0 0 1 6ns 250MHz 167MHz 0 0 0 0 1 1 1 1 0 0 0.840 125MHz 8ns 28
( 50cm) 29
LVDS (DS90LV047/048) 3.3V 30
LVDS (DS90LV047/048) 25MHz 11110000 @200Mbps 100MHz 010101 @200Mbps 50MHz 00110011 @200Mbps 2 3m 31
LVDS (DS90LV047/048) 32
LVDS (DS15BR400EVK) 3.3V 33
LVDS (DS15BR400EVK) 200MHz 750MHz 010101 @1.5Gbps 2 350MHz 00110011 @1.5Gbps 34
( LVDS) / 50% 35
36
1 1 2 37
( ) 38
( ) 39
( ) 40
41
42
One Level Eye Height Eye Amplitude Zero Level Eye Width UI 43
LVDS 44
Vmax Vmin Vnorm Jitter Tr UI 45
46
ExclusiveOR 47
PRBS3 X3+X+1 X -1 + X -1 X -1 1 1 1 + + + 1 0 0 1 1 0 0 + 1 0 0 + 0 1 1 + 1 0 0 1 1 1 1 0 0 1 0 1 48
PRBS3 X3+X+1 6 4 1 2 5 3 7 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 49
PRBS7 X7+X3+1 X -1 X -1 X -1 + X -1 X -1 X -1 X -1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 50
(2.5Gbps) 800MHz LPF 1 51
LVDS (DS15BR400EVK) 52
LVDS (DS15BR400EVK) 24 3.3V 53
LVDS (DS15BR400EVK) ( ) 54
LVDS (DS15BR400EVK) ( ) 55
LVDS (DS15BR400EVK) ( ) 56
LVDS (DS15BR400EVK) ( ) 57
LVDS (DS15BR400EVK) ( ) 1010 0101 58
Transmitter Transmitter Receiver Receiver 59
LVDS (DS15BR400EVK) ( ) 60
LVDS (DS15BR400EVK) ( ) 1010 0101 61
LVDS (DS15BR400EVK) ( ) 62
LVDS (DS15BR400EVK) ( ) 63
( LVDS) / 50% 64
( ) LVDS / LVDS 65
( ) Texas Instruments Interface Circuits for TIA/EIA-644 (LVDS) 66
/ X8 PLL 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 -> 0 1 0 1 0 -> 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 8 Serializer/Deserializer=>Serdes( ) Modulator/Demodulator=>Modem 67
P S S P 68
P S S P X PLL 69
National Semiconductors FPD Link 7 1 70
(NRZ ) 1 Setup Hold 0 1 0 1 1 0 D Q 0 1 0 1 1 0 > (D ) Setup time Hold time 71
Setup time Hold time ( ) ( ) CDR PLL(DLL) 72
PLL ( ) ( ) PLL 73
( LVDS) / 50% 74
LVDS 100 100 75
LVDS 100 100 100 100 100 100 100 76
77
o o o o = L/C) L C: R L C = V2 / V1 = o o / o o o o V V2 78
( ) / 79
( ) 50 50 100 50 2 100 100 80
PCI Express Electrical Interconnect Design Practical Solutions for Broard-level Integration and Validation INTEL PRESS www.intel.com/intelpress ISBN 0-9743649-9-1 $79.95 81
7 mils 0.1778mm 7 mils 0.1778mm r = 3.6 +/- 0.2 5 mils 0.127mm 5 mils 0.127mm 20 mils 0.508mm 5 mils 0.127mm 5 mils 0.127mm 2.0 mils +0.8/- 0.5 0.0508mm +0.02032/- 0.0127 r = 4.1 +/- 0.3 4.4 mils +/- 0.6 0.11176mm +/- 0.01524 4 82
5 mils 0.127mm 5 mils 0.127mm 5 mils 0.127mm 5 mils 0.127mm 20 mils 0.508mm 5 mils 0.127mm 5 mils 0.127mm r = 4.1 +/- 0.3 r = 4.1 +/- 0.3 6.2 mils 0.15748mm 1.3 mils 0.03302mm 6.2 mils 0.15748mm 6 83
TDR TDR DUT Z S = 50 Ω V incident V reflected + V meas - Z 0 = 50 Ω Z Load = 50 Ω TDR (20ps WaveExpert ) DUT ( ) 84
TDR V meas TDR 2(V incident ) V reflected = +V incident V incident V reflected = 0 TDR t=0 V reflected = -V incident 85
TDR : 75 TDR Module Device Under Test Z S = 50 Ω Step Generator + V meas - V incident Z 0 = 50 Ω V reflected Z Load V reflected = V incident ( Z Load Z 0 Z Load + Z 0 = V incident ( 75 50 ) 75 + 50 = V incident ( 25 ) 125 = 1 5 V incident ) 2(V incident ) V meas TDR Display V measured = V incident + V reflected = 1.2(V incident ) V incident V measured = V incident time 86
: TDR 87
88
89
90
200mil 91
PCI Express Electrical Interconnect Design Practical Solutions for Broard-level Integration and Validation Better Good AC 3 92
PCI Express Electrical Interconnect Design Practical Solutions for Broard-level Integration and Validation 93
PCI Express Electrical Interconnect Design Practical Solutions for Broard-level Integration and Validation 94
PCI Express Electrical Interconnect Design Practical Solutions for Broard-level Integration and Validation 95
100ps Gbps Zo V(t) Zo V(t) 100ps 96
EMC 97
HS 98
FS 99
( LVDS) / 50% 100
PLL LSI TTL/CMOS GND PLL LSI 101
Vdd i t t 102
GND Zanalog Zdigital Zpass 103
PLL LS I/O GND LOGIC ANALOG GND GND GND 33 F I/O Logic Analog 0 H 0.1 F GND 104
PLL LS GND LOGIC ANALOG GND I/O Logic Analog 0 H 33 F 0.1 F GND 105
LVDS LSI LVDS 106