1600 1,a) 1,b) 8080 SH-2 8080 SH-2 Simulation of a Many-Core Architecture with 16 Million Processing Cores Hisanobu Tomari 1,a) Kei Hiraki 1,b) Abstract: 8080 and SH-2 processors are evaluated as building blocks for a many-core architecture. In manycore architecture processor core designs simpler than conventional ones are often used because the number of processing elements that are integrated on a chip is limited by the size of the processor core. A many-core system design intends to maximize the throughput of instruction execution through the balance between the number of processor cores and the performance of a processor core. We put the 8080, which is one of the simplest processors, and the SH-2 pipelined processor in our many-core design to examine the optimal balance of simplicity and performance for the processor core in many-core designs. 1. [3] 1 The University of Tokyo a) tomari@is.s.u-tokyo.ac.jp b) hiraki@is.s.u-tokyo.ac.jp [4] 1 Intel Single-chip 1
Cloud[2] (48 ) Xeon Phi (50+ ) IBM Cyclops[9] (64 ) Cavium Octeon II (32 ) Tilera Tile-GX (100 ) PE [11][7] 2 Nsim[10] 8080[1] SH-2[5] SH-2 1600 70 [8] 1 2. 2.1 Processing Element (PE) PE Shuffle Exchange 1 PE 2 Pipe ( ), Rank ( ) Rank Shuffle Exchange 1 ( 1) I/O PE Shuffle Exchange hop hop Reflective Memory [6] PE PE n n 1 PE ( 2) n n + 1 PE PE 1 PE 1 PE 2 8080 SH2 8080 8 1 3 1 4 16 SH-2 32 16 1 / 8080 PE 8080 1 16 SH-2 MIPS ARM, PowerPC 32 SH 68000 16 80 SH 8080 SH-2 SH-2 GNU ROM GNU Binutils 2
Pipe 0 Pipe 1 Pipe 2 Pipe 3 Pipe 4 Pipe 5 Pipe 6 Pipe 7 rank 0 rank 1 rank 2 rank 3 rank 4 1 PE PE Address space RM_P1 RM_P2 Other PE 0000 0300 0380 Local Memory RM_IN1 RM_IN2 Mapped to local memory in PEs in the next rank Mapped to local memory 0400 4000 RM_P1 Another PE RM_P1 4080 6000 6080 RM_P2 RM_P2 8000 Config Previous rank 2 PE 3
C 8080 1 KiB SH-2 2 KiB 8080 1 128 bytes Shuffle Exchange 2 1 KiB 256 bytes SH-2 2 2.2 MAME MAME CPU PE 0 MAME CPU 8080 SH-2 1 2 S N Number of packets Synchronization bit 3 N packets follow Payload Destination Pipe ID Distasnce to the destination 4 PE SH-2 7 8080 25 PE 2 1 8080 1 KiB 3200 36 GiB SH-2 2 KiB SH-2 512 1600 50 GiB OS PE 4
Clock count 1200 800 600 400 200 0 100 5 Npipe 8080 SH-2 0 1 8080 N rank N pipe = 4 8 16 32 2 3,269 6,010 12,059 22,824 4 5,594 12,314 23,897 8 12,578 24,146 16 24,270 1 δ δ2 r(n, t) = r(n, t) (1) δt δn2 r(n, t) = (x, y, z, w) 4 3. 3.1 1 (8080 1 SH-2 1 ) ( 3) 1 PE-PE 0 ( ) 1 ( PE) PE 2 PE log 2 N pipe 3 5 8080 SH-2 Shuffle Exchange log 2 N pipe SH-2 8080 1/5 8080 5 3.2 2 x t+1 (n) = (x t (n 1) 2x t (n) + x t (n + 1))/4 (2) log 2 N pipe PE log 2 N pipe PE Algorithm 1 hop ID ( 1) log 2 N pipe 1 8080 SH2 ( 6) Routing Calc Send 5
Algorithm 1 PE loop wait(output port 0 sync bit=0) output port 0 number of packets 0 wait(output port 1 sync bit=0) output port 1 number of packets 0 for p input port 0 and input port 1 do wait(p sync bit=1) for n = 0 to p number of packets do q pointer to the head of nth packet if distance to destination in q > 0 then route this packet to output port else copy payload to static region end if end for done(input port p, sync bit 0) end for do calculation output port 0, sync bit 1 output port 1, sync bit 1 end loop Cycles Cycles/s 6000 5000 4000 3000 2000 6 0 100 Route/SH Calc/SH Route/80 Calc/80 Send Calc Routing SH-2 1/5 8080 SH-2 8080 8 SH-2 32 4 SH-2 1 16 SH-2 SH-2 4 8080 SH 1 8080 468 SH-2 624 SH-2 33% 8080 1 KiB SH-2 3.3 6 Intel Westmere (2.93 GHz) 12 8080 25 SH-2 7 SH-2 8080 1/7 ( 7) SH-2 8080 1 SH-2 2 1 8080 805 MHz SH-2 112 MHz 10 1e+06 1e+07 1e+08 PE count 7 3.4 8080 FPGA 8080 8080 6
64 FPGA Xilinx Virtex-6 XC6VLX240T-1FF1156 1 Shuffle Exchange Shuffle Exchange PE Shuffle Exchange I/O Shuffle Exchange Shuffle Exchange 4. SH-2 8080 5 8080 64 SH-2 8080 SH-2 8080 5 SH-2 FPGA MIPS 8080 2 [1] Intel Corporation. intel 8080 microcomputer systems user s manual. September 1975. [2] Jim Held. Single-chip cloud computer an experimental many-core processor from Intel Labs. Intel Labs Singlechip Cloud Computer Symposium, 2010. [3] R. Kalla, B. Sinharoy, W.J. Starke, and M. Floyd. Power7: Ibm s next-generation server processor. Micro, IEEE, 30(2):7 15, march-april 2010. [4] P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: a 32-way multithreaded sparc processor. Micro, IEEE, 25(2):21 29, march-april 2005. [5] Hitachi America Ltd. Superh risc engine sh-1/sh-2 programming manual. September 1996. [6] S. Lucci, I. Gertner, A. Gupta, and U. Hegde. Reflectivememory multiprocessor. In System Sciences, 1995. Proceedings of the Twenty-Eighth Hawaii International Conference on, volume 1, pages 85 94 vol.1, jan 1995. [7] Hisanobu Tomari. Design and evaluation of sea-of-core array architecture with 32 million processor cores. Masther Thesis, Dept. of Computer Science, the University of Tokyo, Mar. 2012. [8] M. Yokokawa, F. Shoji, A. Uno, M. Kurokawa, and T. Watanabe. The k computer: Japanese nextgeneration supercomputer development project. In Low Power Electronics and Design (ISLPED) 2011 International Symposium on, pages 371 372, aug. 2011. [9] Ying Ping Zhang, Taikyeong Jeong, Fei Chen, Haiping Wu, R. Nitzsche, and G.R. Gao. A study of the on-chip interconnection network for the ibm cyclops64 multicore architecture. In Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International, page 10 pp., april 2006. [10],,,,,, and. PSI-NSIM :. IEICE technical report. Computer systems, 107(276):45 50, 2007. [11] and.. ARC 2010-ARC-190(3), jul 2010. 7