2 Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter Literature Number: JAJSAA2
2 200KSPS 8 A/D 2 8 CMOS A/D 50kSPS 200kSPS / IN1 IN2 1 2 SPI QSPI MICROWIRE DSP 2.7V 5.25V 3V 1.6mW 5V 5.8mW 3V 0.12 W 5V 0.35 W 8 MSOP ( 40 85 ) TRI-STATE QSPI SPI ( ) 2 200KSPS 8 A/D Gary Crown 20040927 20040924 ds201248 Corrected graphics 06 and 50. GC More corrections per Nick and Stan and edit ID. GC Correct limits per Nick. GC Update to new polar format using 12-bit as axample. GC Updated timing table and "power-up" note in Section 2.0 and copied Electrical Characteristics and Typ Perf Curves from 10-bit for markup. Updated Table 3. GC Corrected Section 2.0 "rising edge of SCLK..." to "falling edge of SCLK...". GC Update tables for the clock frequencies and change for external release, remove TM on MICROWIRE, add soldering note, change AIN to IN in graphics and text. Add f SCLK Max in AC Electrical Characteristics. Changed Timing specifications for t6 and t7 to 0.3Xf SCLK instead of 0.4Xf SCLK. GC Add sample rate ranges. GC Corrections and Top Mark change. GC New data sheet copied and renamed from ds201120 which was copied from ds201042. dt 2 ( : 2.7V 5.25V) 2005 4 DNL 0.04LSB ( ) INL 0.04LSB ( ) S/N 49.6dB ( ) 3V 1.6mW ( ) 5V 5.8mW ( ) 20050427 2 200KSPS 8 A/D National Semiconductor Corporation DS201248-02-JP 1
I/O 5,4 IN1 IN2 0V V A I/O 8 SCLK 7 DOUT 6 DIN 1 CS SCLK SCLK CS CS Low 2 V A 0.1 F 1 F 2.7V 5.25V 1cm 3 GND 2
(Note 1 2) (V A ) 0.3V 6.5V GND 0.3V V A 0.3V (Note 3) 10mA (Note 3) 20mA (T A 25 ) Note 4 ESD (Note 5) 2500V 250V 150 65 150 (Note 1 2) 40 T A 85 (V A ) 2.7V 5.25V 0.3V V A 0.8MHz 3.2MHz 0V V A National Semiconductor s Reflow Temperature Profile http://www.national.com/jpn/packaging (Note 6) (Note 9) V A 2.7V 5.25V GND 0V f SCLK 0.8MHz 3.2MHz f SAMPLE 50kSPS 200kSPS C L 50pF T A T MIN T MAX T A 25 3
(Note 9) ( ) V A 2.7V 5.25V GND 0V f SCLK 0.8MHz 3.2MHz f SAMPLE 50kSPS 200kSPS C L 50pF T A T MIN T MAX T A 25 4
V A 2.7V 5.25V GND 0V f SCLK 0.8MHz 3.2MHz f SAMPLE 50kSPS 200kSPS C L 50pF T A T MIN T MAX T A 25 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: GND 0V (V IN ) (V IN GND V IN V A ) 10mA (20mA) 10mA 2 V A V A T J max( : T J max 150 ) JA ( ) T A ( ) P D MAX (T J max T A )/ JA ( ) 100pF 1.5 k220pf AOQL( ) min/max t CSU t CLH CS (HIGH LOW) 5
Operational Timing Diagram Timing Test Circuit Serial Timing Diagram SCLK and CS Timing Parameters 6
(ACQUISITION TIME) (APERTURE DELAY) 4 SCLK (CONVERSION TIME) A/D (CROSSTALK) (DIFFERENTIAL NON-LINEARITY: DNL) 1LSB (DUTY CYCLE) High SCLK (EFFECTIVE NUMBER OF BITS: ENOB) /( ) SINAD ENOB (SINAD 1.76)/6.02 A/D (FULL POWER BANDWIDTH) 3dB (GAIN ERROR) (V REF 1.5LSB) (111...110) (111...111) (INTEGRAL NON-LINEARITY: INL) ( 1/2LSB ) ( 1/2LSB ) (INTERMODULATION DISTORTION: IMD) A/D 2 2 1 2 3 IMD db (MISSING CODES) A/D (OFFSET ERROR) (GND 0.5LSB) (000...000) (000...001) / (SIGNAL TO NOISE RATIO: SNR) 1/2 DC db /( ) (SIGNAL TO NOISE PLUS DISTORTION RATIO: S/(N D) SINAD) 1/2 DC (SPURIOUS FREE DYNAMIC RANGE: SFDR) db (TOTAL HARMONIC DISTORTION: THD) 5 db dbc THD Af 1 ( ) (RMS ) Af 2 Af 6 2 6 (THROUGHPUT TIME) 2 7
T A 25 f SAMPLE 50kSPS 200kSPS f SCLK 0.8MHz 3.2MHz f IN 39.9kHz DNL - V A = 3.0V INL - V A = 3.0V DNL - V A = 5.0V INL - V A = 5.0V DNL vs. Supply INL vs. Supply 8
( ) T A 25 f SAMPLE 50kSPS 200kSPS f SCLK 0.8MHz 3.2MHz f IN 39.9kHz DNL vs. Clock Frequency INL vs. Clock Frequency DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle DNL vs. Temperature INL vs. Temperature 9
( ) T A 25 f SAMPLE 50kSPS 200kSPS f SCLK 0.8MHz 3.2MHz f IN 39.9kHz SNR vs. Supply THD vs. Supply SNR vs. Clock Frequency THD vs. Clock Frequency SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle 10
( ) T A 25 f SAMPLE 50kSPS 200kSPS f SCLK 0.8MHz 3.2MHz f IN 39.9kHz SNR vs. Input Frequency THD vs. Input Frequency SNR vs. Temperature THD vs. Temperature SFDR vs. Supply SINAD vs. Supply 11
( ) T A 25 f SAMPLE 50kSPS 200kSPS f SCLK 0.8MHz 3.2MHz f IN 39.9kHz SFDR vs. Clock Frequency SINAD vs. Clock Frequency SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle SFDR vs. Input Frequency SINAD vs. Input Frequency 12
( ) T A 25 f SAMPLE 50kSPS 200kSPS f SCLK 0.8MHz 3.2MHz f IN 39.9kHz SFDR vs. Temperature SINAD vs. Temperature ENOB vs. Supply ENOB vs. Clock Frequency ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency 13
( ) T A 25 f SAMPLE 50kSPS 200kSPS f SCLK 0.8MHz 3.2MHz f IN 39.9kHz ENOB vs. Temperature Spectral Response - 3V, 200 ksps Spectral Response - 5V, 200 ksps Power Consumption vs. Throughput 14
1.0 D/A A/D Figure 1 2 Figure 1 SW1 2 1 SW2 CS Low 3 SCLK Figure 2 SW1 SW2 1 ( ) DAC DAC CS Low 4 16 SCLK CS Low 16 SCLK DOUT DIN 2 FIGURE 1. in Track Mode FIGURE 2. in Hold Mode 2.0 CS SCLK ( ) DOUT DIN DIN CS CS 16 SCLK A/D (DOUT) CS High CS Low CS CS High SCLK 3 A/D SCLK 13 MSB 5 1 2 A/D SCLK N 16 SCLK N 16 4 SCLK / (N ) CS High SCLK CS High SCLK Low CS A/D SCLK A/D A/D SCLK SCLK High SCLK A/D CS CS 8 SCLK DIN Table 1 2 3 15
( ) CS SCLK Low SCLK DIN TABLE 1. Control Register Bits A/D IN1 TABLE 2. Control Register Bit Descriptions 7-6, 2-0 DONTC Don't care 3 ADD0 4 ADD1 3 / Table 3 5 ADD2 TABLE 3. Input Channel Selection ADD2 ADD1 ADD0 x 0 0 IN1 ( ) x 0 1 IN2 x 1 x ADD1 High D OUT 16
( ) 3.0 LSB LSB LSB V A /256 3 Figure 3 0000 0000 0000 0001 1/2 LSB V A / 512 1LSB FIGURE 3. Ideal Transfer Characteristic 4.0 Figure 4 LP2950 ( ) 4 4 DSP FIGURE 4. Typical Application Circuit 17
( ) 5.0 Figure 5 D1 D2 ESD ESD (V A 300mV) (GND 300mV) Figure 5 C1 3pF R1 / 500 C2 30pF AC 5 Power Consumption vs. Throughput 7.1 f SCLK /16 f SCLK 3.2MHz Power Consumption vs. Throughput FIGURE 5. Equivalent Input Circuit 6.0 DOUT V A SCLK CS DIN V A 7.0 CS Low CS High 16 SCLK 1 SCLK ( ) 16 SCLK CS Low 7.2 V A A/D S/N SINAD High Low 50pF A/D 100 A/D 18
inches (millimeters) 8-Lead MSOP Order Number CIMM, CIMMX NS Package Number P0MUA08A 2 200KSPS 8 A/D (CEO) (GENERAL COUNSEL) a (b) National Semiconductor Copyright 2006 National Semiconductor Corporation www.national.com 135-0042 2-17-16 / TEL.(03)5639-7300
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