ADC121S625 ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter Literature Number: JAJSAB8
ADC121S625 12 50kSPS 200kSPS A/D ADC121S625 50kSPS 200kSPS 12 A/D 500mV 2.5V 100mV 2.5V 49 V 1.22mV 2 SPI QSPI MICROWIRE DSP ADC121S625 ADC121S625 5V ADC121S625 MSOP-8 ADS7817 40 85 800kHz 3.2MHz 20050514 20041117 2005 5 ds201327 50kSPS 200kSPS AC SPI /QSPI /MICROWIRE /DSP 50kSPS 200kSPS 0.4LSB ( ) 0.05LSB ( ) INL 1LSB ( ) DNL 0.75LSB ( ) CMRR 82dB ( ) 200kSPS 2.25mW ( ) 50kSPS 1.33mW ( ) 60nW ( ) ADC121S625 ADC121S625 12 50kSPS 200kSPS A/D TRI-STATE MICROWIRE QSPI SPI ( ) 20050531 National Semiconductor Corporation DS201327-02-JP 1
ADC121S625 1 V REF 2 +IN 3 IN 4 GND 5 CS Low ADC High CS 6 D OUT CS 2 null 12 12 SCLK SCLK 7 SCLK 8 V A 2
(Note 1 2) (V A ) 0.3V 6.5V GND 0.3V (V A 0.3V) (Note 3) 10mA (Note 3) 50 ma (T A 25 ) Note 4 ESD (Note 5) 2500V 250V (CDM) 750V (10 ) (Note 6) 260 150 65 150 (Note 1 2) 40 T A 85 (V A ) 4.5V 5.5V (V REF ) 0.1V 2.5V (V CM ) Figure 1 ( 2.3) 0 V A 0.8MHz 3.2MHz V REF V REF ADC121S625 ADC121S625 (Note 8) V A 4.5V 5.5V V REF 2.5V f SCLK 0.8 3.2MHz f IN 20kHz C L 100pF T A T MIN T MAX T A 25 3
ADC121S625 ADC121S625 (Note 8) ( ) V A 4.5V 5.5V V REF 2.5V f SCLK 0.8 3.2MHz f IN 20kHz C L 100pF T A T MIN T MAX T A 25 4
ADC121S625 (Note 8) ( ) V A 4.5V 5.5V V REF 2.5V f SCLK 0.8 3.2MHz f IN 20kHz C L 100pF T A T MIN T MAX T A 25 ADC121S625 ADC121S625 (Note 8) V A 4.5V 5.5V V REF 2.5V f SCLK 0.8MHz 3.2MHz C L 100pF T A T MIN T MAX T A 25 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: GND 0V (V IN ) (V IN AGND V IN V A V D ) 10mA (50mA) 10mA 5 T J max( : T J max 150 ) JA ( ) T A ( ) P D MAX (T J max T A )/ JA ADC121S625 ( ) 100pF 1.5 k220pf AN-450 (SO) AOQL min/max t CSCR t CFCS CS Low f SCLK /16 CS f SCLK /16 5
ADC121S625 ADC121S625 Single Cycle Timing Diagram ADC121S625 Double Cycle Timing Diagram Voltage Waveform for t EN Timing Test Circuit Voltage Waveform for D OUT, t r, t f Voltage Waveform for t DIS Voltage Waveforms for d OUT delay time, t CDV 6
(APERTURE DELAY) 2 SCLK (COMMON MODE REJECTION RATIO: CMRR) CMRR 20LOG ( Common / Output) (CONVERSION TIME) A/D (DIFFERENTIAL NON-LINEARITY : DNL) 1LSB (DUTY CYCLE) High SCLK (EFFECTIVE NUMBER OF BITS: ENOB) /( ) SINAD ENOB (SINAD 1.76)/6.02 A/D (FULL POWER BANDWIDTH) 3dB (GAIN ERROR) (INTEGRAL NON-LINEARITY: INL) ( 1/2LSB ) ( 1/2LSB ) (MISSING CODES) ADC ADC121S625 (NEGATIVE FULL-SCALE ERROR) ( V REF 0.5LSB) (OFFSET ERROR) 000h 001h 1/2LSB (POSITIVE FULL-SCALE ERROR) (V REF 1.5LSB) (POWER SUPPLY REJECTION RATIO: PSRR) DC db PSRR = 20 LOG ( V A / Offset) PSRR = 20 LOG ( V A / Gain) / (SIGNAL TO NOISE RATIO: SNR) 1/2 DC db /( ) (SIGNAL TO NOISE PLUS DISTORTION RATIO: S/(N D) SINAD) 1/2 DC (SPURIOUS FREE DYNAMIC RANGE: SFDR) db (TOTAL HARMONIC DISTORTION: THD) 5 RMS RMS db dbc THD A f1 RMS A f2 A f6 5 RMS (THROUGHPUT TIME) 2 ADC121S625 7
ADC121S625 T A 25 f SAMPLE 200ksps f SCLK 3.2MHz f IN 20kHz DNL - 50 ksps INL - 50 ksps DNL - 200 ksps INL - 200 ksps DNL vs. V A INL vs. V A 8
( ) T A 25 f SAMPLE 200ksps f SCLK 3.2MHz f IN 20kHz DNL vs. f SCLK INL vs. f SCLK ADC121S625 DNL vs. SCLK DUTY CYCLE INL vs. SCLK DUTY CYCLE DNL vs. TEMPERATURE INL vs. TEMPERATURE 9
ADC121S625 ( ) T A 25 f SAMPLE 200ksps f SCLK 3.2MHz f IN 20kHz SNR vs. V A THD vs. V A SINAD vs. V A SFDR vs. V A SNR vs. V REF THD vs. V REF 10
( ) T A 25 f SAMPLE 200ksps f SCLK 3.2MHz f IN 20kHz SINAD vs. V REF SFDR vs. V REF ADC121S625 SNR vs. CLOCK FREQUENCY THD vs. CLOCK FREQUENCY SINAD vs. CLOCK FREQUENCY SFDR vs. CLOCK FREQUENCY 11
ADC121S625 ( ) T A 25 f SAMPLE 200ksps f SCLK 3.2MHz f IN 20kHz SNR vs. SCLK DUTY CYCLE THD vs. SCLK DUTY CYCLE SINAD vs. SCLK DUTY CYCLE SFDR vs. SCLK DUTY CYCLE SNR vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY 12
( ) T A 25 f SAMPLE 200ksps f SCLK 3.2MHz f IN 20kHz SINAD vs. INPUT FREQUENCY SFDR vs. INPUT FREQUENCY ADC121S625 REF. CURRENT vs. TEMPERATURE (Output = FF8h) REF. CURRENT vs. SAMPLE RATE (Output = FF8h) SUPPLY CURRENT vs. TEMPERATURE POWER DOWN CURRENT vs. TEMPERATURE 13
ADC121S625 ( ) T A 25 f SAMPLE 200ksps f SCLK 3.2MHz f IN 20kHz OFFSET ERROR vs. V REF OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. V REF GAIN ERROR vs. TEMPERATURE Spectral Response - 50 ksps Spectral Response - 200 ksps 14
ADC121S625 (SAR) A/D ADC121S625 20 ADC121S625 4.5V 5V 100mV 2.5V High Low 1 16SCLK IN IN 2 SCLK D OUT (MSB) D OUT ADC121S625 ( null ) SCLK SCLK 3.0 1.0 ADC121S625 100mV 2.5V 500mV 1LSB ( ) 1LSB 2 4096 LSB ADC121S625 AC SNR DC LSB LSB A/D ADC121S625 EMI ( ) (CS 1.5 ) "REF. CURRENT vs. SAMPLE RATE REF CURRENT vs. TEMPERATURE SNR vs. V REF " 2.0 ADC121S625 ( IN) ( IN) A/D ADC121S625 2.1 (0111 1111 1111b 7FFh) ( IN) ( IN) V REF 1.5LSB (1000 0000 0000b 800h) ( IN) ( IN) V REF 0.5LSB 2.2 ADC121S625 ( IN) 2 ( IN) 2.3 (V CM ) ADC121S625 Figure 1 Figure 2 Table 1 ADC121S625 15
ADC121S625 ( ) 1 FIGURE 1. V CM range for Differential Input operation 2 3.1 SCLK CS CS SCLK 2 CS SCLK 2 null MSB CS 3 SCLK 12SCLK D OUT (B0) CS Low "ADC121S625 Double Cycle Timing Diagram" LSB 1 B9 B10 B11 D OUT 15 CS High D OUT LSB (B0) SCLK High CS Low FIGURE 2. V CM range for single-ended operation 3.1 SCLK SCLK ( ) TTL/CMOS ADC121S625 3.2 ADC121S625 Table 2 2 TABLE 2. Ideal Output Code vs. Input Voltage TABLE 1. Allowable V CM Range 3.0 ADC121S625 3 SCLK SCLK D OUT SCLK ADC121S625 40 T A 85 4.5V V A 5.5V 0.1V V REF 2.5V 0.8MHz f CLK 4.8MHz V CM : 2.3 16
( ) 4.0 ADC121S625 200kSPS 50kSPS ADC121S625 3.2MHz f SCLK CS ADC 4.2 ADC121S625 CS 14 16 SCLK CS ( ) CS 12 CS High CMOS SCLK 1.0 CS Low CS High ADC121S625 CS High CS Low CS High 4.1 ADC121S625 CS High ADC121S625 D OUT 8 8 CS High 12 ADC121S625 12 ( 3 4 ) 1 SCLK 16 14 SCLK 14 CS High (t CYC ) 12% 4.2 SCLK 16 CS CS CS 16 SCLK CS SCLK 15 CS High Double Cycle Timing Diagram 5.0 CS SCLK SCLK High CS 1 CS SCLK SCLK Low CS 6.0 PCB SAR SCLK SCLK ADC121S625 0.1 F 1 F 10 F ADC121S625 0.1 F ADC121S625 10 ADC121S625 17
ADC121S625 ( ) 0.1 F ( ) AD121S625 SCLK High 20mA 1.5 SCLK High Low A/D ADC121S625 (50Hz 120Hz) LM4040 LM4050 LM4120 LM4121 LM4140 ADC121S625 GND 30MHz 40MHz EMI/RFI EMI/RFI GND 7.0 ADC121S625 7.1 Figure 3 3 FIGURE 3. Low cost, low power Data Acquisition System 7.2 Figure 4 AD121S625 AD121S625 150mV AD121S625 S/N A/D 3 3 7.3 Figure 5 ( ) AD121S625 ( ) ADC121S625 18
( ) 4 ADC121S625 5 FIGURE 4. Motor Control using isolated ADC121S625 FIGURE 5. Interfacing the ADC121S625 to a strain gauge 19
ADC121S625 12 50kSPS 200kSPS A/D inches (millimeters) 8-Lead MSOP 5CIMM NS Package Number MUA08A (CEO) (GENERAL COUNSEL) a (b) National Semiconductor Copyright 2006 National Semiconductor Corporation www.national.com 135-0042 2-17-16 / TEL.(03)5639-7300
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