テストコスト抑制のための技術課題－DFTとATEの観点から

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さゆりたけはな
5 years ago
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7 7 Year of Production Embedded Cores Standardization of core Standard format Standard format Standard format Extension to Extension to test data on EDA/ATE on EDA/ATE on EDA/ATE analog cores analog cores Embedded Cores: Logic Test logic insertion at RTL design Partially Partially Fully Fully Fully Fully BISR for logic cores Minimal Minimal Minimal Some Some Some Extension to analog cores Embedded Cores: Memory Embedded non-volatile memory BIST Yes Yes Yes Yes Yes Yes SoC Level Testing Fault model for SoC level Single stuck-at fault coverage fault model/ Yes Yes Yes Yes Yes transition :

8 Prober ITRS: Product family approach Logic STRJ : technology approach Memory 8

9 ITRS: Product family approach STRJ : Probe technology approach 9 Year of Production Technology Node Product family vs function and performance of Probe card hp90 I/O Pad Size (µm) X Y X Y Wirebond Bump Scrub (% of I/O) AREA DEPTH AREA DEPTH Wirebond Bump Multi-DUT Volume (% of Total Product Type Wafers Probed) Memory (DRAM) ASIC Microprocessor RF Mixed-signal Number of Probe Points /Touchdown Memory (DRAM) Signal Total Signal Total ASIC Microprocessor RF Mixed-signal Technology Node D-RAM hp (nm) Technology Node MPU (nm) Probe card (1) 1 Cantilever / Conventional Probe card (1) 2 Cantilever / HF type Minimal pitch (µ m) Maximal Pin count Multi-die test Minimal pitch (µ m) Maximal Pin count Multi-die test L.O.C Peripheral Area array L.O.C Peripheral Area array L.O.C Peripheral 4~ 8 4~ 8 4~ 8 Area array L.O.C Peripheral Area array N/A N/A N/A L.O.C. 30~100 30~100 30~100 Peripheral 60~400 60~400 60~400 Area array N/A N/A N/A L.O.C Peripheral Area array N/A N/A N/A Probe card technology vs Suitable Probe card for the arrangement bond pad of the DUT (=Function) Technology Node D-RAM hp (nm) Technology Node MPU (nm) Positional accuracy ( ± µ m : Maximal (1) - 1 Cantilever / Conventional ± 5 ± 5 (1) - 2 Cantilever / HF type ± 5 ± 5 (2) - 1 Cantilever / New generation ± 3 ± 3 (1) - 4 Membrane type (1) - 3 Vertical / Conventional ± 5 ± 5 (2) - 2 Vertical / New generation ± 3 ± 3 2. Co-planarity (µ m) : Maximal (1) - 1 Cantilever / Conventional (1) - 2 Cantilever / HF type (2) - 1 Cantilever / New generation (1) - 4 Membrane type (1) - 3 Vertical / Conventional (2) - 2 Vertical / New generation Contact Force :mn / over drive (µ m ) / pin (1mN=0.102 gf) (1) - 1 Cantilever / Conventional 50/60 50/60 (1) - 2 Cantilever / HF type 50/60 50/60 (2) - 1 Cantilever / New generation 50/60 50/60 (1) - 4 Membrane type (1) - 3 Vertical / Conventional 70/60 70/60 (2) - 2 Vertical / New generation 20/50 15/50 Probe card technology vs Performance of Probe card

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12 0.18um/400MHz/470mW (typ.) PWR CPG PWM RTC 6.5MTrs. FICP SSP CPU Max 400MHz Sound I2C GPIO I-cache D-cache 32KB 32KB USB if USB OST MMC MMC I2S DMA cnt. SDRAM Flash LCD 4 48MHz KEY UART AC97 64MB MEM Cnt. 32MB LCD Cnt. 100MHz 12

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スライド 1

スライド 1 SoC -SWG ATE -SWG 2004 2005 1 SEAJ 2 VLSI 3 How can we improve manageability of the divergence between validation and manufacturing equipment? What is the cost and capability optimal SOC test approach?