3次元LSI集積化技術

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1 3 LSI 3D LSI Integration Technology あらまし LSI 33DI LSI Si TSV Wafer on Wafer WOW 3 45 nm CMOS LSI FeRAM 10 m LSI Abstract The conventional enhancement of LSIs based on Moore s Law is approaching its limits in terms of high-speed inter-chip buses and low power consumption as well as physical limits of device operation. Three-dimensional integration (3DI) has been actively researched recently as an innovative device manufacturing technique. The technology allows for functions and performances different from those offered by the existing devices. It achieves this by stacking LSI chips and connecting between the top and bottom devices with through-silicon vias (TSVs). This paper presents the wafer-level 3D stacking technology that Fujitsu Laboratories is developing by participating in the Wafer-on-Wafer (WOW) Alliance centered on the University of Tokyo. This paper focuses on device thinning and bump-less TSV process technologies. Fujitsu has helped develop various technologies. They include ultra-thin wafer transfer technology, in which device wafers such as 45 nm CMOS logic LSIs and FeRAMs are thinned to 10 m or less for stacking. Another example is bump-less TSV technology that uses a low-temperature process of up to 200 and dual damascene method. High yield and reliability have been demonstrated and the feasibility of high-bandwidth and low-power-consumption 3D LSIs verified. FUJITSU. 62, 5, p ,

2 3 LSI まえがき LSI 22 nm 1 LSI SiP LSI Si TSV Through-Silicon-Via 3 3DI 3 Dimensional Integration 24 3DI LSI 3D TSV 3DI RC TSV LSI 図 DI LSI CPU- TSV 3DI 3DI TSV TSV 3DI Wafer on Wafer WOW 3DI 3 ウエハレベル 3 次元積層技術 WOW TSV 図 -2 BG BG UPGCMP Chemical Mechanical Polishing10 m 2 m TSV Cu TSV TSV W/Gbps/ IC L Bus L Bus L Bus G/ / -1 Fig.1-Comparison of bus power and bus band width. 602 FUJITSU. 62, 5 09, 2011

3 3 LSI 1 4 Si TSV Cu Cu 7 CMP -2 WOW Fig.2-Wafer-on-Wafer (WOW) process flow. 56 バンプレス TSV プロセス技術 LSI Cu 100 Cu TSV 52 ppm Si 2.6 ppm TSV Cu 16.6 ppm CTE Coefficient of Thermal Expansion TSV 7 TSV 5 m 図 -3 TSV TSVCu CMP 8 3DI 11/ m 55 m 1/3 2 Cu- FUJITSU. 62, 5 09,

ppm Si 5 µm Si3-400 0 20 40 60 Si µm Cu Si3 525 MPa 900 MPa -900 MPa 1000 MPa -4 TSV Fig.

4 3 LSI 195 µm 55 µm a TSV b TSV -3 TSVTSV Fig.3-Comparison of µ-bump and bump-less TSV with Si-to-Si gap. MPa TSV FEM Cu 30 µm T si 100 µm Si 100 µm MPa T si 20 µm 0 Si Cu 225 MPa Si4-200 CTE 40 ppm Si 5 µm Si Si µm Cu Si3 525 MPa 900 MPa -900 MPa 1000 MPa -4 TSV Fig.4-Via aspect ratio dependence of TSV inside stress. 1/30 I/O7.8 3 Si 10 m TSV 4Cu-TSV 100 m 525 MPa Cu 10 m 225 MPa 図 FUJITSU. 62, 5 09, 2011

3 LSI Si 7 µm NMOS 35 nm tcesl asem PMOS ccesl 35 nm SiGe-SD Ioff A/µm 10-5 10-6 10-7 10-8 10-9 10-10 NMOS Ioff A/µm 10-5 10-6 10-7 10-8 10-9 10-10 PMOS 0.4 0.6 0.8 1.0 1.2 1.4 0.0 0.2 0.4 0.6 0.8 1.0 I on ma/µm I on ma/µm b I on -I off -57 µm45-nm SEMNMOS PMOS I on -I off Fig.

5 3 LSI Si 7 µm NMOS 35 nm tcesl asem PMOS ccesl 35 nm SiGe-SD Ioff A/µm NMOS Ioff A/µm PMOS I on ma/µm I on ma/µm b I on -I off -57 µm45-nm SEMNMOS PMOS I on -I off Fig.5-Cross-sectional SEM image of 45 nm-node strained Tr after being thinned down to 7 µm and comparison of I on -I off characteristics of NMOS and PMOS FETs Cu- 6 PE-CVD Plasma-Enhanced Chemical Vapor Deposition Cu TSV 9 デバイス薄化積層技術 45 nm CMOS NCS Low-k/Cu 300 mm 10 WOW 725 m Si UPG7 m Si 図 -5 a PMOS NMOS I on I off -5 bpmos SiO 2 1/5 Cu/Low-k 200 mm FeRAM BG CMP 9 m FeRAM PZT PZT CMP 11 CMOS Back End Of Line 10 m TSV TSV 構造の信頼性評価 10 m TSV FIB- SEM Focused Ion Beam-Scanning Electron Microscope 図 -6 TSV 12 m ECD Electrochemical Deposition Cu Cu CMP FUJITSU. 62, 5 09,

3 LSI 99.99 99.9 % 99 90 251 k 31 k 0.4 µm TSV 50 10 1.1.01 0.21 m / 0 4 10 4 8 10 4 1.2 10 5-7 Cu- Fig.

6 3 LSI % k 31 k 0.4 µm TSV m / Cu- Fig.7-Via chain resistance cumulative failure distribution of Cu interconnects with and without Cu-TSVs. TC µm CuTSV Si 2 Si 1-6 TSV Fig.6-SEM image of bird s-eye view of TSVs connected with devices PE-CVD 100 nm TSV TSV 0.4 m 図 -7 TSV TSV TSV 100 Cu-TSV 3 TSV 5 V A LSI Cu- TSV 3DI むすび WOW 3 CMOS 10 m 200 Si 3 LSI 参考文献 1 H. Kitada et al. The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology Proc IITC 2007 p A. Jourdain et al. Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of 606 FUJITSU. 62, 5 09, 2011

3 LSI ICs Proc IITC 2007 p.207-209 3 F. Liu et al. A 300-mm Wafer-Level Three- Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding IEDM Tech. Dig. 2008 p.

Novel and production-worthy wafer-on-a-wafer (WOW) technology using selfaligned TSV (SALT) interconnect Proc Advanced Metallization Conf. 2008 p.91-92 6 T. Ohba et al.

Stress sensitivity analysis on TSV structure of wafer-on-a-wafer (WOW) by the finite element method (FEM) Proc IITC 2009 p.107-109 8 H. Kitada et al.

7 3 LSI ICs Proc IITC 2007 p F. Liu et al. A 300-mm Wafer-Level Three- Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding IEDM Tech. Dig p N. Miyakawa A 3D prototyping chip based on a wafer-level stacking technology Proc ASP- DAC 2009 p N. Maeda et al. Novel and production-worthy wafer-on-a-wafer (WOW) technology using selfaligned TSV (SALT) interconnect Proc Advanced Metallization Conf p T. Ohba et al. Thinned wafer multi-stack 3DI technology. Micro-electron. Eng. 87, 2010, p H. Kitada et al. Stress sensitivity analysis on TSV structure of wafer-on-a-wafer (WOW) by the finite element method (FEM) Proc IITC 2009 p H. Kitada et al. Planarization technology in the wafer level 3-dimensional integration Proc The Japan Society for Precision Engineering Invited 2009 p H. Kitada et al. Development of low temperature dielectrics down to 150 for multiple TSVs structure with Wafer-on-Wafer (WOW) technology Proc IITC 2010 p Y. S. Kim et al. Ultra Thinning 300-mm Wafer down to 7- m for 3D Wafer Integration on 45-nm Node CMOS using Strained Silicon and Cu/Low-k Interconnects IEDM Tech. Dig. (2009) p N. Maeda et al. Development of Sub 10- m Ultra-Thinning Technology using Device Wafers for 3D Manufacturing of Terabit Memory VLSI Symp p 著者紹介北田秀樹 ( きただひでき ) 3 中田義弘 ( なかたよしひろ ) 水島賢子 ( みずしまよりこ ) 3 中村友二 ( なかむらともじ ) LSI3 FUJITSU. 62, 5 09,

Table 1. Reluctance equalization design. Fig. 2. Voltage vector of LSynRM. Fig. 4. Analytical model. Table 2. Specifications of analytical models. Fig

Table 1. Reluctance equalization design. Fig. 2. Voltage vector of LSynRM. Fig. 4. Analytical model. Table 2. Specifications of analytical models. Fig Mover Design and Performance Analysis of Linear Synchronous Reluctance Motor with Multi-flux Barrier Masayuki Sanada, Member, Mitsutoshi Asano, Student Member, Shigeo Morimoto, Member, Yoji Takeda, Member