Tanner EDA Application Notes (L-Edit, DRC, LVS, SPR)

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1 Tanner EDA Web Tanner EDA Web L-Edit Windows... 4 L-Edit... 5 L-Edit ASCII DRC DRC End of Line end of line DRC LVS SPR SDF SDF SDF

2 L-Edit Windows 4. L-Edit 5. L-Edit 6. L-Edit 2

3 L-Edit 3

4 L-Edit 20 30% Tanner Pentium III CPU 1 GHz CPU 512 MB RAM 32 MB Windows NT Voodoo dfx NVIDIA DIAMOND FIRE GL 1000 PRO Windows 2000 NVIDIA GeForce2 NVIDIA Quadro2 Pro Matrox Millennium G400 NVIDIA Velocity 128 ATI RAGE 128 Windows 98 Matrox Millennium G400 Matrox Millennium G450 Intel 82810E Windows Tanner Windows 2000 Windows 98 Windows ME L-Edit [ ] [True Color (24 )] [ ] [1280 x 1024] [ ] [ ] Windows 98/ME 1. [ ] [ ] [ ] [ ] 2. [ ] [True Color (24 )] [1280 x 1024] 3. [ ] [ ] [ ] [ ] 4. [ ] [ ] 5. [ ] Windows [ ] [ ] [ ] [ ] 2. [ ] [True Color (24 )] [1280 x 1024] 3. [...] 4. [ ] 5. [ ] 4

5 L-Edit L-Edit L-Edit Rendering Application Setup 6 L-Edit Setup>Application Rendering A. Hide instance insides if less than Horizontal Vertical 5

6 L-Edit Horizontal Vertical B. Cache instances smaller than 6

7 L-Edit 1280x x C. Hide objects smaller than 3 5 D. Redraw All windows 1 Active window only Active Window only E. Fill objects when editing/drawing 1 TAB TAB Fill objects when editing/drawing F. Rendering can be interrupted and Show design while rendering L-Edit Rendering can be interrupted Showing design while rendering Rendering can be interrupted Show design while rendering first time after then every Rendering can be interrupted Show design while rendering Rendering can be interrupted 7

8 L-Edit G. Advanced Performance Settings Application Setup Advanced Performance Settings Advanced Performance Settings Use CPU for color mixing CPU L- Edit CPU Use MMX technology Use CPU for color mixing MMX technology Use MMX technology Use PatBit function for patterns L- Edit PatBit Windows Use PatBit function for patterns Default Test 10 8

9 L-Edit L-Edit Setup>Layers Rendering Outline Pattern None Pattern None Outline Style 9

10 L-Edit L-Edit 10

11 L-Edit ASCII IC X Y ASCII IC L-Edit L-Edit TDB 2. PADCELL Cell>New 3. PADCELL Cell>Instance I 4. 0,0 Edit>Edit Object(s) Ctrl-E Translation X=0.0 Y= PADXY Setup>Layers overglass Setup Layers General CIF name.xy. L-Edit CIF 11

12 L-Edit * >34.2 µm XY 12

13 L-Edit 6. Tools>Generate Layers PADXY Merge objects after generation 7. PADCELL 8. TDB File>Save 9. CIF File>Export Mask Data 13

14 L-Edit 10. CIF PADCELL PADCELL 2 X Y (SCALING: 1 CIF Unit = 1/2000 Microns); DS ; 9 padcell; L XY; X center,y center B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B , ; B ,700000; B ,700000; B ,400000; B ,400000; DF; 14

15 DRC DRC End of Line L-Edit 10 end-of-line end of line Metal1 Contact Extend Surround Metal1 Contact Metal2 Via1 end of line end of line Contact Metal1 DRC Metal1 Contact 0.25µm end of line 0.10µm Contact end of line Grow Metal1 NOT AND 15

16 DRC VERTEX 3 5 Metal1 Overlap Contact 5 16

17 DRC Contact Metal1 DRC Surround DRC end of line Not Exists DRC 17

18 DRC DRC end of line DRC Contact False Error 18

19 DRC 19

20 DRC 9 10 DRC L-Edit 10 DRC Calibre 10 9 DRC

21 DRC DRC DRC 10 DRC DRC 2 " " " " " " " " Layer 1 = Blue CUT Red Layer 2 = Blue AND NOT Layer 1 21

22 DRC 22

23 LVS 1 Vdd 1 MOSFET N Vdd 23

24 LVS " " LVS SPICE L-Edit Extract.EXT.EXT <L-Edit > samples lvs softconnect MOSIS HP 0.5 um CMOS LVS L-Edit 0 T-Spice LVS "merge parasitics" 2 ohmic well contact n well wire ndiff n well wire N N ID ohmic substrate contact subs AND pdiff subs NOT N Well Resistivity 0 24

25 LVS.EXT 2 # Well contact device = RES( RLAYER=ohmic well contact; Plus=n well wire; Minus=ndiff; MODEL=WELLCONTACT; ) # substrate contact device = RES( RLAYER=ohmic substrate contact; Plus=subs; Minus=pdiff; MODEL=SUBSCONTACT; ) n- p- 2 // Delete or comment these two connect statements #connect(n well wire, ndiff, ndiff) #connect(subs, pdiff, pdiff) 2 LVS Extract Output SPICE include statement.model SUBSCONTACT.MODEL WELLCONTACT 25

26 LVS 2 Vdd Vdd_1 M1 1 In Vdd 8 PMOS M2 Out 1 Vdd_1 8 PMOS M3 1 In Gnd 7 NMOS M4 Out 1 Gnd 7 NMOS R1 7 Gnd SUBSCONTACT 0 R2 7 Gnd SUBSCONTACT 0 R3 8 Vdd WELLCONTACT 0 R4 8 Vdd_1 WELLCONTACT 0 Vdd PMOS M1 1 In Vdd Vdd PMOS M2 Out 1 Vdd Vdd PMOS M3 1 In Gnd Gnd NMOS M4 Out 1 Gnd Gnd NMOS LVS LVS SPICE WELLCONTACT SUBSCONTACT 1. LVS 26

27 LVS Device Parameters Length and width Maximum geometric-value tolerance 5% Resistance, capacitance, and inductance values Parasitics Short out devices with model named: R_WELLCONTACT R_SUBSCONTACT LVS LVS SPICE WELLCONTACT WELLCONTACT R_WELLCONTACT SPICE Q BJT C D L J JFET Z MESFET M MOSFET R T 27

28 LVS LVS Options R_WELLCONTACT R_SUBSCONTACT LVS 1 MOSFET 2 8 R3 R4 Vdd Vdd_1 28

29 LVS LVS Vdd Vdd_1 LVS SPICE include statement.model WELLCONTACT.MODEL SUBSCONTACT Warning: Buffer.spc(46): Multiple value definitions. First definition used. 29

30 SPR SDF SDF SPR SDF SPR Elmore SPR SDF layer-to-substrate layer-to-layer <L-Edit > Samples SPR example1 SDF MOSIS Orbit 2.0 um CMOS SPR SDF 1 30

31 SPR Layer-to-substrate Setup>Layers-General Layer-to-layer Tools>SPR>Setup >Core Setup Layers 31

32 SPR SPR SPR SPR NAND SPR Block Extraction SPR 32

33 SPR Tools>Add-Ins>SDF Driver Properties>Edit Pin Characteristics 1 1 Input Output - 50% 35% 50% 65% SDF SDF None liberty liberty liberty Tools>Add-Ins>SDF Driver Properties>Import.LIB Timing Data liberty liberty TBD L-Edit direction input/output capacitance timing() - rise_resistance timing() - fall_resistance timing() L-Edit rise_resistances fall_resistances liberty Synopsys Liberty. User Guide, Volume 1 - Version , August

34 SPR 1. lightslb.tdb 2. Tools>Add-Ins>SDF Driver Properties>Import.LIB Timing Data 3. lightslb.lib 4. import SDF SPR Elmore Elmore Elmore 63.2% So Si Elmore So So Si Elmore 1 Elmore 1/2 Elmore i n Ck k 34

35 SPR SDF Nor2C Out2 4 2 Nor2 2 Nand2C 1/2 < >< > M2N1 metal 2 NOR2C_1 metal 1 N1 < >< > M2X2 metal 2 N2 NOR2_7 X2 B 35

36 SPR Elmore 36

37 SPR 37

38 SPR SDF SDF SPR SDF SDF Tools>SPR>Place and Route lights.tdb SPR SDF SPR (TIMESCALE 1ps) (CELL (CELLTYPE "Lights") (DELAY (ABSOLUTE (INTERCONNECT NOR2C_1/Out2 NAND2C_2/A ( : : ) ( : : )) (INTERCONNECT NOR2C_1/Out2 NAND2C_1/A ( : : ) ( : : )) (INTERCONNECT NOR2C_1/Out2 NOR2_2/B ( : : ) ( : : )) (INTERCONNECT NOR2C_1/Out2 NOR2_7/B ( : : ) ( : : )) ) ) ) 38

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